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Intel 855PM Chipset Platform · PDF file The Intel® Pentium® M processor, Intel® Pentium® M processor on 90nm process with 2-MB L2 Cache, Intel® Celeron® M Processor and Intel®

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  • Intel® 855PM Chipset Platform Design Guide

    For use with Intel® Pentium® M and Intel® Celeron® M Processors May 2004 Revision Number 003

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    Document Number: 252614-003

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    2 Intel® 855PM Chipset Platform Design Guide

    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

    Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers’ system designs, nor is Intel responsible for ensuring that its customers’ products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel’s customers, and Intel’s customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics.

    Intel may make changes to specifications and product descriptions at any time, without notice.

    Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

    The Intel® Pentium® M processor, Intel® Pentium® M processor on 90nm process with 2-MB L2 Cache, Intel® Celeron® M Processor and Intel® 855PM Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

    Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

    Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

    Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

    Intel Corporation

    www.intel.com

    or call 1-800-548-4725

    Intel, the Intel logo, Pentium, Celeron, Intel SpeedStep, and Intel Centrino are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries.

    *Other brands and names are the property of their respective owners.

    C i ht © I t l C ti 2003 2004

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    Intel® 855PM Chipset Platform Design Guide 3

    Contents

    1. Introduction .................................................................................................................................19 1.1. Terminology ...................................................................................................................19 1.2. Referenced Documents .................................................................................................21

    2. System Overview........................................................................................................................23 2.1. Intel® CentrinoTM Mobile Technology Features..............................................................23 2.2. Intel® Pentium® M Processor/Intel® Celeron® M Processor ............................................25

    2.2.1. Architectural Features ....................................................................................25 2.2.1.1. Packaging/Power ............................................................................25

    2.3. Intel 855PM Memory Controller Hub (MCH)..................................................................25 2.3.1. Front Side Bus Support..................................................................................25 2.3.2. Integrated System Memory DRAM Controller................................................26 2.3.3. Accelerated Graphics Port (AGP) Interface...................................................26 2.3.4. Packaging/Power ...........................................................................................26

    2.4. Intel 82801DBM I/O Controller Hub (ICH4-M) ...............................................................27 2.4.1. Packaging/Power ...........................................................................................27

    2.5. Intel PRO/Wireless Network Connection.......................................................................27 2.5.1. Packaging and Power ....................................................................................28

    2.6. Firmware Hub (FWH).....................................................................................................28 2.6.1. Packaging/Power ...........................................................................................28

    3. General Design Considerations .................................................................................................29 3.1. Nominal Board Stack-Up ...............................................................................................29

    4. FSB Design Guidelines ..............................................................................................................33 4.1. FSB Design Recommendations.....................................................................................33

    4.1.1. Recommended Stack-up Routing and Spacing Assumptions .......................33 4.1.1.1. Trace Space to Trace – Reference Plane Separation Ratio ..........33 4.1.1.2. Trace Space to Trace Width Ratio..................................................34 4.1.1.3. Recommended Stack-up Calculated Coupling Model ....................34 4.1.1.4. Signal Propagation Time to Distance Relationship

    and Assumptions.............................................................................35 4.1.2. Common Clock Signals..................................................................................36 4.1.3. Source Synchronous Signals.........................................................................41

    4.1.3.1. Source Synchronous General Routing Guidelines .........................41 4.1.3.2. Source Synchronous – Data ...........................................................43 4.1.3.3. Source Synchronous – Address .....................................................44 4.1.3.4. Source Synchronous Signals Recommended Layout Example .....45 4.1.3.5. Trace Length Equalization Procedures...........................................50

    4.1.4. Asynchronous Signals....................................................................................51 4.1.4.1. Topologies.......................................................................................51

    4.1.4.1.1. Topology 1A: Open Drain (OD) Signal Driven by the Processor – IERR# .......................................................52

    4.1.4.1.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor – FERR# and THERMTRIP#.......................53

    4.1.4.1.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor – PROCHOT#..............................................54

    4.1.4.1.4. Topology 2A: Open Drain (OD) Signal Driven by Intel 82801DBM ICH4-M – PWRGOOD...............................55

    4.1.4.1.5. Topology 2B: CMOS Signals Driven by Intel 82801DBM ICH4-M – DPSLP#........................................................56

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    4 Intel® 855PM Chipset Platform Design Guide

    4.1.4.1.6. Topology 2C: CMOS Signals Driven by Intel 82801DBM ICH4-M – LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# ......................................... 58

    4.1.4.1.7. Topology 3: CMOS Signals Driven by Intel 82801DBM ICH4-M to Processor and FWH – INIT#....................... 59

    4.1.4.2. Voltage Translation Logic ............................................................... 60 4.1.5. Processor RESET# Signal ............................................................................ 60

    4.1.5.1. Processor RESET# Routing Example............................................ 62 4.1.6. Processor and Intel 855PM MCH Host Clock Signals .................................. 63 4.1.7. GTLREF Layout and Routing Recommendations ......................................... 65 4.1.8. AGTL+ I/O Buffer Compensation .................................................................. 69

    4.1.8.1. Processor AGTL+ I/O Buffer Compensation .................................. 69 4.1.8.2. Intel 855PM MCH AGTL+ I/O Buffer Compensation...................... 71

    4.1.9. Processor FSB Strapping .............................................................................. 73 4.1.10. Processor VCCSENSE/VSSSENSE Design Recommendations.............................. 75

    4.2. Intel System Validation Debug Support ....................................................................

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