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MicroBoardのSPI ROMから MicroBlazeのプログラムを 読んで起動する話 イーツリーズ/わさらぼ 三好 健文

Microblaze loader

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  • MicroBoardSPI ROMMicroBlaze

    /

  • 1) MicroBlaze

    BlockRAM/2)

    ROM3) MicroBoardQSPI FlashROM4) Xilinx AR#55026SPI5) MicroBoard

  • 1) MicroBlaze2) QSPI3) HDL#HOLD4) UCF5) 6) BlockRAM7) 8) MCS

  • MicroBlaze/ ISE BSB

    66.666667MHz CPU66MHz

    DDR3(LPDDR) LED(GPIO) DIP(GPIO) UART(115200)

  • MicroBlaze(1)ISENew Source

    New SourceEmbedded Processor

    XPSBSB WizardYES

  • MicroBlaze(2)PLBAXI()

    66.666667MHzActive HIGH

    CPU66MHz

    MCB_DDR3 LED(GPIO, 4bit) DIP(GPIO, 4bit) UART(115200, Interrupt)

  • MicroBlaze(3)

    LEDDIP8bit4bit([0:3])

    BSB4bit[0:7][0:3]

    clock_generator_0_CLKIN_pin

  • MicroBlaze(4) MIG

    DDR3LPDDR MT46H32M16XXXX-5 OK

    MCB_DDR3MIG

    LPDDRMT46H32M16XXXX-5

  • MicroBlaze(5) 200MHz

    clock_generator_0

    600MHz

    200MHz

  • MicroBlaze(6) RAM32KB

    microblaze_0_d_bram_ctrlmicroblaze_0_i_bram_ctrl

    LMB BRAM High Address0x00007fff

    Addresses

  • QSPI ROM/ IP CatalogAXI Quad SPI Interface FIFO Depth16SCK Ratio2 microblaze_0(CPU) CLKOUT2 Netlist

  • QSPI ROM(1)

    AXI Quad SPI InterfaceIP

    QSPI_FLASH()

    microblaze_0() (QSPI_FLASH)

    FIFO Depth=16SCK Ratio=2

  • QSPI ROM(2) SPICLKOUT2 IO

    Ports - EXT_SPI_CLKclock_generator_0CLKOUT2 - SCK, SS, IO0, IO1, SPISEL

    Netlist

  • HDL/ ISEHDL SSEL'1' #HOLD'1'

    Embedded Processor

    Create top HDL Source

    (VHDL)

  • HDL(1) SSEL'1'

    QSPI_FLASH_SPISEL_pin port map QSPI_FLASH_SPISEL_pin => '1',

    #HOLD'1' QSPI_FLASH_HOLD : out std_logic QSPI_FLASH_HOLD

  • UCF

    NET RS232_Uart_1_sout LOC = T7 | IOSTANDARD = LVCMOS33;NET RS232_Uart_1_sin LOC = R7 | IOSTANDARD = LVCMOS33;NET RESET LOC = V4 | IOSTANDARD = LVCMOS33 | TIG | PULLDOWN;NET LEDS_TRI_O LOC = P4 | IOSTANDARD = LVCMOS18;NET LEDS_TRI_O LOC = L6 | IOSTANDARD = LVCMOS18;NET LEDS_TRI_O LOC = F5 | IOSTANDARD = LVCMOS18;NET LEDS_TRI_O LOC = C2 | IOSTANDARD = LVCMOS18;NET DIP_Switches_TRI_I LOC = B3 | IOSTANDARD = LVCMOS33;NET DIP_Switches_TRI_I LOC = A3 | IOSTANDARD = LVCMOS33;NET DIP_Switches_TRI_I LOC = B4 | IOSTANDARD = LVCMOS33;NET DIP_Switches_TRI_I LOC = A4 | IOSTANDARD = LVCMOS33;NET clock_generator_0_CLKIN_pin LOC = K15 | IOSTANDARD = LVCMOS33;NET QSPI_FLASH_SCK_pin LOC = R15 | IOSTANDARD = LVCMOS33;NET QSPI_FLASH_SS_pin LOC = V3 | IOSTANDARD = LVCMOS33;NET QSPI_FLASH_IO0_pin LOC = T13 | IOSTANDARD = LVCMOS33;NET QSPI_FLASH_IO1_pin LOC = R13 | IOSTANDARD = LVCMOS33;

    NET QSPI_FLASH_HOLD LOC = V14 | IOSTANDARD = LVCMOS33;

    NET "clock_generator_0_CLKIN_pin" TNM_NET = clock_generator_0_CLKIN_pin;TIMESPEC TS_clock_generator_0_CLKIN_pin = PERIOD clock_generator_0_CLKIN_pin 66666 kHz;

    ### Set Vccaux for S6LX9 MicroBoard to 3.3V ###CONFIG VCCAUX = "3.3" ;

  • Xilinx #AR55026

    REST_SECTION_BYTE_NUM

    DDR xparameters.h XPAR_DDR3_SDRAM_S_AXI_BASEADDR

    XPAR_MCB_DDR3_S0_AXI_BASEADDR BRAM

    lscript.ld

  • SPI SPIDDR

    DDR(

    )

  • ().../* * Read the rest_section data from flash. */for(i=0; i

  • BlockRAM data2mem SDKelfGenerate Programming FileOK

    elf

    Generate Programming File?elf!!

    data2membit!!

  • /

    (0x00000000-0x0000004f) (DDR)

  • (1)

    C:\WORK\images>mb-objcopy -O binary -j .vectors.reset ^ -j .vectors.sw_exception -j .vectors.interrupt -j .vectors.hw_exception ^ user_application.elf vector_section.bin

    ISE

    rest_section.binbootloader.cREST_SECTION_BYTE_NUM

    C:\WORK\images> mb-objcopy -O binary -R .vectors.reset ^ -R .vectors.sw_exception -R .vectors.interrupt -R .vectors.hw_exception ^ user_application.elf rest_section.bin

  • (2)

  • MCS/ FPGAbit

    MCS FPGAbit0 0xb00000 0xc0000 bootloader.c

    iMPACTOK

  • MCS(1)

    C:\WORK\images>promgen -spi ^ -w -p mcs -u 0 download.bit ^ -data_file up b00000 rest_section.bin^ -data_file up c00000 vector_section.bin

    ROM

  • AR#55026MicroBlaze !! ISE

    Spartan6

    SDKS

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