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Microblaze Soft Processor Core 32-bit Harvard RISC architecture Performance Feature Cost Easy-to use Area-efficient Optimized for cost-sensitive designs Able to give support into the future solution

Microblaze Soft Processor Core

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Microblaze Soft Processor Core. 32-bit Harvard RISC architecture Performance Feature Cost Easy-to use Area-efficient Optimized for cost-sensitive designs Able to give support into the future solution. Microblaze's Features. Cost-efficient, high performance 32-bit soft processor - PowerPoint PPT Presentation

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Page 1: Microblaze Soft Processor Core

Microblaze Soft Processor Core

32-bit Harvard RISC architecture Performance Feature Cost Easy-to use Area-efficient Optimized for cost-sensitive designs Able to give support into the future solution

Page 2: Microblaze Soft Processor Core

Microblaze's Features

Cost-efficient, high performance 32-bit soft processor

Optimized for Xilinx FPGAs Highly configurable feature set Co-processor interface for hardware

acceleration Fully supported by the Platform Studio

embedded development environment JTAG-based integrated debug support Optional integrated single precision FPU

Page 3: Microblaze Soft Processor Core

Picoblaze

Cost-effective fully embedded 8-bit RISC microcontroller core

Optimized for the Virtex and Spartan series of FPGAs and CoolRunner-II CPLDs

Provided as a free, source-level VHDL file with royalty-free re-use within Xilinx FPGAs.

Cost-efficient microcontroller-based control and simple data processing.

Page 4: Microblaze Soft Processor Core

Picoblaze's Features

16 byte-wide general-purpose data registers 1K instructions of programmable on-chip

program store, automatically loaded during FPGA configuration

Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags

64-byte internal scratchpad RAM 256 input and 256 output ports for easy

expansion and enhancement Automatic 31-location CALL/RETURN stack

Page 5: Microblaze Soft Processor Core

Picoblaze's Features (Cont.)

Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-4™ FPGA and 88 MHz or 44 MIPS in a Spartan-3 FPGA

Fast interrupt response; worst-case 5 clock cycles

Assembler, instruction-set simulator support

Page 6: Microblaze Soft Processor Core

PicoBlaze Microcontroller Embedded within an FPGA

Optimal Balance between Microcontroller and FPGA Solutions

Page 7: Microblaze Soft Processor Core

MicroBlaze Hardware Options and Configurable Blocks

Hardware Functions Hardware Barrel Shifter Hardware Divider Machine Status Set and Clear Instructions Hardware Exception Support Processor Version Register Floating-Point Unit (FPU) Hardware Multiplier Hardware Debug Logic

Page 8: Microblaze Soft Processor Core

MicroBlaze Hardware Options and Configurable Blocks (Cont.)

Cache Options Configurable size 2kB - 64 kB Configurable micro-cache size 64B – 1024B 4 or 8 word cache lines Bus Infrastructure On-Chip Peripheral Bus (OPB) for interfacing to

peripherals Local Memory Bus (LMB) for fast local access memory Fast Simplex Link (FSL) for interfacing to co-

processors

Page 9: Microblaze Soft Processor Core

MicroBlaze Architecture

32 general-purpose registers An Arithmetic Logic Unit (ALU) A shift unit Two levels of interrupt It can be configured this basic design with more

advanced features to allow the user to balance the required performance of the target application against the logic area cost of the soft processor.

Page 10: Microblaze Soft Processor Core

MicroBlaze Architecture (Cont.)

Page 11: Microblaze Soft Processor Core

MicroBlaze Block Diagram

Page 12: Microblaze Soft Processor Core

Microblaze - Data Types and Endianness

Uses Big-Endian bit-reversed format to represent data.

Hardware supported data types: Word Half word Byte

Page 13: Microblaze Soft Processor Core

Microblaze - Data Types and Endianness (Cont.)

Word Data Type

Half Word Data Type Byte Data Type

Page 14: Microblaze Soft Processor Core

Microblaze - Instructions

Instructions are 32 bits defined as either Type A or Type B

Type A

Have up to two source register operands and one destination register operand

Page 15: Microblaze Soft Processor Core

Microblaze – Instructions (Cont.)

Type B

Have one source register and a 16-bit immediate operand

can be extended to 32 bits by preceding the Type B instruction with an IMM instruction

Have a single destination register operand

Page 16: Microblaze Soft Processor Core

add - Arithmetic Add (Microblaze's Instruction)

add rD, rA, rB Addaddc rD, rA, rB Add with Carryaddk rD, rA, rB Add and Keep Carryaddkc rD, rA, rB Add with Carry and Keep Carry

Pseudocode:if C = 0 then

(rD) ←(rA) + (rB)else

(rD) ← (rA) + (rB) + MSR[C]if K = 0 then

MSR[C] ← CarryOut

Registers Altered:rDMSR[C]

Latency:1 cycle

Page 17: Microblaze Soft Processor Core

bne - Branch if Not Equal (Microblaze's Instruction)

bne rA, rB Branch if Not Equalbned rA, rB Branch if Not Equal with Delay

Pseudocode:If rA ≠ 0 then

PC ←PC + rBelse

PC ←PC + 4if D = 1 then

allow following instruction to complete execution

Latency:1 cycle (if branch is not taken)2 cycles (if branch is taken and the D bit is set)3 cycles (if branch is taken and the D bit is not set)

Registers Altered:PC

Page 18: Microblaze Soft Processor Core

Microblaze - Registers

General Purpose Registers 32-bit General Purpose Registers numbered R0

through R31. Special Purpose Registers

Program Counter (PC) Machine Status Register (MSR) Exception Address Register (EAR) Exception Status Register (ESR) Branch Target Register (BTR) Floating Point Status Register (FSR) Processor Version Register (PVR)

Page 19: Microblaze Soft Processor Core

MicroblazePipeline Architecture

Three Stage Pipeline When area optimization is enabled, the pipeline is

divided into three stages to minimize hardware cost: Fetch, Decode, and Execute.

Page 20: Microblaze Soft Processor Core

MicroblazePipeline Architecture (Cont.)

Five Stage Pipeline When area optimization is disabled, the pipeline is

divided into five stages to maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and Writeback (WB).

Page 21: Microblaze Soft Processor Core

MicroblazePipeline Architecture (Cont.)

Branches The instructions in the fetch and decode stages (as

well as prefetch buffer) are flushed when executing a taken branch. The fetch pipeline stage is then reloaded with a new instruction from the calculated branch address. A taken branch in MicroBlaze takes three clock cycles to execute, two of which are required for refilling the pipeline. To reduce this latency overhead, MicroBlaze supports branches with delay slots.

Page 22: Microblaze Soft Processor Core

Microblaze - Reset, Interrupts, Exceptions, and Break

ResetEquivalent Pseudocode

PC ← 0x00000000MSR ← C_RESET_MSREAR ← 0ESR ← 0FSR ← 0

Hardware ExceptionsEquivalent Pseudocode

ESR[DS] ← exception in delay slotif ESR[DS] then

BTR ← branch target PCr17 ← invalid value

elser17 ← PC + 4

PC ← 0x00000020MSR[EE] ← 0MSR[EIP]← 1ESR[EC] ← exception specific valueESR[ESS]← exception specific valueEAR ← exception specific valueFSR ← exception specific value

Page 23: Microblaze Soft Processor Core

Microblaze - Reset, Interrupts, Exceptions, and Break

Breaks There are two kinds of breaks:

1.Hardware (external) breaks 2.Software (internal) breaks

Equivalent Pseudocoder16 ← PCPC ← 0x00000018MSR[BIP] ← 1

Page 24: Microblaze Soft Processor Core

Microblaze - Reset, Interrupts, Exceptions, and Break

InterruptEquivalent Pseudocode

r14 ← PCPC ← 0x00000010MSR[IE] ← 0

User Vector (Exception)Pseudocode

rx ← PCPC ← 0x00000008

Interrupt and Exception Handling

Page 25: Microblaze Soft Processor Core

Microblaze - Instruction Cache Optional instruction cache for improved

performance when executing code that resides outside the LMB address range.

The instruction cache has the following features:

Direct mapped (1-way associative) User selectable cacheable memory address range Configurable cache and tag size Caching over CacheLink (XCL) interface Option to use 4 or 8 word cache-line Cache on and off controlled using a bit in the MSR Optional WIC instruction to invalidate instruction

cache lines

Page 26: Microblaze Soft Processor Core

Microblaze - Data Cache Optional data cache for improved performance.

The cached memory range must not include addresses in the LMB address range.

The data cache has the following features Direct mapped (1-way associative) Write-through User selectable cacheable memory address range Configurable cache size and tag size Caching over CacheLink (XCL) interface Option to use 4 or 8 word cache-lines Cache on and off controlled using a bit in the MSR Optional WDC instruction to invalidate data cache

lines

Page 27: Microblaze Soft Processor Core

PicoBlaze™ 8-bit Embedded Microcontroller's Block Diagram

Page 28: Microblaze Soft Processor Core

PicoBlaze - Instruction Set

Processing Data All data processing instructions operate on any of

the 16 general-purpose registers The data processing instructions consists of the

following types: Logic instructions Arithmetic instructions Test and Compare instructions Shift and Rotate instructions

Page 29: Microblaze Soft Processor Core

PicoBlaze - Instruction Set (Cont.)

Logic Instructions : Bitwise logical AND, OR, or XOR between two

operands. The first operand is a register location The second operand is either a register location or

a literal constant Besides performing pure AND, OR, and XOR

operations, the logic instructions provide a means to:

complement or invert a register clear a register set or clear specific bits within a register

Page 30: Microblaze Soft Processor Core

PicoblazeBitwise AND, OR, XOR

Bitwise AND, OR, XOR All logic instructions are bitwise operations

The OR and XOR instructions are similar to the AND instruction illustrated in the figure above except that they perform an OR or XOR logical operation, respectively

Page 31: Microblaze Soft Processor Core

PicoblazeComplement/Invert Register

PicoBlaze microcontroller does not have a specific instruction to invert individual bits within register sX. However, the XOR sX,FF instruction performs the equivalent operation, as shown in the figure below

Complementing a Register Value

Does not have a specific instruction to invert or toggle an individual bit or bits within a specific register. However, the XOR instruction performs the equivalent operation

Inverting an Individual Bit Location

Page 32: Microblaze Soft Processor Core

Third Party Real Time Operating Systems (RTOS) Support

About lacking a Memory Management Unit, and thus unable to run full Linux, several operating systems have been ported to the MicroBlaze including µClinux and FreeRTOS

Page 33: Microblaze Soft Processor Core

ARM Comparison Xilinx’s MicroBlaze soft core is similar to

Altera’s Nios II Sharing many of the same advantages and

disadvantages Nios II, designed specifically for FPGA

integration It runs at 140–180MHz in a fast Stratix or Stratix II

device Is a 32-bit RISC processor with a deeper pipeline

than the ARM7TDMI It has additional advantages: dynamic or static

branch prediction Configurable instruction and data caches An extendable instruction set

Page 34: Microblaze Soft Processor Core

ARM Comparison

Nios II has two disadvantages All instructions are 32 bits long

the ARM7TDMI has 16-bit Thumb instructions for greater code density

It’s a proprietary Altera architecture not the industry-standard ARM architecture.