of 39/39
FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Embedded Design with the MicroBlaze Soft Processor Core

Embedded Microblaze

  • View
    9

  • Download
    3

Embed Size (px)

DESCRIPTION

MicroBlaze Aplication

Text of Embedded Microblaze

[Sample Course Title Slide Insert Presentation Title]© 2009 Xilinx, Inc. All Rights Reserved
Embedded Design with the MicroBlaze Soft Processor Core
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Welcome
If you are new to Embedded design with Xilinx FPGA’s, this module will explain why you may want to use the MicroBlaze soft processor core in any of our FPGA families
Understanding the basics of MicroBlaze is important if you are going to take full advantage of its features
The Embedded Developers Kit software (EDK) is designed to make building a fast embedded design easy
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
After completing this module…
Explain some of the benefits of MicroBlaze processor
Explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for MicroBlaze
Explain how the Base System Builder makes it easy to build your embedded system
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Hardware Overview
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Xilinx Embedded Processor Innovation
PowerPC 440
PowerPC® 405
Hard Core
2000
2002
2004
2008
2006
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Supported FPGAs
FPGA families
Spartan-6 (MicroBlaze Processor)
Virtex-4 FX (MicroBlaze and PowerPC 405 processors) and LX/SX FPGA (MicroBlaze processor)
Virtex-5 FXT (MicroBlaze and PowerPC 440 processor) LX/LXT FPGA (MicroBlaze)
Virtex-6 (MicroBlaze processor)
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Embedded Design in an FPGA
Embedded design in an FPGA can consist of the following
FPGA hardware design
PLB bus components
Other FPGA hardware
Peripherals can either be custom made by the user with a Xilinx bus interface or a library of pre-optimized peripherals are available
Typically the FPGA contains logic that can be unrelated to the processor component of the design. This is part of the system-on-chip or single chip architecture concept.
Xilinx can support multiple processor instances. Each processor instance will have its own software platform that may or may not include a third-party operating system, such as Linux, or one of the many Real-Time Operating Systems (RTOS).
A software platform that does not include an OS will use the Xilinx Standalone platform that provides the basic software services.
The user software application is written from the aspect of main and performs the desired function.
Interrupt service routines may be part of the user application.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor-Based Embedded Design
PLB v46
Because the MicroBlaze processor is a soft-logic processor, it runs on all current FPGA families.
Caches: With the MicroBlaze processor, you can select whether to use an instruction cache and a data cache and their sizes. FPGA block RAM is used for these caches.
Local Memory Bus (LMB): The MicroBlaze processor has a 32-bit LMB that is used for low-latency access to on-chip block RAM. The LMB provides single-cycle access to on-chip, dual-port block RAM and is split into instruction-side LMB and data-side LMB.
Off-Chip Memory: The MicroBlaze processor includes a tightly coupled, off-chip Flash/SRAM/DDR2 memory controller interface to provide high-speed, low-latency access, called CacheLink. The CacheLink interface implements the cache function without tying up the PLB v46 bus. This is similar to the Fast Simplex Link (FSL).
Fast Simplex Link (FSL): The MicroBlaze processor contains zero to sixteen input and output Fast Simplex Link interfaces.
The FSL channels are dedicated, unidirectional, point-to-point data-streaming interfaces. The FSL interfaces on the MicroBlaze processor are 32-bits wide.
In addition, the same FSL channels can be used to transmit or receive either control or data words. A separate bit indicates whether the transmitted (received) word is control or data information.
There are two cycle-assembly instructions: get and put. Wrapping this into custom C functions with appropriate custom hardware also provides an optimal method by which you can implement custom instructions for the processor.
PLB v46: The MicroBlaze and PPC 440 processor both use the PLB v46 bus. The same peripherals that work on the PLB v46 with the PowerPC processor can also be used with the MicroBlaze processor.
PPC processor: In the figure, both processors have been connected to the same slave PLB v46. This allows less critical functions to be ported off to the MicroBlaze processor, and the most timing critical to be ported to the PPC processor on the master PLB v46 bus.
In this particular scenario, the MicroBlaze processor will have access to PowerPC 440 processor MCI memory and the MPLB peripherals.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
IP Peripherals
Debug
Peripherals
Arithmetic
Timers
Fabric Co-processor Bus (FCB)
Fast Simplex Link (FSL)
DCR bridge and bus
Memory and memory controller cores
Block RAM (PLB v46/LMB)
Multi-port memory controller (SDRAM, DDR, DDR2)
Multi-channel external memory controller (SRAM, FLASH)
System ACE™ interface controller (Compact Flash)
Debug
MicroBlaze Debug Module (MDM)
Hard-core tri-mode Ethernet MAC
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Hardware Overview
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor Block Diagram
Hardware features of the MicroBlaze processor, shown in gray, are optionally generated in FPGA fabric.
ALU:
Barrel shifter
Supports addition, subtraction, multiplication, division, and comparison
IEEE754-compatible, single-precision floating point
Floating point instructions part of the MicroBlaze processor instruction set
Fully supported by compiler, tools, and an Instruction Set Simulator (ISS)
Pattern-compare instructions for optimized comparisons
MMU support for operating systems
Caching for off-FPGA memory resources
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor Basic Architecture
Embedded soft RISC processor
32-bit instruction word (three operands and two addressing modes)
32 registers (32-bit wide)
Three or five pipeline stages (three stages if area optimization is selected)
Big-endian format
PLB v46 (CoreConnect bus architecture standard), instruction, and data (user selectable)
LMB for connecting to local block RAM (faster), instruction, and data (user selectable)
Fast Simplex Links: dedicated, unidirectional point-to-point data streaming interfaces; support for up to 16 FSLs
Dedicated CacheLink ports for instruction and data caching with four-word cache line size and critical word-first access capability
The MicroBlaze embedded soft core processor includes the following features, some of which are optionally selected:
Thirty-two 32-bit general-purpose registers
Thirty-bit instruction word with three operands and two addressing modes
Separate 32-bit instruction and data buses that conform to the IBM PLB bus standard
Separate 32-bit instruction and data buses with direct connection to on-chip RAM through an LMB
32-bit address bus
Fast Simplex Link support
Instruction and data caching is allowed on CacheLink
Note that you are not required to use both D/I of the LMP or the D/I of the PLB. They are all selectable by function and allow you to optimize your system to just what hardware that you need.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor Features
Supports addition, subtraction, multiplication, division, and comparison
Program counter
Instruction decode
Instruction cache
Direct mapped
Configurable caching with CacheLink
Configurable size: 2 kB, 4 kB, 8 kB, 16 kB, 32 kB, 64 kB
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor Performance
Load and store (two clock cycles)
Multiply (two clock cycles)
Operating frequency – fast speed grade, 5-stage pipeline
307 MHz on Virtex-6 FPGA (-3)
245 MHz on Virtex-5 FPGA (-3)
154 MHz on Spartan®-6 FPGA (-3)
119 MHz on Spartan-3 FPGA (-5)
Performance of 1.15 DMIPS/MHz
779/1,134 LUTs in Virtex-6 FPGA
240/330 LUTs in Virtex-5 FPGA
770/1,154 LUTs in Spartan-6 FPGA
1,258/1,821 LUTs in Spartan-3 FPGA
The MicroBlaze processor architecture balances execution performance against implementation size. It is important to keep in mind that benchmark performance varies depending on the processor configuration, implementation tool results, targeted FPGA architecture, and device speed grade.
The performance numbers presented on this slide are best-case comparison numbers achieved under conditions equivalent to those used in the industry. The maximum performance and maximum clock frequency varies from one design to another, according to the configuration options used.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
New MicroBlaze Processor v7 Features
New features and improvements
Virtual memory management provides greater control over memory protection, which is especially useful with applications that can use an RTOS
Note…the MicroBlaze processor MMU is compatible but does not have the same functionality as the PPC405 processor MMU
Processing improvements
Speeds up
FP > Int conversion
Int > FP conversion
FP square root
Higher performance is achieved with the MicroBlaze processor v7 for various reasons, but the main reason is the new PLB v46 bus. The PLB46/IP replaces OPB/IP. The PLB v46 supports point-to-point and standard shared bus topology.
Although the PLB v46 supports a 128-bit interface, the interface to the MicroBlaze processor is 32 bits.
The MMU for the MicroBlaze processor was derived from the PPC 405 processor. The PPC 405 processor has set associative cache and write through/write back cache policies, so these attributes are not in the MicroBlaze processor MMU. The MMU helps those requiring operating systems that need MMU (Linux or Windriver systems, for example). There are some XMD “fixes” and some FSL improvements.
Those who might worry about the differences between the MicroBlaze processor MMU and the PPC processor MMU include users who design and port operating systems and partition kernels from user space (security-type applications), as well as tools designers - for example, Mentor Graphics co-simulation tools will use memory protection or memory management unit to partition symbol tables.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Buses 101
Bus masters have the ability to initiate a bus transaction
Bus slaves can only respond to a request
Bus arbitration is a three-step process
A device requesting to become a bus master asserts a bus request signal
The arbiter continuously monitors the request and outputs an individual grant signal to each master according to the master’s priority scheme and the state of the other master requests at that time
The requesting master samples its grant line until granted access. When the current bus master releases the bus, the master then drives the address and control lines to initiate a data transaction to a slave bus agent.
Arbitration mechanisms
Fixed priority, round-robin, or hybrid
Arbitration can be hidden or non-hidden. Hidden arbitration indicates that another device will become the next master when the current master releases the bus. Non-hidden arbitration prevents another device from receiving a grant signal when the current master is driving the bus.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor Bus Example
IXCL
DXCL
Instruction CacheLink
Data CacheLink
The MicroBlaze processor core is organized as a Harvard architecture with separate bus interface units for data and instruction access. Two buses are supported, a Local Memory Bus (LMB) and the Processor Local Bus (PLB v46). The Xilinx proprietary LMB provides single-cycle access to on-chip, dual-port block RAM. The PLB interface provides a connection to both on-chip and off-chip peripherals and memory.
In addition, the MicroBlaze processor core provides sixteen input/output interfaces to Fast Simplex Link (FSL) buses. The FSL buses are unidirectional, non-arbitrated, dedicated communication channels. The MicroBlaze processor also has an optional CacheLink interface (FSL like) that provides cache port connections directly to the external memory controller. This offloads the caching operation from the PLB bus.
The MicroBlaze processor bus interfaces include the following features:
PLB v46 bus interface provides byte-enable support
LMB provides a simple synchronous protocol for efficient block RAM transfers
LMB provides guaranteed performance of 125 MHz for the local memory subsystem
FSL provides a fast non-arbitrated streaming communication mechanism
CacheLink provides a fast non-arbitrated external memory caching mechanism
Definitions:
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Local Memory Bus (LMB)
The Local Memory Bus (LMB) provides single-cycle access to on-chip dual-port block RAM for MicroBlaze processors
The LMB provides a simple synchronous protocol for efficient block RAM transfers
The LMB provides a maximum guaranteed performance of 307 MHz in
Virtex-6 FPGAs, for the local memory subsystem
Harvard processor architecture
DLMB: data interface, local memory bus (block RAM only)
ILMB: instruction interface, local memory bus (block RAM only)
The LMB is a fast, local bus for connecting MicroBlaze processor instruction and data ports to high-speed peripherals, primarily on-chip block RAM (block RAM). The LMB is an efficient, single-master bus, requiring no arbiter. It has separate read and write data buses and utilizes few FPGA resources. The bus provides a synchronous protocol operating at 307 MHz (in the Virtex-6 FPGA).
The MicroBlaze processor can have one or two LMB controllers, depending on whether or not instruction or data memory is present on the LMB side.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
LMB Timing
The MB, LMB, PLBv46 clock must be the same clock
Use a timing period constraint on the processor clock line to insure place and route timing closure
This is done for you in Base System Builder
If the period constraint is placed on an external FPGA clock pin it will be pushed through any DCMs and global buffers that drive the MicroBlaze processor clock line
The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses a minimum number of control signals and a simple interface to ensure that local block RAM is accessed in a single clock cycle.
All LMB signals are high true.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Bus Summary
High
Low
Low
Low
Maximum clock rates are estimates and are presented for comparison only. The actual maximum clock rate for each bus is dependent on device family, device speed grade, design complexity, and other factors.
Peak data rate is the maximum theoretical data transfer rate at the clock rate shown for each bus.
The typical data rates are intended to illustrate data rates that are representative of actual system configurations. The typical data is highly dependent on the application software and system hardware configuration.
Assumes primarily cacheline fills and minimal read and write concurrency (66.7-percent bus utilization).
Assumes that the DCR operates at the same clock rate as the PLB and each DCR access requires five clock cycles. The number of clock cycles per DCR transfer is dependent on how many DCR devices are present in the system. Each additional DCR device adds latency to all DCR transfers.
The OCM controller operates at the PPC 405 processor core clock rate, but its data transfer rate is limited by the access time of the on-chip memory. The typical data rate assumes 66.7-percent bus utilization.
Assumes 66.7-percent bus utilization.
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
MicroBlaze Processor-Based Embedded Design
Fast Simplex Link (FSL): The MicroBlaze processor contains zero to sixteen-input Fast Simplex Link interfaces and zero to sixteen-output LocalLink interfaces. The FSL channels are dedicated, unidirectional, point-to-point data-streaming interfaces.
The FSL interfaces on the MicroBlaze processor are 32-bits wide. In addition, the same FSL channels can be used to transmit or receive either control bits or data words.
In addition to the data, an additional control bit is implemented that can be sensed as a MicroBlaze processor condition code.
There are eight cycle-assembly instructions that implement register-to-FSL operations. The instructions accommodate blocking, non-blocking, and control bit dependent operations. Wrapping them into custom C functions provides an optimal method by which you can implement custom instructions to a hardware co-processor function.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Fast Simplex Links (FSL)
Unidirectional point-to-point FIFO-based communication
Dedicated MicroBlaze processor C and ASM instructions for easy access
High-speed access in as little as two clocks on the processor side; 600 MHz at the hardware interface
Available in Xilinx Platform Studio (XPS) as a bus interface library core from Hardware > Create or Import Peripheral
FSL_M_Clk
32-bit data
The slide shows the FSL core with simplified inputs and outputs.
The FSL is basically a FIFO. In fact, the interface on the fabric side is that of a FIFO. The “M” side signals are for the write from fabric direction while the “S” side signals are for the read by fabric direction.
Each direction has its own FIFO. It is not necessary to implement both directions.
The internal FIFO, control bit and datapath are configured via the FSL wizard.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
FSL Advantages
Clock speed is not slowed down by new hardware
FSL is faster than a bus interface
Saves clock cycles
Minimal FPGA fabric overhead
MicroBlaze processor v7 allows for up to 16 parallel FSL channels
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Quiz1_MB
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Hardware Overview
PPC 440
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Many vendors support evaluation and demo boards with Xilinx FPGAs
Xilinx
Avnet
NuHorizons
Digilent
Base System Builder (BSB) is a wizard to facilitate a fast processor-based system design by high abstraction, level-specification entry
Starting a Processor Design
Virtex®-5 FPGA ML507
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Create a New Project Using the BSB
BSB enables fast design construction
Creates a completed platform and
test application that is ready to
download
Automatically matches the pinout of
the design to the board
The Set Project Peripheral Repository
option is used for storing custom
peripherals and drivers in a reserved
location
The first lab, “Hardware Construction with the Base System Builder,” will use the BSB.
The peripheral repository is a place to store custom bus peripherals; the default location is the current project.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Selecting a Board
Xilinx and its distribution partners sell demo boards with a wide range of added components
This dialog box allows you to quickly learn more about all available demo boards
It also allows you to install the necessary BSB files if you want to target a demo from another vendor
Note that you can also create your own BSB file for a custom board
Stepping is a means of providing the most currently available architectural resources as soon as it becomes available.
Each device, once available, has a mark that specifies what step device is being used.
Enter the value placed on the package into the software if the device is early access silicon.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Selecting a Processor
supports the construction of single- and dual-processor systems
When selecting the multi-processor option, later screens will have choices of processors to attach peripheral components and various inter-processor communication schemes.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Configuring the Processor
Processor clock frequency is the clock rate connected directly to the processor
Bus clock frequency is the clock rate of all bus peripherals in the system
These selections will automatically customize the clock generator module
The appropriate debug interface is added automatically
The selections made here will instantiate and configure the system clocking component.
The debug interface is always included. For the MicroBlaze processor, a MDM debug peripheral will be included and hooked to the FPGA internal BSCAN component for visibility on the FPGA JTAG pins.
For the PowerPC® processor, which has the debug module in silicon, a choice is given to hook the internal JTAG signals from the PPC to either FPGA pins or the BSCAN module.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Configuring the I/O Interfaces
Choose the peripherals you need from those available for your demo board
Peripherals can be added or removed
Most peripherals are customizable via drop-down lists when selected
Most peripherals support
for all board hardware configurations
The Base System Builder (BSB) determines and lists what external memory and peripheral devices are available for your development board. You can enable or disable each interface by adding or removing from the list of available devices to the processor list.
The following are commonly used devices:
Serial devices: Universal Asynchronous Receiver-Transmitter (UART), IIC, and Serial Peripheral Interface (SPI)
General-purpose I/O devices: Light Emitting Diodes (LEDs), dip switches, and pushbuttons
External memories: Synchronous Dynamic RAM (SDRAM), Double Data Rate (DDR), and Static RAM (SRAM)
High-speed communication devices: Ethernet
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
A Good Start on a Processor Design
Basic PowerPC processor system
Basic MicroBlaze processor system
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Hardware Overview
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Quiz_final_MB
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Summary
The MicroBlaze processor v7 supports the PLB v46 bus standard
Being a soft core processor, many features are implemented on demand
The MicroBlaze processor supports two buses
LMB for block RAM only
PLB v46 for bus peripheral components; same as the PowerPC 440 processor
Typically the ILMB and DLMB buses share the same block RAM via the dual ports
Support of up to 16 channels FSL
Simplex; up to 16 in and 16 out
FIFO interface on fabric side
CacheLink is used to cache contents from an external memory interface controller to block RAM cache
Editor Note: Put the Where Can I Learn More content in LGP after the Summary slide.
Where Can I Learn More?
Tool documentation
Right-click any processor or peripheral from the IP Catalog and select View PDF Datasheet
Processor IP Reference Guide
PowerPC 440 Processor Block Reference Guide – Hardware Reference
MicroBlaze Processor Reference Guide
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
Xilinx Embedded Processing page
www.support.xilinx.com/embedded
Learn more about Embedded Design Kits for all of our device families
Xilinx online documents
Processor IP Reference Guide
Right-click any peripheral from the IP Catalog to learn more about it
Embedded Systems Tools Guide
MicroBlaze Processor Reference Guide
For all docs, select Help EDK Online Documentation from the EDK tools
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
Xilinx Training Courses
Introduction to most of the EDK tools
Embedded Systems Software Development course
Rapidly architect an embedded software system
Introduction to the SDK (Software Development Kit)
Advanced Embedded Systems Development course
Take advantage of advanced features of the PPC440
Apply advanced debugging techniques including ChipScope
Design a Flash memory-based system and boot load from off-chip Flash memory
Customers spend 50% of their time in lab
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
What’s Next?
Related Video Courses
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
Trademark Information
Allow user to leave quiz:After user has completed quiz
User may view slides after quiz:At any time
User may attempt quiz:Unlimited times
PROPERTIES
Allow user to leave quiz:After user has completed quiz
User may view slides after quiz:At any time
User may attempt quiz:Unlimited times