Work in progress – Do not publish or distribute1
Summer Public Conference ORTC 2011 ITRS
Alan Allan, Rev 0, 7/13/11
Work in Progress – Do Not Publish
2
1) Unchanged for 2010/11 MPU contacted M11) 2-year cycle trend through 2013; then 3-year trend to 20262) 60f2 SRAM 6t cell Design Factor3) 175f2 Logic Gate 4t Design Factor4) Ongoing - evaluate alignment of “nodes” with latest M1 industry
status and also High Performance/Low Power timing needs
2) Unchanged for 2010/11 Tables: MPU Functions/Chip and Chip Size Models
1) Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factors
2) ORTC line item OverHead (OH) area model, includes non-active area
3) Updated for 2010/11 Tables: MPU GLpr, GLph – trends “smoothed” by PIDS modeling; but close to previous targets
4) Updated for 2010/11 Tables: Vdd Low operating and standby line items from PIDS model track “smoothed” gate length changes
2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary
Work in Progress – Do Not Publish
3
5) Updated in ORTC 2011 Tables - DRAM contacted M1:1) 1-year pull-in of M1 and bits/chip trends; 2) no Flattening of DRAM M1 as with Flash Poly**3) 4f2 push out [to 2013];
6) Updated in ORTC 2011 Tables - Flash Un-contacted Poly:1) 2-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs)
trend to 2020/10nm; then 3-year trend to 2022/8nm; ** then Flat Poly after 2022/8nm;
2) and 3bits/cell extended to 2018; 4bits/cell delay to 2019
7) Updated in ORTC 2011 Tables - DRAM Bits/Chip and Chip Size Model:
1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for smaller chip sizes)
8) Updated in ORTC 2011 Tables - Flash Bits/Chip and Chip Size Model:
1) 2-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr acceleration for higher densities sooner);
2) New 3D layers Models vs. relaxed half-pitch tradeoffs are now included in the 2011 Renewal
2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
Work in Progress – Do Not Publish
4
9) Updated in ORTC 2011 Tables - ORTC Table 5 - Litho # of Mask layers MPU, DRAM,
9) Flash Survey inputs Updated10) Also IC Knowledge (ICK) model contribution to extend mask levels range
10) Unchanged for 2011 - IRC 450mm Position: 1) Timing Status
1) Consortia work underway2) IDM and Foundry Pilot lines: 2013-14; 3) Production: 2014-162) ISMI making good progress on 450mm program activities to meet the ITRS Timing3) Europe momentum building - EEMI status reviewed with IRC in Potsdam4) FI TWG will extend 300mm wafer generation in parallel line item header with 450mm; 1) Including Technology upgrade assumptions through end of roadmap2) Assuming compatibility of 300mm productivity extensions into the 450mm generation ;
5) Utilizing a new ITRS-based ICK Strategic commercial model , SEMATECH has developed 300mm and 450mm 2009-2024 Range Scenarios for silicon and equipment demand
11) Updated in 2011 - More than Moore white paper online at www.itrs.net 1) New “Moore’s Law and More” Graphic update included in 2011 ITRS Executive Summary2) MtM Workshop completed in Potsdam, GE, in April and reviewed at Summer ITRS meeting3) New MEMS TWG and Chapter added to 2011 ITRS
2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
Work in Progress – Do Not Publish
– IRC Equivalent Scaling Graphic Update• Included in 2011 Update: Parallel bulk and SOI pathways; and Clarification of gate mobility
materials pathway• Pull-in placement of MuGFET Timing (taking into account multiple manufacturers)
– PIDS and FEP Memory Survey Proposal Updates • Possible additional acceleration
– FEP and Design and System Drivers Logic Monitor• Monitor MPU and Leading Edge Logic technology trends
– A&P/Design Power Model• Possible proposals for Power Dissipation "hot spot" model rather than chip area basis
– PIDS/Design Max On-chip Frequency vs Intrinsic Modeling• Included in 2011 Update: New Max Chip Frequency trends (reset to 3.6Ghz/2010
plus 4% CAGR trend)• TBD PIDS Intrinsic Transistor and Ring Oscillator model Changes to 8% [from
unchanged 2011 13% trend]• PIDS Updates include MASTAR static modeling near-term and TCAD dynamic
long-term modeling• Also “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional
scaling– YE Defect Density Modeling
• New ORTC Defect Density model work moved to 2012 Update due to loss of modeling resources
5
Technology Pacing Cross-TWG Study Group (CTSG) work preparation for 2012 Update:
2010 vs 2011 Renewal ITRS ORTC Technology Trend Pre-Summary (cont.)
6
2011- Updated Flash Poly Definition
DRAM and MPU/ASIC Unchanged
2011 Definition of the Half Pitch – New 2010 Poly Definition[Note: The ITRS does not utilize any single-product “node” designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology
trends may be drivers on individual TWG tables]
Source: 2009 ITRS - Exec. Summary Fig 1
Poly Pitch
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
8-16 Lines 32-64 Lines
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2
Rev 8, 07/08/11 Status Revision
Work in Progress – Do Not Publish!
Work in Progress – Do Not Publish!7
Production Ramp-up Model and Technology/Cycle Timing
Months
0-24
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
First Two Companies
Reaching Production 2
20
200
2K
20K
200K
AdditionalLead-time:ERD/ERM
Research andPIDS Transfer
Volum
e (Wafers/M
onth)
Production Ramp-up Model and Technology Cycle Timing
Source: 2009 ITRS - Exec. Summary Fig 2a
*Examples: 25Kwspm ~= 4.5Mu/mo @ 280mm210Mu/mo @ 140mm215Mu/mo @ 100mm222mu/mo @ 70mm2
2010 WAS 2011 Unchanged
Work in Progress – Do Not Publish!8
ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing [Example: MOSFET High-mobility Channel Replacement Materials]
Source: 2009 ITRS - Executive Summary Fig 2b
Months
Alpha
Tool
Development Production
Beta
Tool
Product
Tool
Vol
ume
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200KResearch
-72 0 24-48 -24-96
Transfer to PIDS/FEP(96-72moLeadtime)
First Tech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021Hi-
Example:
1st 2 Co’s
Reach
Product
First Tech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
2010 WAS 2011
Unchanged
Work in Progress – Do Not Publish!9
Table ORTC-1 ITRS Technology Trend Targets
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
WAS Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 38 32 28 25 23 20 18 15.9 14.2 12.6
IS 38 24 22 20 18 17 15 14.2 13.0 11.9
WAS DRAM ½ Pitch (nm) (contacted)[1,2] 52 45 40 36 32 28 25 22.5 20.0 17.9
IS 45 40 36 32 28 25 23 20.0 17.9 15.9
WAS MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 54 45 38 32 27 24 21 18.9 16.9 15.0
IS 54 45 38 32 27 24 21 18.9 16.9 15.0
WASMPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 47 41 35 31 28 25 22 19.8 17.7 15.7
IS 47 41 35 31 28 25 22 19.8 17.7 15.7
WASMPU High-Performance Physical Gate Length (GLph) (nm)[1] 29 27 24 22 20 18 17 15.3 14.0 12.8
IS 29 27 24 22 20 18 17 15.3 14.0 12.8
IS/UnchgASIC/Low Operating Power Printed Gate Length (nm) ††[1] 54 47 41 35 31 25 22 19.8 17.7 15.7
IS 54 47 41 35 31 25 22 19.8 17.7 15.7
WAS ASIC/Low Operating Power Physical Gate Length (nm)[1] 32 29 27 24 22 18 17 15.3 14.0 12.8
IS 32 29 26 24 21 19.4 17.6 16.0 14.5 13.1
WAS ASIC/Low Standby Power Physical Gate Length (nm)[1] 38 32 29 27 22 18 17 15.3 14.0 12.8
IS 38 32 30 27 24 22 20 17.5 15.7 14.1
WAS MPU High-Performance Etch Ratio GLpr/GLph [1] 1.6039 1.5296 1.4588 1.4237 1.3895 1.3561 1.3235 1.2917 1.2607 1.2304
IS 1.6040 1.5297 1.4589 1.4239 1.3898 1.3564 1.3239 1.2921 1.2611 1.2309
NEW MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.6818 1.6039 1.5599 1.4972 1.4706 1.2869 1.2640 1.2416 1.2196 1.1979
[new PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]
Work in Progress – Do Not Publish!10
Table ORTC-1 ITRS Technology Trend Targets
Year of Production 2019 2020 2021 2022 2023 2024 2025 2026
Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 11.3 10.0 8.9 8.0 7.1 6.3 5.6 5.0
10.9 10.0 8.9 8.0 8.0 8.0 8.0 8.0
DRAM ½ Pitch (nm) (contacted)[1,2] 15.9 14.2 12.6 11.3 10.0 8.9 8.0 7.1
14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0
13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 7.0 6.2
14.0 12.5 11.1 9.9 8.8 7.9 6.79 5.87MPU High-Performance Physical Gate Length (GLph) (nm)[1] 11.7 10.7 9.7 8.9 8.1 7.4 6.8 6.2
11.7 10.6 9.7 8.9 8.1 7.4 6.6 5.9
ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 7.0 6.2
14.0 12.5 11.1 9.9 8.8 7.9 6.8 5.8
ASIC/Low Operating Power Physical Gate Length (nm)[1] 11.7 10.7 9.7 8.9 8.1 7.4 6.8 6.2
11.9 10.8 9.8 8.9 8.1 7.3 6.5 5.8
ASIC/Low Standby Power Physical Gate Length (nm)[1] 11.7 10.7 9.7 8.9 8.1 7.4 6.8 6.2
12.7 11.4 10.2 9.2 8.2 7.4 6.6 5.9
MPU High-Performance Etch Ratio GLpr/GLph [1] 1.2008 1.1720 1.1438 1.1163 1.0895 1.0633 1.0312 1.0000
1.2013 1.1725 1.1444 1.1169 1.0901 1.0640 1.0315 1.0000
MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.1766 1.1558 1.1352 1.1151 1.0953 1.0759 1.0372 1.0000
WASIS
WASIS
WASIS
WAS
IS
WAS
IS
IS/Unchg
ISWAS
ISWAS
ISWAS
ISNEW
[new PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]
Work in Progress – Do Not Publish
11
2009 ITRS - Technology Trends
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025
Year of Production
Na
no
met
ers
(1e-
9)
2009 ITRS Flash ½ Pitch (nm) (un-contactedPoly) - [2-yr cycle to 2010; then 3-yr cycle]
2009 ITRS DRAM ½ Pitch (nm) (contacted)[2.5yr cycle '00-'10, then 3-yr cycle]
2009 ITRS: 2009-2024
16nm
Near-Term Long-Term
Source: 2009 ITRS - Executive Summary Fig 7a
2010 ITRS Summary Figure 5aFigure 5a DRAM and Flash Memory Half Pitch Trends
Work in Progress – Do Not Publish
12Source: 2009 ITRS - Executive Summary Fig 7a
2010 ITRS Summary Figure 2 – With Updated 2011 Flash Scenario 2 from 2011 ITRS KickoffFigure 2 ORTC Table 1 Graphical Trends (including overlay of PIDS update proposals for 2011 ITRS effort)
2009 ITRS - Technology Trends
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025
Year of Production
Na
no
met
ers
(1e-
9)
2009 ITRS Flash ½ Pitch (nm) (un-contactedPoly) - [2-yr cycle to 2010; then 3-yr cycle]
2009 ITRS DRAM ½ Pitch (nm) (contacted)[2.5yr cycle '00-'10, then 3-yr cycle]
2009 ITRS: 2009-2024
16nm
Near-Term Long-Term
PIDS DRAM Projection~1-yr pull-in
42nm M1 to 2010 (2 co’s);Then 3-yr cycle to 2024/8nm;
2019: PIDS Flash 4 bits/cell push-out
MemoryPIDS 2011Proposals
2013: PIDS DRAM 4f2 Design Factor bits/cell push-out
PIDS 2011 Sc 2: 2010/24[23.84]nm;Then 4yr cycle* to
2020/10nm;Then 3-yr cycle to
2022/8nm;Then flat/8nm to 2026:
4yr cycle = 0.917004/yr:2010/23.84nm2011/21.86nm
2012/20.0452nm2016/14.17nm
2020/10.0226nm2022->26/7.95nm
3D - 8 layers
3D - 128 layers
PIDS 3DFlash :
26nm Polyhalf-pitch
2016-18/32;Then
2019-21/28;Then
2022-25/24Then
2025-26/18nm ~5.5-yr
Cycle ?
[Including Final PIDS 2011 ITRS Proposal Revision for 2011 ITRS Work]
Long-Term ‘11
Work in Progress – Do Not Publish!13
Flash (NAND) Product Size Generations
2009 ITRS Renewal:
PIDS Flash Size: 2007 2011 2016 2020
2007 ??? ??? ??? ???
4x/4-5yrs WAS'09 16G 64G 256G 1T
Interim Generations: 2009 2014 2018 2022
??? 2007 ??? ??? ??? ???
4x/4-5yrs WAS'09 32G 128G 512G 2T
5yrs 4yrs 4yrs
2011 ITRS Renewal (PIDS 2010 Update Proposal):
PIDS Flash Size: 2007 2010 2011 2014 2016 2019 2020
4x/4-5yrs WAS'09 16G 64G 256G 1T
4x/4-5yrs IS'11 64G 256G 1T
Interim Generations: 2008 2009 2012 2014 2017 2018 2021 2022 2026
4x/4-5yrs WAS'09 32G 128G 512G 2T n/a
4x/4-5yrs IS'11 32G 128G 512G 2T 2T
4yrs 5yrs 4yrs ??yrs
Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/2022-26
Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G
128Gbit chip will be available in 2012.
NAND Cell Array Efficiency unchanged from 56% in ITRS 2010
Work in Progress – Do Not Publish!14
DRAM Product Size Generations
2009/10 ITRS Renewal:
PIDS DRAM Size: 2010 2011 2016 2017 2022 2023
4x/6yrs 2007 4G 16G 64G
WAS'09/10 4G 16G 64G
Interim Generations: 2008 2013 2014 2019 2020
4x/5-6yrs 2007 2G 8G 32G
4x/6yrs WAS'09/10 2G 8G 32G
5yrs 6yrs
2011 ITRS Renewal (PIDS 2010 Update Proposal):
PIDS DRAM Size: 2011 2017 2018 2023 2025
4x/6yrs WAS'09/10 4G 16G 64G n/a
4x/7yrs IS'11 4G 16G 64G
Interim Generations: 2008 2014 2020
4x/6yrs WAS'09/10 2G 8G 32G
4x/6yrs IS'11 2G 8G 32G
6yrs 6yrs 7yrs?
DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026
DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025
DRAM Cell size factor: 4F2 cell will be available in 2013. Delay 2years from ITRS2009/10
DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010
15
2009 ITRS - Technology Trends
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025
Year of Production
Na
no
met
ers
(1e-
9)
2009 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[historical trailing at 2-yr cycle; extended to 2013;then 3-yr cycle]
2009 ITRS MPU Printed Gate Length (GLpr) (nm)[3-yr cycle from 2011/35.3nm]
2009 ITRS MPU Physical Gate Length (nm) [begin3.8-yr cycle from 2009/29.0nm]
2009 ITRS: 2009-2024
16nm
Near-Term Long-Term
2010 ITRS Summary Figure 5bFigure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends [ Unchanged from 2009 ITRS ]
2009/2010 ITRS versions WAS versus IS/Unchanged (except extend to new end period): 2011 ITRS: 2011-2026
Work in Progress – Do Not Publish!
16
2009 ITRS - Technology Trends
1
10
100
1000
1995 2000 2005 2010 2015 2020 2025
Year of Production
Na
no
met
ers
(1e-
9)
2009 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[historical trailing at 2-yr cycle; extended to 2013;then 3-yr cycle]
2009 ITRS MPU Printed Gate Length (GLpr) (nm)[3-yr cycle from 2011/35.3nm]
2009 ITRS MPU Physical Gate Length (nm) [begin3.8-yr cycle from 2009/29.0nm]
2009 ITRS: 2009-2024
16nm
Near-Term Long-Term
2010 ITRS Summary Figure 5bFigure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends [ Unchanged from 2009 ITRS ]
2009/2010 ITRS versions WAS versus IS/Unchanged (except extend to new end period): 2011 ITRS: 2011-2026
Work in Progress – Do Not Publish!
Equiv. ScalingTrade-
off
StrainHK/MG
MuG-FET
Hi-u,(tbd)
ITRS 1999P. Gargini
“EquivalentScaling”Concept
FDSOI
PDSOI
IS: 2011 ITRS: 2011-2026
Long-Term ‘11
2011ITRS:
Extend M1;
&GLpr;to 2026
on3-yearCycle
GLph
versus M1 in 2026
- analyzing implications
1995->2015“Nodes”
“360-11(10)”ITRS M1 hp303-20nmITRS GLph90nm-45nm
Work in Progress – Do Not Publish!17
Updated Proposal - for 2011 work
Metal
High kGate-stack material
2009 2012 2015 2018 2021
Bulk
FDSOI
Multi-gate(on bulk or SOI)Structure
(electrostatic control)
Channelmaterial
Metal
High k
2nd generation
Si + Stress
S D
High-µ InGaAs; Ge
S D
PDSOI
Metal
High k
nth generation
PossibleDelay
Possible Pull -in
17See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)
68nm 45nm 32nm 22nm 16nm2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm
2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 22nm 16nm 11nm2009 IS ITRS Flash Poly : 54nm2009 ITWG Table Timing: 2007 2010 2013 2016 2019 2021
= Additional timing movementconsiderations for 2011 ITRS work
2010 ITRS Summary Figure 3 “Equivalent Scaling” RoadmapFigure 3 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison)
[ PIDS/FEP/DesignHP/LOP/LSTP
Sub-Team Transistor
Modeling Work Underway ]
Need Proposals - for 2012 Update work; Plus 2011 Text & Exec. Summary Topic
Work in Progress – Do Not Publish
ORTC Table 4: Design TWG Model for On-Chip Frequency – Lower model starting point 2010/3.6Ghz– 4% growth rate through 2026– *Unchanged 2011 ITRS 13% PIDS target
model Intrinsic Transistor Frequency Growth;– *However, proposal for 2012 ITRS 8% PIDS
target model Intrinsic Transistor Growth (work preparation in 2011)
18
Table ORTC-4 Performance and Packaged Chips Trends
Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026Chip Frequency (MHz)
WAS On-chip local clock [2] 5.454 5.875 6.329 6.817 7.344 7.911 8.522 9.180 9.889 10.652 11.475 12.361 13.315 14.343 15.451 16.640 Design /
ISOn-chip local clock [2] 3.462 3.600 3.744 3.894 4.050 4.211 4.380 4.555 4.737 4.927 5.124 5.329 5.542 5.764 5.994 6.234 6.483 6.743
Ghz
Work in Progress – Do Not Publish!19
0.10
1.00
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRSC
V/I
(ps)
Year of Production Ramp
1/(CV/I)Ring Oscillator (invertors) 101 stages; 1001, etc.FO 1 (capacitance example .1pf)FO 4 (capacitance example .4pf)
PIDS Table 2: CV/I – 2009-2011 ITRS Unchanged
100
1000
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRS
1/(
CV
/I )(
Gh
z)
Year of Production Ramp
1/(CV/I)Ring Oscillator (invertors) 101 stages; 1001, etc.FO 1 (capacitance example .1pf)FO 4 (capacitance example .4pf)
ITRS PIDS 2009-10 ITRS CV/I Trends vs Possible 2012 ITRS MUG-FET Pull-In “What if” proposal
Work in Progress – Do Not Publish!20
0.10
1.00
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRSC
V/I
(ps)
Year of Production Ramp
PIDS Table 2: CV/I – 2009-2011 ITRS Unchanged
100
1000
20
00
20
05
20
10
20
15
20
20
20
25
20
30
Extended Planar Bulk
UTB FDSOI
Multiple Gate 2010 ITRS; 2011 ITRS Unchanged
Multiple Gate Pull-in Scenario - 2012 ITRS
1/(
CV
/I )(
Gh
z)
Year of Production Ramp
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
PIDS 2009-10 ITRS CV/I Trends vs Possible 2012 ITRS MUG-FET Pull-In “What if” proposal
1/(CV/I) (Ghz) ~ +13%CAGR; from:
CV/I (ps) ~-11%CAGR
1/(CV/I) (Ghz) ~ +13%CAGR; from:
CV/I (ps) ~-11%CAGR
Note: 1/(CV/I) frequency is reduced by a factor of 1/22.4 in a PIDS model of a Ring Oscillator (inverter chain) 101 stages; 1001 stages, etc.;FO 1 (capacitance example .1pf);FO 4 (capacitance example .4pf)
21
Source: ITRS Test TWG compilation, ca 4Q 2010
ITRS 2011 ISPast Future
PIDS/FEP 1/(CV/I) WAS: 13% CAGR (~2x/5.5yrs)2011 Proposal by Design TWG: 1/(CV/I) = 8% CAGR
(~2x/9yrs)
ORTC Table 4:On-Chip Local Clock Frequency:2011 Proposal by Design TWG:
4% CAGR (~2x/18yrs), Trend begins at 2010:
High [not included in ORTC]: 5.5Ghz [special cooling]
ORTC: On-Chip Freq: 3.6Ghz
On-Chip Clock Frequency:Performance Improvement tradeoffs provided by “Equivalent Scaling” Including Design Alternatives:
-Multi-Core Architecture-Memory Architecture-Software Power Management-Etc.
Work in Progress – Do Not Publish!
ORTC Table 4:On Chip Local Clock Frequency
“GOLD” Trend
2003-2009Historical
Trend: 26% CAGR (~2x/3yrs)
1999-2003Historical
Trend: 39% CAGR (~2x/2yrs)
PIDS/FEP 2012 Update
Proposal
PIDS/FEP CV/I WAS 2007: 1/(CV/I) =from 18% to 13% CAGR (~2x/5.5yrs)
2007 Proposal by Design TWG: On-Chip Freq. = from 18% to 8% CAGR
(~2x/9yrs)
PIDS/FEPRing Oscillator Model
101 invertor stagesWith equivalent Fan-out 4
Capacitance load; Results in Frequency of
~1/22 x 1/(CV/I)at 13% CAGR (~2x/5.5yrs)
DesignH’room
1/22.4
PIDS/FEP 1/(CV/I)at 13% CAGR (~2x/5.5yrs)
2012 - PIDS/FEP 1/(CV/I)at 8% CAGR (~2x/9yrs)
Work in Progress – Do Not Publish
ORTC Table 5 Update: Litho TWG IS model for Mask Count – MPU survey-based, mask counts peak 2014/(54 masks peak) EUV
expected 2015 – DRAM referenced to MPU, mask counts peak 2012/(41 masks peak)
EUV expected 2013 – Flash survey-based, mask counts peak 2012/(43 masks peak) EUV
expected 2013 – Sidewall image transfer technology IEDM papers should be evaluated– Table 5 also includes NEW IC Knowledge (ICK)
www.icknowledge.com modeled comparison targeting ITRS 2011 Litho EUV timing; but extended out through 2024 using 2009-10 ITRS (www.itrs.net ) assumptions
– Limited YE Defect Density modeling resources requires delay of update response to 2012
22
Work in Progress – Do Not Publish
23
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
SEMATECHSurvey ITRS 2011
IS:
WithMPU EUV in
2015;
DRAM& Flash in
2013
Litho 2011 Survey vs ICK 2011 ITRS-based* Model[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]
Work in Progress – Do Not Publish24
Litho 2011 Survey vs ICK 2011 ITRS-based* Model[*extended to 2024 based on 2009-24 ITRS www.itrs.net ]
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
ICK Strategic Model*
*Based onITRS v2009-10
WithMPU EUV in
2015;
DRAM & Flash EUV in
2013
Flash Charge Trap
in 2012;Multi-layer 3D begins
2016
MPU Delay EUV to
2017
Backup:
Work in Progress – Do Not Publish
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
SEMATECHSurvey
ITRS 2011
WithMPU EUV in
2015;
DRAM& Flash in
2013
25
Litho 2011 Survey “IS” vs ICK-based* 2012 ITRS Model Proposal[*extended to 2024 based on 2009-24 ITRS www.itrs.net ; then “smoothed” and extrapolated ]
Backup:
ITRS 2012 Update Proposal: MPU: DRAM: Flash:
20
30
40
50
60
70
80
1995 2000 2005 2010 2015 2020 2025
DRAM
Flash
MPU
ITRS 2011SEMATECH
Survey-based “IS”: MPU ; DRAM ; Flash vs. ICK-based proposal
WithMPU EUV in
2015;
DRAM& Flash EUV in
2013
ITRS 2012 Update (ICK-based) Proposal: MPU: DRAM: Flash:
Flash Charge Trap in 2012;
Multi-layer 3D begins
2016
Work in Progress – Do Not Publish! 26
2009 ITWG Table Timing: 2007 2010 2013 2016 2019
68nm 45nm 32nm 22nm 16nm2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 22nm 16nm 11nm2009 IS ITRS Flash Poly : 54nm
Vo
lum
e
Years
Alpha
Tool
Beta
ToolTools for Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development Production
450mm 32nm M1 half-pitchPilot Line Ramp
2010
2011
2012
2013
2014
2015
2016
Beta
Tool
Production
Tool
450mm Production Ramp-up Model[ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Source: 2009 ITRS - Executive Summary Fig 2c
450mm Production Ramp-up Model[ 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Versus “Node”/actual contacted M1 and un-contacted Poly Half-Pitch alignment
201122nm
201515nm
201232nm
201522nm
Unchg
11nm
201816nm
202111.3nm2010
40nm
2009/10 WAS 2011
Unchanged
[ORTC DRAM, Flash M1 and Poly
Half-Pitch timing
changes per below]
20xxxxnm
20xxxxnm
*Note: At ITRS/Europe, the IRC approved continuing the ITRS 450mm Timing Graphic unchanged for use in the 2011 ITRS Roadmap guidance.
Work in Progress – Do Not Publish!27
Backup:
1)Moore’s Law and More Graphic Update2)4Q10 SICAS Technology Capacity Demand Tracking Update3)“Nodes” vs MPU/ASIC Technology Trends4)ORTC Table 4 Design On-chip Frequecy vs History and “Nodes”5)ORTC Table 6 PIDS Gate Length vs. HP, LOP, LSTP Vdd 6)Litho Survey #Mask Levels Survey/Technology Timing Alignment7)ORTC Table 5 #Mask Levels and Notes8)FEP Logic Status Monitor9)IMEC www.electroiq.com FinFET SRAM Cell Article
Work in Progress – Do Not Publish
28
More than Moore: Diversification
Mo
re M
oo
re:
Min
iatu
riza
tio
n
Combining SoC and SiP: Higher Value SystemsBa
se
lin
e C
MO
S:
CP
U,
Me
mo
ry,
Lo
gic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
2010 ITRS Summary Figure 4Figure 4 The Concept of Moore’s Law and More
2010/2011
Unchanged
Work in Progress – Do Not Publish!29
0.01
0.1
1
10
2006200520041999 2000 2001 2002 2003 2007 2008 2009
W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS
W.P.C.
W.P.C W.P.C.
W.P.C W.P.C.
W.P.C.
W.P.C W.P.C.
W.P.C.
W.P.C W.P.C.
>0.7m
0.7-0.4m
0.4-0.3m
0.3- 0.2m
0.2- 0.16m
0.16-.12m
<0.08m
0.08-.12m
<0.06m
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.
Year
Fea
ture
Siz
e (H
alf
Pitc
h) (m
)
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU3-Year Cycle
2010 2013
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Un-contacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year CycleAfter 2010 for
Flash; after 2013For MPU
Source: 2009 ITRS - Executive Summary Fig 3
4Q09 SICAS Update ProposalFrom Furukawa-san/Japan
To IRC 3/28/10 (modified by AA)
Year