2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals For Public 07/13/05

2005 ITRS Work in Progress – Do Not Publish

1

International Technology Roadmap for Semiconductors

2005 ITRS/ORTC Product Model ProposalsFor Public 07/13/05 Conference

(based on Rev1Kc, 07/12/05)


2

ORTC Overview - 2005 ITRS Proposals• Recommendation for one standard TWG table technology trend header

– Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver – UNCHANGED from the 2003/2004 Roadmap Update

– Remove ITRS single-product “node” label emphasis, to minimize industry guidance confusion; as we transition to product-oriented technology trend drivers and cycles*

• ORTC Table 1a,b - adjusted to Proposed Japan (STRJ) MPU/ASIC M1 Half-Pitch Trend

– Stagger-contacted, same as DRAM– 2.5-year Technology Cycle* (.5x/5yrs) – 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM)– Then continue on a 3-year Technology Cycle*, equal to DRAM 2010-2020

• ORTC Table 1a,b - added Proposed STRJ Flash Poly (Un-contacted dense lines)– 2-year Technology Cycle* (0.5x/4yrs)– 180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006– Then 3-year Technology Cycle* 1 year ahead of DRAM ’06-’20

• ORTC Table 1a,b – adjusted MPU/ASIC Printed Gate Length to FEP and Litho TWG agreement for ratio relationship to Final Physical Gate Length, which remains UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005)

• TWG table Product-specific technology trend driver header items to be added to individual TWG tables from ORTC Table 1a&b

• Chip Size Models connected to proposals and historical trends, incl. new Flash Model

– Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)]– Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU]– Chip Size [hp MPU; cp MPU; DRAM; Flash]

*Note: Cycle = time to 0.5xlinear scaling every two

cycle periods ~ 0.71x/ cycle


3

Source: 2003 ITRS - Exec. Summary Fig 4

2003/2004 ITRS Definition of the Half Pitch - WAS [DRAM half-pitch determines the 2003 ITRS “node”]

Metal Pitch

Typical DRAM Metal Bit Line

DRAM ½ Pitch = DRAM Metal Pitch/2

Poly Pitch

Typical MPU/ASIC Un-contacted Poly

MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2

Typical MPU/ASICContacted Metal 1

MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2

Metal 1 (M1) Pitch


4

2005 Definition of the Half Pitch – IS[No single-product “node” designation; DRAM half-pitch still litho driver; however,

other product technology trends may be drivers on individual TWG tables]

Metal Pitch

Typical DRAM/MPU/ASIC Metal Bit Line

DRAM ½ Pitch = DRAM Metal Pitch/2

MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly

Pitch

Typical flash Un-contacted Poly

FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2

8-16 Lines


5

Production Ramp-up Model and Technology NodeV

olu

me

(Par

ts/M

on

th)

1K

10K

100K

Months0-24

1M

10M

100M

Alpha

Tool

12 24-12

Development Production

Beta

Tool

Production

Tool

First

Conf.

Papers

First Two Companies

Reaching Production

Vo

lum

e (W

afer

s/M

on

th)

2

20

200

2K

20K

200K

Source: 2003 ITRS - Exec. Summary Fig 2

Fig 2 [UNCHANGED]


6

hp22hp32hp45hp65hp90

20182016

20152013

20122010

20092007

20062004

20032002[Actual]

Year of Production

hp130Technology Node (nm)

WAS: 2003 ITRS Technology Nodes: 3-year cycle*

3-Year Technology Cycle2-Year Technology Cycle [1998-2002actual]

Note: Faster introduction of half-poly pitch from Flash is expected; and Doubling of transistors every 2 years from MPU/ASIC is expected.* Cycle Time = one-half of the time to reach a technology trend reduction to 0.5x

Source: 2003 ITRS - Exec. Summary


7

Note: Faster introduction of half-poly pitch from Flash is expected; Doubling of transistors every 2 years from MPU/ASIC is expected

2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of DRAM @65nm/’06

3-Year Technology Cycle2-Year Technology Cycle [’98-’06 ]

Year of Production

Technology -UncontactedPoly H-P (nm)

2003 20052001

65 223245 16

2008

20062002[Actual]

20042000[Actual]

90130180

76107151 5057 13

201520122009 2018

201620132010 2019 2020

2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal DRAM @45nm/2010

Year of Production

Technology- ContactedM1 H-P (nm)

157 136 119 103 78 68 59 52

201620132010 2019[July’08][July’02] 20052000

201820152012 2020

[130]180 [ 65]90 2232 1645

2008200620032001 2002 2004 2007 2009

2.5-Year Technology Cycle3-2-Yr Cycle] 3-Year Technology Cycle

14

IS: 2005 (’05-’20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle

3-Year Technology Cycle2-Year Technology Cycle [‘98-’04]

Year of Production

Technology - ContactedM1 H-P (nm)

201820152012 2020

201620132010 2019

2003 20052001

65 223245 16

20082006 2009

20072002[Actual]

20042000[Actual]

90130180

80107151 71 57 50 14

10


8

2005 ITRS Product Technology Trends - Half-Pitch, Gate-Length

1.0

10.0

100.0

1000.0

10000.0

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Year of Production

Pro

du

ct

Ha

lf-P

itc

h,

Ga

te-L

en

gth

(n

m)

DRAM 1/2 Pitch[Sc.C]

MPU M1 1/2 Pitch STRJ Proposal (2.5-year cycle)

Flash Poly 1/2 Pitch[NEW Proposal]

MPU Gate Length - Printed[Sc.C]

MPUGate Length - Physical[Sc.C]

.71x/2.5yrsHistorical.71x/3yrs

2005 ITRS Product Technology Trends

Past Future2005 - 2020 ITRS Range

[Cross DRAM 65nm/20061 year ahead after that]

[Equal DRAM 45nm/2010]

[GLpr IS = 1.6818 x GLph WAS, which is

unchanged from 2003/04ITRS, but under discussion

by FEP, PIDS, Litho, and Design TWGs

for CD-control red limits]

[Unchanged from 2003 ITRS]

.71x/2yrs.71x/3yrs

GLpr / GLph =1.6818 Ratio

• DRAM Survey Update: - DRAM (H-P unchanged)

• Flash: Japan/STRJ• MPU: Japan/STRJ


9


10

2005 ITRS Product Technology Trends - Cell Size, Transitor Size

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Year of Production

Bit

, T

ran

sis

tor

Siz

e(u

m2

)

DRAM Cell Size (u2)

Sawada IS DRAM Cell Size (u2)

Flash Cell Size (u2) SLC(NEW)

Flash Eqv.bit Size(u2) MLC(NEW)

MPU SRAM Cell Size (6t)(u2)

MPU Gate Size (4t)(u2)


DRAM IS: 8f2 -> 6f2 / 2008

5f2

~ 29f2

~ 320f2

Flash 28f2 -> 4f2

[WAS: 2003 ITRS][IS: 2005 ITRS]

Note: f = product-related

Half-PitchFeature Size;

A = product-relatedDesign Factor;

n = # transistors perSRAM cell or

MPU Logic Gate;

Af2 = Function Size;

Af2/n = SRAM Cell or Logic Gate

Transistor Size

Note for Flash: SLC = Single-Level-Cell Size

MLC =Multi-Level-Cell

(Electrical Equivalent) Cell Size


11

Moore’s Law After 40 years (functions per chip)

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

10,000,000,000

1970 1980 1990 2000 2010

40048080

8086

8008

Pentium® Processor

486™ DX Processor386™ Processor

286

Pentium® II Processor

Pentium® III Processor

Itanium® Processor

Pentium® 4 Processor

Itanium® 2 Processor2X/2YR

2X/1YR

2X/2YR

Source: Intel® Corp.


12

2005 ITRS Product Technology Trends Proposal - Functions/Chip

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Year of Production

Pro

du

ct

Fu

nc

tio

ns

/Ch

ip(G

iga

(1

0^

9)

- b

its

, tr

an

sis

tors

)

Flash Bits/Chip (Gbits) SLC

Flash Bits/Chip (Gbits) MLC

MPU GTransistors/Chip - H.perf.

MPU GTransistors/Chip - C.perf.

DRAM Bits/Chip Prod (Gbits)

Sawada IS DRAM Bits/Chip Prod (Gbits)

MPU Actual Trends

Chip Size Trends – 2005 ITRS Functions/Chip Model Proposal IS

(WAS)


AverageIndustry 1970-2020

“Moore’s Law”2x Functions/chip

Per 2 years

(@Volume Production, Affordable Chip Size**)

** Affordable Production

Chip Size Targets:DRAM, Flash < 145mm2

hp MPU < 310mm2

cp MPU < 140mm2

** Example Chip Size Targets:1.1Gt P07h MPU

@ intro in 2004/620mm2

@ prod in 2007/310mm2

** Example Chip Size Targets:0.39Gt P07c MPU

@ intro in 2004/280mm2

@ prod in 2007/140mm2

MPU ahead or =“Moore’s Law”2x Xstors/chipPer 2 years Thru 2010


13Past Future 2005 - 2020 ITRS Range

Chip Size Trends – 2003/04 vs.2005 ITRS DRAM & Flash (NEW) Model IS

2005 Proposal ITRS DRAM Chip Size Model(Rev 1K, 06/23/05)

0

100

200

300

400

500

600

700

1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025

Year of Introduction and Production

(mm

2) DRAM Introduction Chip Size

Sawada Production Chip Size IS

4 chips per Litho Field @ 572mm2 = 143mm2

(22x6.5)

4G 8G 32G 64G16G

Bits/

chip: 128G64M

Bits/

chip:

256M

128G

1G 2G

4G

8G 32G 64G

16G

256G 1T

512M

Prod Cell Area Efficiency (CAE) = 63%-56%

Intro Cell Area Efficiency (CAE) = 73%-75%

90 64 45 22 1632 11 8

5 chips per Litho Field @ 704mm2 = 141mm2

(22x6.4)

WAS/IS: 128180255360

128M

32G

16G

4G

8G

2G

32G

16G

64G2G

8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.0DRAM Des.

Factor: 11 6.0 6.0

DRAM

Max Litho Field 2005 ITRS (4x) : 834mm2 (26x32)

2 C

hip

s p

er

Ma

x L

itho

Fie

ld 2

00

5

ITR

S (

4x)

: 4

17

m2

(2

6x

16

)


14Past Future 2005 - 2020 ITRS Range

Chip Size Trends – 2003/04 vs.2005 ITRS Flash (NEW) Model IS2005 Proposal ITRS Flash chip Size (NEW) Model (Allan)

(Rev 1K, 06/23/05)

0

100

200

300

400

500

600

700

1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025


(mm

2)

Flash SLC Production Chip Size

4 chips per Max Affordable Litho Field @

572mm2 = 143mm2 (22x6.5)

Flash Prod Cell Area Efficiency (CAE) = 67%

Flash Intro Cell Area Efficiency (CAE) =TBD -

no model

5 chips per Max Affordable Litho Field @

704mm2 = 141mm2 (22x6.4)

Flash

Bits/chip: 4G 8G 16G 32G 64G 128G256M 1G64M 2G

16 4.032 8.0 4.0 4.0 4.0 4.0 4.04.0 Flash SLC

Des.Factor: 4.0 4.0

128180255360Flash: 90 64 45 22 1632 11 8WAS/IS: 128180255360

8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.011 6.0 6.0

90 64 45 22 1632 11 8

DRAM

HP

DRAM Des.

Factor:


15

2005 Proposal ITRS MPU Chip Size Model (Rev 1K, 06/23/05)

0

100

200

300

400

500

600

700

1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025


(mm

2)

MPU hp Production Chip Size

MPU cp Production Chip Size

MPU hp Introduction Chip Size

MPU cp Introduction Chip Size

DRAM

HP

8G

SRAM Cell Efficiency= 60%Logic Gate Efficiency = 50%

p13c1.5Bt

p16c3.1

p19c p22c

800

Max Litho Field 2005 ITRS (4x): 834mm2 (26x32)

2 C

hip

s p

er

Ma

x L

itho

Fie

ld

2

00

5 I

TR

S (

4x)

: 4

17

m2

(2

6x

16

)

Max Litho Field - Future ITRS? (8x): 208mm2 (13x16)?

p07h1.1Bt

p10h2.2Bt

p07h

1.1Bt

p16h p19h p22hp10h

2.2Bt

p13h

4.4Bt

p02h276Mt

p00h138Mt

p98h69Mt

p04h552Mt

p10c768Mt

hp MPU = 82% SRAM Transistors, 18% Core Logic Transistors

cp MPU = 58% SRAM Transistors, 42% Core Logic Transistors

p02h

276Mt

p04h

552Mt

26% / 2yrsChip Size Growth

p04c192Mt

p02c96Mt

p00c48Mt

p07c384Mt

p07c384Mt

p10c768Mt

p04c96Mt

p02c96Mt

p00c48Mt

p13c1.5Bt

Affordable hp MPU prod Target: 310mm2

Affordable cp MPU prod Target: 140mm2

90 64 45 22 1632 11 8WAS/IS: 12818025536090 68 45 22 1632 11 8

[2

MPU: 136180255360 [2.5yr Technology Cycle

2000- 2010]

Past Future 2005 - 2020 ITRS Range

Chip Size Trends – 2005 ITRS MPU Model Proposal IS


16

Summary• DRAM Model stagger-contacted M1 is unchanged from

2003/2004 Update ITRS (single-“Node” reference removed)• MPU Revised M1 to stagger-contact half-pitch (same as

DRAM) and 2.5-year cycle* through 2010, then 3-year cycle* same as DRAM

• New Flash Model Added for un-contacted poly half-pitch and equal to DRAM contacted, but continues on 2-year cycle* to 1 year ahead of DRAM in 2006, then 3-year cycle* same as DRAM

• Printed MPU/ASIC Gate Length adjusted to new FEP and Litho TWGs ratio agreement, but Physical GL unchanged and on 3-year cycle* beginning 2005

• Historical chip size models “connected” to new Product model proposals, including design factors, function size, and array efficiencies

• Average industry product “Moore’s Law” met or exceeded throughout 2005-2020 ITRS timeframe

[* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]


17

Backup


18

Generic ITRS Table Header Technology Trend Proposal:INDEX 2005 Headers

Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Was DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32 28 25 22 20 18 16 14

IS DRAM ½ Pitch (nm) (contacted) 80 70 65 57 51 45 40 35 32 28 25 22 20 18 16 14

Near-term Long-term

Optional (from ORTC Table 1a&b) TWG Table Product-Specific Technology Trend Proposals:INDEX Table Title WAS: Table 1a and b Product Generations and Chip Size Model Technology Nodes

IS Table 1a and b Product Generations and Chip Size Model Technology Trend Targets

Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

WAS DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32 28 25 22 20 18 16 14

IS DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32 28 25 22 20 18 16 14

WASMPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

95 85 76 67 60 54 48 42 38 34 30 27 24 21 19 17

ISMPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

85 76 67 60 54 48 42 38 34 30 27 24 21 19 17 15

ALTER-NATE

Alternate STRJ Proposal (2.5-year Technology Cycle; equal DRAM at 45nm/2010) MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (stagger-contacted M1, same as DRAM)(f) ( NOT ROUNDED)

90 78 68 59 52 45 40 36 32 28 25 23 20 18 16 14

WasMPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

95 85 76 67 60 54 48 42 38 34 30 27 24 21 19 17

ISMPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

85 76 67 60 54 48 42 38 34 30 27 24 21 19 17 15

ALTER-NATE

Alternate STRJ Proposal (2.5-year Technology Cycle; equal DRAM at 45nm/2010) MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (stagger-contacted M1, same as DRAM)(f) ( NOT ROUNDED)

80 71 64 57 51 45 40 36 32 28 25 23 20 18 16 14

WAS MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 80 70 65 57 50 45 40 35 32 28 25 22 20 18 16 14

IS [Deleted in 2005 ORTC] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

WAS MPU Printed Gate Length (nm) †† 45 40 35 32 28 25 22 20 18 16 14 13 11 10 9 8

IS MPU Printed Gate Length (nm) †† 54 48 42 38 34 30 27 24 21 19 17 15 13 12 11 9

WAS MPU Physical Gate Length (nm) 32 28 25 22 20 18 16 14 13 11 10 9 8 7 6 6

IS MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13 11 10 9 8 7 6 6

WASASIC/Low Operating Power Printed Gate Length (nm) ††

65 53 45 40 35 32 28 25 22 20 18 16 14 13 11 10

ISASIC/Low Operating Power Printed Gate Length (nm) ††

76 64 54 48 42 38 34 30 27 24 21 19 17 15 13 12

WASASIC/Low Operating Power Physical Gate Length (nm)

45 37 32 28 25 22 20 18 16 14 13 11 10 9 8 7

ISASIC/Low Operating Power Physical Gate Length (nm)

45 38 32 28 25 23 20 18 16 14 13 11 10 9 8 7

ADD Flash ½ Pitch (nm) (Contacted Poly) 80 70 65 57 50 45 40 35 32 28 25 22 20 18 16 14

ALTER-NATE

Alternate STRJ Proposal (2-year Technology Cycle; Cross-over DRAM to 65nm/2006, then 3-year Technology cycle, 1 year ahead of DRAM) Flash ½ Pitch (nm) (contacted Poly)(f) (NOT ROUNDED)

76 64 57 51 45 40 36 32 28 25 23 20 18 16 14 13

Near-term Long-term

Documents

2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals For Public 07/13/05