ITRS 2000 Update - Taipei, Taiwan, 11/06/00 1 ITRS/ORTC Tables Technology Node, DRAM Chip Size, Logic Chip Size, and key TWG Line-items (1999 refers to

ITRS 2000 Update - Taipei, Taiwan, 11/06/00

1

ITRS/ORTC TablesTechnology Node, DRAM Chip Size,

Logic Chip Size, and key TWG Line-items (“1999 ” refers to 1999 ITRS; “Sc. 2.0” refers to the IRC “Most

Aggressive” Scenario 2.0 Proposal, 7/11/00)

ITRS 2000 Update Review - Taipei 12/6/00

Rev 1kg_h, 11/7/00

Contact: Alan Allan 480-554-8624, [email protected]


2

ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00

• Technology Requirements Perspective- Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex. 1999 through 2005), annually- Long-Term Years : Following 9 years (ex.: 2008, 2011, and 2014), every 3 years

• Technology Node : - General indices of technology development. - Approximately 70% of the preceding node, 50% of 2 preceding nodes. - Each step represents the creation of significant technology progress- Example: DRAM half pitches (2000 ITRS) of 180, 130, 90, 65, 45 and 33 nm*Year 2000 : Smallest 1/2 pitch among DRAM, ASIC, MPU, etc

• Year of Production: - The volume = *10K units (devices)/month. ASICs manufactured by same

process technology are granted as same devices- Beginning of manufacturing by *a company and another company starts

production within 3 months

• Technology Requirements Color :- : Manufacturable Solutions are NOT known

- : Manufacturable Solutions are known

- : Manufacturable Solutions exist, and they are being optimized

*Year 2000 : Red cannot exist in next 3 years (2000, 2001, 2002)***Year 2000 : Yellow cannot exist in next 1 year (2000)

Red

Yellow

White

** Exception: Solution NOT known, but does not prevent Production manufacturing


3

Table A Product Generations and Chip Size Model - Technology Node Scenarios

YEAR OF PRODUCTION

TECHNOLOGY NODE

WAS(1999 ITRS)

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

200870 nm

201150 nm

201435 nm

DRAM ½ Pitch (nm)WAS (1999 ITRS)

180 165 150 130 120 110 100 70 50 35

DRAM ½ Pitch (nm) I S[Sc.1.0][pull- in 130nm 1 year;100nm/2005; then .7x/3yrsreduction rate]

180 150 130 120 115 105 100 70 50 35

DRAM ½ Pitch (nm) I S[Sc.1.5][pull- in 130nm 1 year;100nm/2004; then.7x/3yrsreduction rate]

180 150 130 120 110 100 90 65 45 33

DRAM ½ Pitch (nm) I S[Sc.2.0][pull- in 130nm 1 year; then.7x/3yrs reduction rate]

180 150 130 115 100 90 80 [60§] [40§] [30§]

§ Note that proposed node years for Scenario 2.0 are now 2007/65nm; 2010/45nm; 2013/33nm; 2016/23nm


4

REV 1kg_g - 10/20/00

ITRS Roadmap Acceleration Continues...(I ncluding MPU/ASIC “Physical Gate Length” Proposal)

1994

1997

1998/1999

500

350

250

180

130

100

70

50

35

25

~.7x pertechnologynode (.5xper 2 nodes)

Year of Production

Fea

ture

Siz

e (n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

XX90XX65XX45XX33XX23

16

AlternativeScenario [1.0]

20007/11 IRC Proposal

Best Case OpportunityScenario [ 2.0 ]

AlternativeScenario [1.5]

MPU/ASIC

Gate Length

Minimum

Feature Size

MPU/ASIC Gate “Physical”

MPU/ASIC Gate “In Resist”

* Note: MPU ASIC Physical Bottom Gate Length Preliminary 2000 Updatestill under discussion.

Technology Node (DRAM Half Pitch)

[9/15 - Litho Proposed “I n Resist” (70% of “Best Case” Half Pitch)]

[9/15 - Litho Proposed “Physical” (1 year ahead of “I n Resist”)]


5

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (Technology Node):

Technology Node Assumptions (per IRC Proposal 7/11/00): a) DRAM Half-Pitch:

1999: 3-year Node cycle (0.7x/3yrs), except year 2005 shifted off trendSc.2.0: 130nm pull-in to 2001 and ~.7x/3yrs(.5x/6yrs) reduction rate

1999 (nm): 1999/180, 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35

Sc.2.0 (nm): 1999/180, 2000/150, 2001/130, 2002/115, 2003/100, 2004/90, 2005/80; 2008/60, 2011/40, 2014/30

Note: .7x/Node(.5x/2 Nodes): 2001/130; 04/90; 07/65; 10/45; 13/33; 16/23

b) MPU/ASIC Half-Pitch:1999: MPU/ASIC Half-Pitch Same, lagged typically 1-2 years behind DRAMSc.2.0: tied to DRAM: pull-in one year starting 160nm in 2001, then

~.7x/3yrs(.5x/6yrs) reduction rate

1999 (nm): 1999/230, 2000/210, 2001/180, 2002/160, 2003/145, 2004/130, 2005/115; 2008/80, 2011/55, 2014/40

Sc.2.0 (nm): 1999/230, 2000/190, 2001/160, 2002/145, 2003/130, 2004/115, 2005/100; 2008/70, 2011/50, 2014/35


6

Technology Node Assumptions (cont.):

c) MPU/ASIC “In Resist” Gate Length:

1999: MPU Gate Length 2-year node cycle (.7x/2yrs) to 2001, then 3-year node cycle (.7x/3yrs); ASIC Gate Length typically lagged ~1 node behind MPU

Sc.2.0 : 1. MPU Same as 1999 ITRS, except Variable ranges in 2002, 2011, 2014 replaced by single targets; 2. ASIC same as

MPU

1999 (nm): MPU: 1999/140 , 2000/120, 2001/100, 2002/85-90, 2003/80, 2004/70, 2005/65; 2008/45, 2011/30-32, 2014/20-22

ASIC: 1999/180 , 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35

Sc.2.0 (nm): MPU/ASIC: 1999/140 , 2000/120, 2001/100, 2002/90, 2003/80, 2004/70, 2005/65; 2008/45, 2011/33, 2014/23

d) NEW (Sc.2.0) (nm): MPU/ASIC “Physical Bottom” Gate Length line item targets added which are pulled-in 1 year from the Lithography “In Resist” targets.NEW (Sc.2.0) (nm): 1999/120, 2000/100, 2001/90, 2002/80, 2003/70, 2004/65,

2005/60; 2008/40, 2011/30, 2014/20

e) Litho TWG Proposal: Full 70% Reduction of Printed Gate Length from Sc.2.0, plus 1-year lead for “Physical Bottom Gate Length”

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (Technology Node):


7

Table 1a Product Generations and Chip Size Model Technology Nodes—Near TermYearsYEAR OF PRODUCTION

TECHNOLOGY NODE (1999 I TRS)1999

180 nm2000 2001 2002

130 nm2003 2004 2005

100 nmDRIVER

YEAR OF PRODUCTION

TECHNOLOGY NODE (SC. 2.0)1999

180 nm2000 2001

130 nm2002 2003 2004

90nm2005 DRIVER

Lithography- Based Characteristics

DRAM ½ Pitch (nm) (1999) 180 165 150 130 120 110 100 D ½

DRAM ½ Pitch (nm) (SC. 2.0) 180 150 130 115 100 90 80 D ½

MPU/ ASIC ½ Pitch (nm) (1999) 230 210 180 160 145 130 115 M AND A ½

MPU/ ASIC ½ Pitch (nm) (SC. 2.0)[Tied to DRAM]

230 190 160 145 130 115 100 M AND A ½

MPU Gate Length (nm) †† (1999) 140 120 100 85-90 80 70 65 M GATE

ASIC Gate Length (nm) (1999) 180 165 150 130 120 110 100 A GATE

MPU/ ASIC Gate Length (I n Resist) (nm) †† (SC. 2.0)

140 120 100 90 80 70 65 M AND AGATE

Physical Bottom Gate- Length

MPU/ASI C Gate Length (nm) ††[NEW]

120 100 90 80 70 65 60 COST/PERFORM

ANCE

=> Roadmap portion still under discussion


8

Table 1b Product Generations and Chip Size ModelTechnology Nodes—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION TECHNOLOGY NODE

(NOTE THAT PROPOSED NODE YEARS ARE NOW 2007/65NM;2010/45NM; 2013/33NM; 2016/23NM) (SC. 2.0)

2008[60 NM]

2011[40 NM]

2014[30 NM]

Lithography- Based Characteristics

DRAM ½ Pitch (nm) (1999) 70 50 35

DRAM ½ Pitch (nm) (SC. 2.0) 60 40 30

MPU/ ASIC ½ Pitch (nm) (1999) 80 55 40

MPU/ ASIC ½ Pitch (nm) (SC. 2.0) [Tied to DRAM] 70 50 35

MPU Gate Length (nm) †† (1999) 45 30-32 20-22

ASIC Gate Length (nm) (1999) 70 50 35

MPU/ ASI C Gate Length (I n Resist) (nm) †† (SC. 2.0) 45 33 23

Physical Bottom Gate- Length

MPU/ASI C Gate Length (nm) †† [NEW] 40 30 20

=> Roadmap portion still under discussion


9

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (cont.- DRAM):

DRAM Assumptions:

a) Cell Area Factor Limits (from FEP TWG):

1999: 8x/1999 -> 6x/2002 -> 4.4x/2005 -> 3.0x/2011 -> 2.5x/2014

Sc.2.0: 8x/1999-2004, 6x/2005-2010, 4x/2011-16b) Cell Array Efficiency Limit Trends (from FEP, Nikkei Microdevices):

1999: Intro: 1999/70% --> 2016/75%

Sc.2.0: Intro: 1999/70% --> 2016/75%1999: Production 1999/53% --> 2016/57%

Sc.2.0: Production 1999/53% --> 2016/58%c) Litho Field Size (from Litho TWG):

1999: 4x Magnification, 6-inch Reticle

Intro 1999-2016 25x32 = 800mm2

Production 1999-2016 12.5x32 = 400mm (2 chips/field)

Sc.2.0: 5x Magnification, 6-inch ReticleIntro 2004-2016 22x26 = 572mm2Production 2004-2016 11x26 = 286mm2 (2

chips/field)d) Bits/Chip Product Generation Growth Rate:

1999: 1999-2014:2x bits/chip every 2 years

Sc.2.0: @ Introduction: Through 8Gbit: 2x bits/chip every 2 years;After 8Gbit: 2x bits/chip every 2-3 years (4x/5years)

@ Production: Through 32Gbit: 2x bits/chip every 2 years;After 32Gbit: 2x bits/chip every 2-3 years (4x/5years)


10

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (cont.- Logic):

MPU Assumptions:

a) High Performance (HP) MPU @Ramp Starting Chip Size:

WAS: 2Mbyte on-chip (6t) SRAM in 1999

(170mm2 Core plus 280mm2 SRAM = 450mm2/1999)

IS: 1Mbyte on-chip (6t) SRAM in 1999 (170mm2 Core plus 140mm2 SRAM =

310mm2/1999)b) Cost Performance (CP) Starting Chip Size (SAME as 1999 ITRS):

MPU @Introduction/340mm2

MPU @Ramp/170mm2

c) SRAM and Logic Transistors/chip Trend (SAME as ITRS) = 2x/2yrs

d) Chip Size Growth Rate Trend

WAS/ IS: Flat chip sizes through 2001, then 1.2x/4rs


11

Table 1c-j Product Generations and Chip Size Model—[Assumptions, Notes]†† MPU and ASIC Gate-length (In Resist) node targets refer to most aggressive requirements,as printed in photoresist (which was by definition also “as etched in polysilicon”, in the 1999 ITRS).

NEW: Trends have been identified, in which the MPU and ASI C “physical bottom” gatelengths may be reduced from the “as- printed” dimension. These “physical bottom” gate- lengthtargets are also included in the FEP, PI Ds, and Design TWG Tables as needs which drivedevice and process technology requirements.

§ DRAM Model—Cell Factor (design/process improvement) targets are: 1999- 2004/8x;2005- 2010/6x; 2011- 2016/4x. DRAM product generations are usually increased by 4

bits/ chip every four years with interim 2 bits/ chip generations, except: 1) at theI ntroduction phase, after the 8Gbit interim generation, the introduction rate is4x/5years (2x/2- 3yrs); and 2) at the Production phase, after the interim 32Gbitgeneration, the introduction rate is 4x/5years (2x/2- 3yrs). InTER-generation chip size

growth rate varies to maintain 1 chip per 572mm2 field at Introduction and 2 chip per

572mm2 field at Production. The more aggressive “best case opportunity” technologynode trends allow the Production- phase products to remain at 2x bits/chip every 2 years

and still fit within the target of two DRAM chips per 572mm2 field size, through the32Gbit interim generation. The InTRA-generation chip size shrink model is 0.5 everytechnology node in- between cell factor reductions.

Note: Long- Term nodes now fall on: 2010/45; 2013/33; 2016/25

Chip Size - Model Assumptions, Notes, Tables


12

Table 1c-j Product Generations and Chip Size Model—[Assumptions, Notes]

* p is processor, numerals reflect year of introduction, c is cost-performance product.

** p is processor, numerals reflect year at ramp, h is high-performance product.

† MPU Cost-performance Model—Cost-performance MPU includes small level 1 (L1) on-chipSRAM (32Kbyte/ 1999), but consists primarily of logic transistor functionality; both SRAM andLogic functionality doubles every two years.

‡ MPU High-performance Model—High-performance MPU includes large level 2 (L2) on-chipSRAM (2MByte/ 1999) added to ramp-level cost-performance core functionality shrunk from 2-year-prior generation (P99h = 11.9M transistor (Mtransistors) (shrunk P97 core) +98Mtransistors (2048 bytes 8 bits/ byte 6 transistors/ bit) L2 SRAM =110Mtransistors/ 1999); both SRAM and Logic functionality doubles every two years.

‡ MPU High-performance Model—High-performance MPU includes large level 2 (L2) on-chipSRAM (1MByte/ 1999) added to ramp-level cost-performance core functionality shrunk from 2-year-prior generation (P99h = 11.9M transistor (Mtransistors) (shrunk P97 core) +49Mtransistors (1024 bytes 8 bits/ byte 6 transistors/ bit) L2 SRAM = 61Mtransistors/ 1999);both SRAM and Logic functionality doubles every two years.

§§ MPU Chip Size Model—Both the cost-performance and high-performance MPUs InTER-generation chip size growth rates can be kept flat through 2001, due to the moreaggressive MPU/ASI C half- pitch technology node trend; but beyond 2001, the target growthrate is 1.2 growth every four years. The InTRA-generation chip size shrink model is 0.5 everytwo years through 2001, then 0.5 every three years after 2001.

Chip Size - Model Assumptions, Notes, Tables (cont. - MPU)


13

Part 2 -

DRAM Tables( Note that target node years for Scenario 2.0 are now proposed to be: 1999/180nm;

2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm; 2016/23nm)


14

[This Page Left Intentionally Blank]


15

Table 1c DRAM Production Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION

TECHNOLOGY (1999 I TRS)1999

180 nm2000 2001 2002

130 nm2003 2004 2005

100 nmDRIVER

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005 DRIVER

DRAM ½ Pitch [f] (nm) (1999) 180 165 150 130 120 110 100 D ½

DRAM ½ Pitch [f] (nm) SC. 2.0) 180 150 130 115 100 90 80 D ½

Cell area factor [A] (1999) 8.0 7.3 6.6 6.0 5.4 4.9 4.4 Market —Cost/ Timing

Cell area factor [A] (SC. 2.0) 8.0 8.0 8.0 8.0 8.0 8.0 6.0 Market —Cost/ Timing

Cell area [Ca = Af2] (m2) (1999) 0.26 0.20 0.15 0.10 0.08 0.059 0.044 Market —

Cost/ Timing

Cell area [Ca = Af2] (m2) (SC. 2.0) 0.26 0.18 0.13 0.10 0.082 0.065 0.039 Market —

Cost/ Timing

Cell array area at production(% of chip size) § (1999)

53% — 55% — 53% — 54% Market —Cost/ Timing

Cell array area at production(% of chip size) § (SC. 2.0)

53.0% 54.0% 54.8% 55.3% 55.7% 56.1% 56.4% Market —Cost/ Timing

Generation at production § (1999)/ (SC. 2.0) 256M — 512M — 1G — 2G Market —Cost/ Timing

Functions per chip (Gbits) [NEW] 0.268 0.380 0.537 0.759 1.07 1.52 2.15 Market —Cost/Timing

Chip size at production (mm2) § (1999) 132 — 145 — 159 — 174 Market —Cost/ Timing

Chip size at production (mm2) § (SC. 2.0) 131 129 127 141 157 175 147 Market —Cost/ Timing

Gbits/ cm2 at production § (1999) 0.20 — 0.37 — 0.68 — 1.23 Market —

Cost/ Timing

Gbits/ cm2 at production § (SC. 2.0) 0.20 0.29 0.42 0.54 0.68 0.87 1.46 Market —

Cost/ Timing


16

Table 1d DRAM Production Product Generations and Chip SizeModel—Long Term YearsYEAR OF PRODUCTION

TECHNOLOGY NODE (1999 ITRS)2008

70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 nm]

2011[40 nm]

2014[30 nm]

DRAM ½ Pitch [f] (nm) (1999) 70 50 35

DRAM ½ Pitch [f] (nm) (SC. 2.0) 60 40 30

Cell area factor [A] (1999) 3.5 3.0 2.5

Cell area factor [A] (SC. 2.0) 6.0 4.0 4.0

Cell area [Ca = Af2] (m2) (1999) 0.017 0.008 0.003

Cell area [Ca = Af2] (m2) (SC. 2.0) 0.019 0.0064 0.0032

Cell array area at production(% of chip size) § (1999)

52% 56% 57%

Cell array area at production (% of chip size) § (SC. 2.0) 57.3% 57.8% 58.2%

Generation at production § (1999) [5.7] 16G [45.2G]

Generation at production § (SC. 2.0) [6G] 16G [48G]

Functions per chip (Gbits) [NEW] 6.1 17.2 48.6

Chip size at production (mm2) § (1999) 199 229 262

Chip size at production (mm2) § (SC. 2.0) 205 191 268

Gbits/ cm2 at production § (1999) 3.05 7.51 18.5

bits/ cm2 at production § (SC. 2.0) 2.97 8.99 18.1


17

Table 1e DRAM Introduction Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION

TECHNOLOGY (1999 ITRS)1999

180 nm2000 2001 2002

130 nm2003 2004 2005

100 nmDRIVER

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005 DRIVER

DRAM ½ Pitch [f] (nm) (1999) 180 165 150 130 120 110 100 D ½

DRAM ½ Pitch [f] (nm) (SC. 2.0) 180 150 130 115 100 90 80 D ½

Cell area factor [A] (1999) 8.0 7.3 6.6 6.0 5.4 4.9 4.4 Market —Cost/ Timing

Cell area factor [A] (SC. 2.0) 8.0 8.0 8.0 8.0 8.0 8.0 6.0 Market —Cost/ Timing

Cell area [Ca = Af2] (m2) (1999) 0.26 0.20 0.15 0.10 0.08 0.059 0.044 Market —

Cost/ Timing

Cell area [Ca = Af2] (m2) (SC. 2.0) 0.259 0.183 0.130 0.103 0.082 0.065 0.039 Market —

Cost/ Timing

Cell array area at introduction(% of chip size) § (1999)

70% — 72% — 70% — 72% Market —Cost/ Timing

Cell array area at introduction(% of chip size) § (SC. 2.0)

69.5% 70.5% 71.3% 71.8% 72.2% 72.6% 72.9% Market —Cost/ Timing

Generation at introduction § (1999) 1G — 2G — 4G — 8G —

Generation at introduction § (SC. 2.0) 1G — 2G — 4G — 8G —

Functions per chip (Gbits) (1999) 1.07 — 2.15 — 4.29 — 8.59 Market —Moore’s Law

Functions per chip (Gbits) (SC. 2.0) 1.07 1.52 2.15 3.04 4.29 6.07 8.59 Market —Cost/Timing

Chip size at introduction (mm2) § (1999) 400 — 438 — 480 — 526 Market —Cost/ Timing

Chip size at introduction (mm2) § (SC. 2.0) 400 395 390 435 485 542 454 Market —Cost/ Timing

Gbits/ cm2 at introduction § (1999) 0.27 — 0.49 — 0.89 — 1.63 Market —

Cost/ Timing

Gbits/ cm2 at introduction § (SC. 2.0) 0.27 0.38 0.55 0.70 0.88 1.12 1.89 Market —

Cost/ Timing


18

Table 1f DRAM Introduction Product Generations and Chip SizeModel—Long Term YearsYEAR OF PRODUCTION

TECHNOLOGY (1999 I TRS)2008

70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 NM]

2011[40 NM]

2014[30 NM]

DRAM ½ Pitch [f] (nm) (1999) 70 50 35

DRAM ½ Pitch [f] (nm) (SC. 2.0) 60 40 30

Cell area factor [A] (1999) 3.5 3.0 2.5

Cell area factor [A] (SC. 2.0) 6.0 4.0 4.0

Cell area [Ca = Af2] (m2) (1999) 0.017 0.008 0.003

Cell area [Ca = Af2] (m2) (SC. 2.0) 0.019 0.0064 0.0032

Cell array area at introduction (% of chip size) § (1999) 69% 75% 75%

Cell array area at introduction% of chip size) § (SC. 2.0) 73.3% 74.3% 74.7%

Generation at introduction § (1999) [22.6G] 64G [181G]

Generation at introduction § (SC. 2.0) [20G] [45G] [104G]

Functions per chip (Gbits) (1999) 24.3 68.7 194

Functions per chip (Gbits) (SC. 2.0) 19.7 45.3 104.2

Chip size at introduction (mm2) § (1999) 603 691 792

Chip size at introduction (mm2) § (SC. 2.0) 516 392 448

Gbits/ cm2 at introduction § (1999) 4.03 9.94 24.5

Gbits/ cm2 at introduction § (SC. 2.0) 3.82 11.56 23.25


19

DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal ["I S", 7/11/00]:

Year 1999 2000 2001 2002 2003 2004 2005 2006 Technol ogy Node [ WAS, 1999] 180 130 100

Technol ogy Node [ I S, 7/ 11/ 00] 180 130 90F ( nm) [ r ounded, I S] 180 150 130 115 100 90 80 70

F ( nm) [ act ual ****, I S] 180 151. 361 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4Cel l Ar ea Fact or , I S 8 8 8 8 8 8 6 6Cel l Ar ea ( um2) , I S 0. 259 0. 183 0. 130 0. 103 0. 082 0. 065 0. 039 0. 031DRAM @ Introduction, IS Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*Gbi t / Chi p ( var . **) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 11. 33

DRAM Pr oductCel l effi ci ency 69. 5% 70. 5% 71. 3% 71. 8% 72. 2% 72. 6% 72. 9% 73. 2%

Tot al Cel l Ar ea ( mm2) 278 278 278 312 351 394 331 347Chi p Si ze ( mm2) 400 395 390 435 485 542 454 474

Densi t y ( Gbi t s/ cm2) 0. 27 0. 38 0. 55 0. 70 0. 88 1. 12 1. 89 2. 39DRAM @ Production, IS Const ant bi t per / chi p gr owt h per schedul e bel ow***

Gbi t / Chi p ( const . ***) 0. 27 0. 38 0. 54 0. 76 1. 07 1. 52 2. 15 3. 04DRAM Pr oduct

Cel l effi ci ency 53. 0% 54. 0% 54. 8% 55. 3% 55. 7% 56. 1% 56. 4% 56. 7%Tot al Cel l Ar ea ( mm2) 70 70 70 78 88 98 83 93

Chi p Si ze ( mm2) 131 129 127 141 157 175 147 164Densi t y ( Gbi t s/ cm2) 0. 20 0. 29 0. 42 0. 54 0. 68 0. 87 1. 46 1. 85

Bi t / Chi p Gr owt h/ yr ( var . **) 1. 41421 For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)Bi t / Chi p Gr owt h/ yr ( var . **) 1. 31951 For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)

Gbi t / Chi p ( annual i ze*) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 12. 15DRAM Pr oduct 1G 2G 4G 8G

Bi t / Chi p Gr owt h/ yr ( const . ***) 1. 41421 For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)

New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e

**** "act ual " = cal cul at ed st ar t i ng f r om 130nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on

Not e: = 1999 I TRS, 2000 Updat e Year Header s

= 2001 I TRS Year Header s

1G

256M 512M 1G 2G

2G 4G 8G


20

DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont):

2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016100 70 50 35

65 45 33 2380 70 65 60 50 45 40 35 33 30 25 23

80. 2 71. 4 63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 56 6 6 6 6 6 4 4 4 4 4 4

0. 039 0. 031 0. 024 0. 019 0. 015 0. 012 0. 0064 0. 0051 0. 0041 0. 0032 0. 0026 0. 0020Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*

8. 59 11. 33 14. 96 19. 73 26. 04 34. 36 45. 34 59. 82 78. 94 104. 16 137. 44 181. 35

72. 9% 73. 2% 73. 5% 73. 8% 74. 0% 74. 2% 74. 3% 74. 5% 74. 6% 74. 7% 74. 8% 74. 9%331 347 363 381 399 417 291 305 320 335 351 367454 474 494 516 539 563 392 410 429 448 469 4901. 89 2. 39 3. 03 3. 82 4. 83 6. 10 11. 56 14. 60 18. 42 23. 25 29. 33 37. 00

Const ant bi t per / chi p gr owt h per schedul e bel ow***2. 15 3. 04 4. 29 6. 07 8. 59 12. 15 17. 18 24. 30 34. 36 45. 34 59. 82 78. 94

56. 4% 56. 7% 57. 0% 57. 3% 57. 5% 57. 7% 57. 8% 58. 0% 58. 1% 58. 2% 58. 3% 58. 4%83 93 104 117 131 148 110 124 139 146 153 160147 164 183 205 229 256 191 214 239 250 262 2741. 46 1. 85 2. 35 2. 97 3. 75 4. 75 8. 99 11. 36 14. 35 18. 11 22. 86 28. 85

For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)

8. 59 12. 15 17. 18 24. 30 34. 36 48. 59 68. 72 97. 18 137. 44 194. 37 274. 88 388. 748G 16G 32G 64G 128G 256G

For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)



= 1999 I TRS, 2000 Updat e Year Header s

* 16G 32G 2G 4G

8G

8G

* 128G 32G *


21

Part 3 -

MPU/ASIC Tables( Note that target node years for Scenario 2.0 are now proposed to be: 1999/180nm;

2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm;

2016/23nm)


22



23

Table 1g MPU (High- volume Microprocessor) Cost- PerformanceProduct Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nmDRIVER

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005 DRIVER

Process/ design annual improvement factor ++ (1999) 0.90 0.90 0.90 0.91 0.92 0.93 0.93 Market —Cost/ Timing

(SC. 2.0) 1.00 1.00 1.00 0.93 0.93 0.93 0.93

Transistor density SRAM at introduction

(Mtransistors/ cm2) (1999)/ (SC. 2.0)

35 50 70 95 128 173 234 Market —Cost/ Timing

Transistor density logic at introduction

(Mtransistors/ cm2) (1999)/ (SC. 2.0)

6.6 9.4 13 18 24 33 44 Market —Cost/ Timing

Generation at introduction * (1999)/ (SC. 2.0) p99c — p01c — p03c — p05c —

Functions per chip (million transistors [Mtransistors]) (1999)

23.8 — 47.6 — 95.2 — 190 Market —Moore’s Law

(1999)/(SC. 2.0) 23.8 33.7 47.6 67.3 95.2 135 190

Chip size at introduction (mm2) ‡ (1999) 340 — 340 — 372 — 408 Market —Cost/ Timing

(SC. 2.0) 340 340 340 356 372 390 408

Cost performance MPU (Mtransistors/ cm2 at

introduction) (including on-chip SRAM) ‡ (1999)

7 — 14 — 26 — 47 M Gate and

M and A ½

(SC. 2.0) 7.0 9.9 14.0 18.9 25.6 34.5 46.7

Generation at production * p97c — p99c — p01c — P03c —

Chip size at production (mm2) §§ (1999) 170 — 170 — 214 — 235 Market —Cost/ Timing

(SC. 2.0) 170 170 170 178 186 195 204

Cost performance MPU (Mtransistors/ cm2 at

production, including on-chip SRAM) ‡ (1999)

7 — 14 — 22 — 41 M Gate and

M and A ½

(SC. 2.0) 7.0 9.9 14.0 18.9 25.6 34.5 46.7

++ The MPU Process/ design improvement factor is an estimate of the additional annual functional area reductionrequired beyond the area reduction contributed by the MPU metal half-pitch reduction. Note that thisadditional area reduction for transistor density plays a role generally analogous to the "cell area factor" forDRAMs. I t has been achieved historically through a combination of many factors, for example: use ofadditional interconnect levels, self-alignment techniques, and more efficient circuit layout.


24

Table 1h MPU (High- volume Microprocessor) Cost- PerformanceProduct Generations and Chip Size Model—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE

(NOTE THAT PROPOSED NODE YEARS ARE NOW 2007/65NM; 2010/45NM; 2013/33NM;2016/23NM) (SC. 2.0)

2008[60 NM]

2011[40 NM]

2014[30 NM]

Process/ design improvement factor (1999) 0.93 0.93 0.93

(SC. 2.0) 0.93 0.93 0.93

Transistor density SRAM at introduction (Mtransistors/ cm2) (1999)/ (SC. 2.0) 577 1,423 3,510

Transistor density logic at introduction (Mtransistors/ cm2) (1999)/ (SC. 2.0) 109 269 664

Generation at introduction * (1999)/ (SC. 2.0) — p11c —

Functions per chip (million transistors (Mtransistors) (1999)/ (SC. 2.0) 539 1,523 4,308

Chip size at introduction (mm2) ‡ (1999) 468 536 615

(SC. 2.0) 468 536 615

Cost-performance MPU Mtransistors/ cm2 at introduction (including on-chip SRAM) ‡

(1999)

115 284 701

(SC. 2.0) 115 284 701

Generation at production * (1999)/ (SC. 2.0) — p09c —

Chip size at production (mm2) § (1999)/ (SC. 2.0) 269 308 354

(SC. 2.0) 234 268 307

Cost performance MPU Mtransistors/ cm2 at production

(including on-chip SRAM) ‡ (1999)

100 247 609

(SC. 2.0) 115 284 701


25

Table 1i High- Performance MPU and ASIC Product Generationsand Chip Size Model—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nmDRIVER

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005 DRIVER

Logic (Low-volume Microprocessor) High-performance ‡

Generation at production ** (1999)/ (SC. 2.0) p99h — p01h — p03h — p05h —

Functions per chip (million transistors) (1999) 110 — 220 — 441 — 882 Market —Moore’s Law

(SC. 2.0) 61 86 122 173 244 345 488

Chip size at production (mm2) § (1999) 450 — 450 — 567 — 622 Market —Cost/ Timing

(SC. 2.0) 310 310 310 325 340 356 372

High-performance MPU Mtransistors/ cm2 at

production (including on-chip SRAM) ‡ (1999)

24 — 49 — 78 — 142 M Gate and

M and A ½

(SC. 2.0) 19.7 27.8 39.4 53.2 71.9 97.1 131

ASIC

ASIC usable Mtransistors/ cm2 (auto layout) (1999) 20 28 40 54 73 99 133 M Gate and

M and A ½(SC. 2.0) 19.7 27.8 39.4 53.2 71.9 97.1 131

ASIC max chip size at production (mm2) (maximumlithographic field size) (1999)

800 800 800 800 800 800 800 LithographicField Size

(SC. 2.0) 800 800 800 800 572 572 572

ASIC maximum functions per chip at production(Mtransistors/ chip) ( fit in maximum lithographicfield size) (1999)

160 224 320 432 584 800 1064 Market —Performance/

Timing

(SC. 2.0) 157 223 315 426 411 556 751


26

Table 1j High- Performance MPU and ASIC Product Generations andChip Size Model—Long Term Years

YEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 NM]

2011[40 NM]

2014[30 NM]

Logic (Low-volume Microprocessor) High-performance ‡

Generation at production ‡ (1999)/ (SC. 2.0) — p11h —

Functions per chip (million transistors) (1999) 2,494 7,053 19,949

(SC. 2.0) 1,381 3,907 11,052

Chip size at production (mm2) § (1999) 713 817 937

(SC. 2.0) 427 489 561

High-performance MPU Mtransistors/ cm2 at production (including

on-chip SRAM) ‡ (1999 )

350 863 2,130

(SC. 2.0) 324 799 1,970

ASIC

ASIC usable Mtransistors/ cm2 (auto layout) (1999) 328 811 2,000

(SC. 2.0) 324 799 1,970

ASIC maximum chip size at production (mm2)(maximum lithographic field size) (1999)

800 800 800

(SC. 2.0) 572 572 572

ASIC maximum functions per chip at ramp (Mtransistors/ chip)(fit in maximum lithographic field size) (1999)

2,624 6,488 16,000

(SC. 2.0) 1,852 4,568 11,269

Since only the 2011 odd-year product generation data column is available in the Long Term table format,interpolated numbers were calculated and included in the 2008 and 2014 node columns. The extendedmarket-need-based product trends for the product generation two-year-cycle years (1999, 2001, 2003,2005, 2007, 2009, 2011, 2013) are forecast to follow patterns established in Near Term Table 1a.


27

MPU/ASIC (M/A) ORTC Chip Size Model Per IRC Technology Node Proposal ["I S", 7/11/00]:

Year 1999 2000 2001 2002 2003 2004 2005 2006 Technol ogy Node [ WAS, 1999] 180 130 100

Technol ogy Node [ I S, 7/ 11/ 00] 180 130 90F ( nm) [ r ounded, 7/ 11] 180 150 130 115 100 90 80 70

F ( nm) [ act ual ****, 7/ 11] 180 151. 361 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4M/ A [ r ounded] :

M/ A H- Pi t ch ( nm) [ WAS, 1999] 230 210 180 160 145 130 115M/ A H- Pi t ch ( nm) [ I S, 7/ 11/ 00] 230 190 160 145 130 115 100 90

MPU Pr i nt ed G- Lengt h ( nm) [ WAS, 1999] 140 120 100 85- 90 80 70 65M/ A Pr i nt ed G- Lengt h ( nm) [ I S, 7/ 11/ 00] 140 120 100 90 80 70 65 60

M/ A Physi cal G- Lengt h ( nm) [ NEW, 7/ 11/ 00] 120 100 90 80 70 65 60 50M/ A [ act ual ****] :

M/ A H- Pi t ch ( nm) , I S 226. 8 190. 7 160. 4 142. 9 127. 3 113. 4 101. 0 90. 0M/ A Pr i nt ed G- Lengt h ( nm) I S 142. 9 120. 1 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7

M/ A Physi cal G- Lengt h ( nm) [ NEW] 120. 1 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7 50. 5

Densi t y Gr owt h Rat e [ ( t / cm2) / yr ] : 2x/ 2yr s 1999- 2001; t hen

[ 2x/ 2yr s/ 1. 2x/ 4yr s] 1. 414 1. 414 1. 414 1. 351 1. 351 1. 351 1. 351 1. 351Densi t y Gr owt h Rat e Cont r i but i on Due t o

Li t ho. Reduct i on 1. 414 1. 414 1. 414 1. 260 1. 260 1. 260 1. 260 1. 260Tr ansi st or Desi gn/ Pr ocess Annual

I mpr ovement Fact or Requi r ed 1. 00 1. 00 1. 00 0. 93 0. 93 0. 93 0. 93 0. 93SRAM Tr . Densi t y ( Mt / cm2) 35 50 70 95 128 173 234 316Logi c Tr . Densi t y ( Mt / cm2) 6. 6 9. 4 13 18 24 33 44 60

Cost-Perf. MPU @ Introduction, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM Mt / chi p 1. 5 2. 2 3. 1 4. 3 6. 1 8. 7 12. 3 17. 4Logi c Mt / chi p 22. 3 31. 5 44. 5 63. 0 89. 1 125. 9 178. 1 251. 9Tot al Mt / chi p 23. 8 33. 7 47. 6 67. 3 95. 2 135 190 269

SRAM Ar ea ( mm2) 4. 4 4. 4 4. 4 4. 6 4. 8 5. 0 5. 3 5. 5Logi c Ar ea ( mm2) 335. 6 335. 6 335. 6 351. 3 367. 7 384. 8 402. 7 421. 5

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 340 340 340 356 372 390 408 427Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 18. 9 25. 6 34. 5 46. 7 63. 1

Cost-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM ( Level 1) Mt / chi p 0. 8 1. 1 1. 5 2. 2 3. 1 4. 3 6. 1 8. 7Logi c Mt / chi p 11. 1 15. 7 22. 3 31. 5 44. 5 63. 0 89. 1 125. 9Tot al Mt / chi p 12 17 24 34 48 67 95 135

SRAM Ar ea ( mm2) 2. 2 2. 2 2. 2 2. 3 2. 4 2. 5 2. 6 2. 8Logi c Ar ea ( mm2) 167. 8 167. 8 167. 8 175. 6 183. 8 192. 4 201. 4 210. 8

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 170 170 170 178 186 195 204 214Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 18. 9 25. 6 34. 5 46. 7 63. 1

High-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM ( on- chi p Level 2) Mt / chi p 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0 393. 2 556. 1Logi c ( Cor e, i ncl . L1 SRAM) Mt / chi p 11. 9 16. 8 23. 8 33. 7 47. 6 67. 3 95. 2 134. 6

Tot al Mt / chi p 61 86 122 173 244 345 488 691SRAM Ar ea ( mm2) 140. 2 140. 2 140. 2 146. 7 153. 5 160. 7 168. 2 176. 0Logi c Ar ea ( mm2) 170. 0 170. 0 170. 0 177. 9 186. 2 194. 9 204. 0 213. 5

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 310 310 310 325 340 356 372 390Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 19. 7 27. 8 39. 4 53. 2 71. 9 97. 1 131 177

High-Perf. ASIC @ Production, ISTot al Mt / chi p 157 223 315 426 411 556 751 1014

Chi p Si ze ( mm2) [ max. Li t ho Fi el d] 800 800 800 800 572 572 572 572Usabl e Tr ansi st or Densi t y ( Mt / cm2) 19. 7 27. 8 39. 4 53. 2 71. 9 97. 1 131 177



Not e: = 1999 I TRS, 2000 Updat e Year Header s

= 2001 I TRS Year Header s

p97c p99c

p99h p01h p03h p05h

p01c p03c

p99c p01c p03c p05c

2007 2008 2009 2010 2011 2012 2013 2014 2015 201670 50 35

65 45 33 2365 60 50 45 40 35 33 30 25 23

63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5

80 55 4080 70 65 60 50 45 40 35 33 30

45 30- 32 20- 2250 45 40 35 33 30 25 23 20 1845 40 35 33 30 25 23 20 18 16

80. 2 71. 4 63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 350. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5 20. 0 17. 945. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5 20. 0 17. 9 15. 9

1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351

1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260

0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93427 577 779 1053 1423 1922 2598 3510 4743 640881 109 147 199 269 364 491 664 897 1212

24. 6 34. 8 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0 393. 2 556. 1356. 2 503. 8 712. 4 1007. 6 1424. 9 2015. 1 2849. 8 4030. 2 5699. 6 8060. 4381 539 762 1077 1523 2154 3046 4308 6093 86175. 8 6. 0 6. 3 6. 6 6. 9 7. 2 7. 6 7. 9 8. 3 8. 7

441. 2 461. 8 483. 3 505. 8 529. 4 554. 1 580. 0 607. 0 635. 3 664. 9447 468 490 512 536 561 588 615 644 67485. 2 115. 1 155. 6 210. 2 284. 0 383. 7 518. 5 700. 6 946. 7 1279. 2

12. 3 17. 4 24. 6 34. 8 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0178. 1 251. 9 356. 2 503. 8 712. 4 1007. 6 1424. 9 2015. 1 2849. 8 4030. 2190 269 381 539 762 1077 1523 2154 3046 43082. 9 3. 0 3. 2 3. 3 3. 5 3. 6 3. 8 4. 0 4. 1 4. 3

220. 6 230. 9 241. 6 252. 9 264. 7 277. 1 290. 0 303. 5 317. 7 332. 5223 234 245 256 268 281 294 307 322 33785. 2 115. 1 155. 6 210. 2 284. 0 383. 7 518. 5 700. 6 946. 7 1279. 2

786. 4 1112 1573 2224 3146 4449 6291 8897 12583 17795190. 4 269. 3 380. 8 538. 5 761. 6 1077. 1 1523. 2 2154. 1 3046. 4 4308. 3977 1381 1954 2763 3907 5526 7815 11052 15629 22103

184. 2 192. 8 201. 8 211. 2 221. 1 231. 4 242. 2 253. 5 265. 3 277. 7223. 5 233. 9 244. 8 256. 2 268. 2 280. 7 293. 8 307. 5 321. 8 336. 8408 427 447 467 489 512 536 561 587 614240 324 437 591 799 1079 1458 1970 2662 3597

1370 1852 2502 3381 4568 6172 8340 11269 15227 20575572 572 572 572 572 572 572 572 572 572240 324 437 591 799 1079 1458 1970 2662 3597


p05c p07c p09c p11c

p07h p09h

p15c

p11h p13h p15h

p13c

p07c p09c p11c p13c


28



29

Part 4 -

Other ORTC Table TWG Line Items

( Note that target node years for Scenario 2.0 are now proposed to be: 1999/180nm;

2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm; 2016/23nm)


30

Other ORTC Table TWG Line Items- Table 2a,b Litho Field Size Litho

Wafer Size FEP, FI

- Table 3a,b # of Chip I/O’s Test, Design

# of Package Pins/Balls Test, A&P

- Table 4a,b Chip Pad Pitch A&P

Cost-Per-Pin A&P

Chip Frequency Design

Chip-to-Board Frequency A&P

Max # Wire Levels Interconnect

- Table 5a,b Electrical Defects Def. Reduct.

- Table 6a,b P.Supply Volt. PIDs

Max. Power Design, PIDs

- Table 7a,b Affordable Cost Economic (AA actg)

Test Cost Test


31

Table 2a Chip-Size, Lithographic-Field and Wafer-Size Trends—Near Term Years(Note: 1999 Lithographic field sizes represent current capability)

YEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE (SC. 2.0 )1999

180 nm2000 2001

130 nm2002 2003 2004

90nm2005

Lithography Field Size

Maximum lithographic field size — area (mm2) (1999) 800 800 800 800 800 800 800

Lithography Field Size—area (mm2) (SC. 2.0) 800 800 800 800 800 572 572

Maximum lithographic field size — length (mm) (1999) 32 32 32 32 32 32 32

Maximum lithographic field size — width (mm) (1999) 25 25 25 25 25 25 25

Lithographic field size (width X length [mm2]) (SC. 2.0) 25x32 25x32 25x32 25x32 25x32 22x26 22x26

Maximum Substrate Diameter (mm) — High-volume Production (>20K wafer starts per month)

Bulk or epitaxial or SOI wafer (1999) 200 200 300 300 300 300 300

(SC. 2.0) 200 200 300 300 300 300 300


32

Table 2b Chip-Size, Lithographic-Field and Wafer Size Trends—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE

(NOTE THAT PROPOSED NODE YEARS ARE NOW 2007/65NM; 2010/45NM;2013/33NM; 2016/23NM) (SC. 2.0)

2008[60 NM]

2011[40 NM]

2014[30 NM]

Lithography Field Size

Maximum lithographic field size—area (mm2) (1999) 800 800 800

Lithography Field Size—area (mm2) (SC. 2.0)572 572 572

Maximum lithographic field size—length (mm) (1999) 32 32 32

Maximum lithographic field size—width (mm) (1999) 25 25 25

Lithographic field size (width X length [mm2]) (SC. 2) 22x26 22x26 22x26

Maximum Substrate Diameter (mm)—High-volume Production (>20K wafer starts per month)

Bulk or epitaxial or SOI wafer (1999) 300 300 450

(SC. 2.0) 300 450 450


33

Table 3a Performance of Packaged Chips: Number of Pads and Pins

—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE (SC. 2.0 )1999

180 nm2000 2001

130 nm2002 2003 2004

90 nm2005

Number of Chip I/Os (Number of Total Chip Pads) — Maximum

Total pads—MPU (1999)/ (SC. 2.0) 2,304 2,560 3,042 3,042 3,042 3,042 3,042

Signal I / O—MPU (1/ 3 of total pads) (1999)/(SC. 2.0) 768 1,024 1,024 1,024 1,024 1,024 1,024

Power and ground pads—MPU (2/ 3 of total pads) (1999)/ (SC. 2.0) 1,536 1,536 2,018 2,018 2,018 2,018 2,018

Total pads—ASIC high-performance (1999)/(SC. 2.0) 1,400 1,800 2,200 2,600 3,000 3,400 3,800

Signal I / O pads—ASIC high-performance (½ of total pads) (1999)/ (SC. 2.0)

700 900 1,100 1,300 1,500 1,700 1,900

Power and ground pads—ASIC high-performance (½ of total pads) (1999)/(SC. 2.0)

700 900 1,100 1,300 1,500 1,700 1,900

Chip-to-package pads (Peripheral) (1999)/ (SC. 2.0) 368 397 429 464 501 541 584

Number of Total Package Pins/Balls—Maximum

Microprocessor/ controller, cost-performance (1999)/ (SC. 2.0) 740 821 912 1,012 1,123 1,247 1,384

ASIC (high-performance) (1999)/(SC. 2.0) 1,600 1,792 2,007 2,248 2,518 2,820 3,158


34

Table 3b Performance of Packaged Chips: Number of Pads and Pins—Long Term Years

YEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 nm]

2011[40 nm]

2014[30 nm]

Number of Chip I/Os (Number of Total Chip Pads)—Maximum

Total pads—MPU (1999)/ (SC. 2.0) 3,840 4,224 4,416

Signal I / O pads—MPU (1/ 3 of total pads) (1999)/ (SC. 2.0) 1,280 1,408 1,472

Power and ground pads—MPU (2/ 3 of total pads) (1999)/ (SC. 2.0) 2,560 2,816 2,944

Total pads—ASIC high-performance (1999)/ (SC. 2.0) 4,600 5,400 6,000

Signal I / O pads—ASIC high-performance(½ of total pads) (1999)/ (SC. 2.0)

2,300 2,700 3,000

Power and ground pads—ASIC high-performance (½ of total pads) (1999)/ (SC. 2.0)

2,300 2,700 3,000

Chip-to-package pads (Peripheral) (1999)/ (SC. 2.0) 736 927 1,167

Number of Total Package Pins/Balls—Maximum

Microprocessor/ controller, cost-performance (1999)/ (SC. 2.0) 1,893 2,589 3,541

ASIC (high-performance) (1999)/ (SC. 2.0) 4,437 6,234 8,758


35

Table 4a Performance and Package Chips: Pads, Cost, and Frequency—Near Term Years

YEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005

Chip Pad Pitch (micron)

Pad pitch—ball bond (1999) 50 48 47 45 43 42 40

(SC. 2.0) 50 50 45 35 30 25 20

Pad pitch—wedge bond (1999) 45 43 42 40 39 38 35

(SC. 2.0) 45 45 40 35 30 25 20

Package cost (cents/ pin) (cost-performance)—minimum (1999) 200 200 200 200 182 165 150

(SC. 2.0) 200 200 175 175 150 150 130

Pad Pitch—area array (handheld, low- cost, harsh) NEW 180 165 150 130 120 110 100

Cost-Per-Pin

Package cost (cents/ pin) (cost-performance)—maximum (1999) 1.90 1.81 1.71 1.63 1.55 1.47 1.40

(SC. 2.0) 1.90 1.40 1.33 1.26 1.20 1.14 1.08

Package cost (cents/ pin) (cost-performance)—minimum (1999)/ (SC. 2.0) 0.90 0.86 0.81 0.77 0.73 0.70 0.66

Package cost (cents/ pin) (Memory)—maximum (1999)/ (SC. 2.0) 1.90 1.71 1.54 1.39 1.25 1.12 1.01

Package cost (cents/ pin) (Memory)—minimum (1999)/ (SC. 2.0) 0.40 0.38 0.36 0.34 0.33 0.31 0.29


36

Table 4b Performance and Package Chips: Pads, Cost, and Frequency—Long Term Years

YEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE

(NOTE THAT PROPOSED NODE YEARS ARE NOW 2007/65NM; 2010/45NM; 2013/33NM;2016/23NM) (SC. 2.0)

2008[60 NM]

2011[40 NM]

2014[30 NM]

Chip Pad Pitch (micron)

Pad pitch—ball bond (1999) 40 40 40

(SC. 2.0) 20 20 20

Pad Pitch—wedge bond (1999) 35 35 35

(SC. 2.0) 20 20 20

Pad Pitch—area array (cost- performance, high- performance) (1999) 150 150 150

(SC. 2.0) 115 100 80

Pad Pitch—area array (handheld, low- cost, harsh) NEW 70 50 35

Cost-Per-Pin

Package cost (cents/ pin) (cost-performance)—maximum (1999) 1.20 1.03 0.88

(SC. 2.0) 1.03 0.98 0.93

Package cost (cents/ pin) (cost-performance)—minimum (1999)/ (SC. 2.0) 0.57 0.49 0.42

(1999)/(SC. 2.0) 0.74 0.54 0.39

Package cost (cents/ pin) (memory)—minimum (1999)/ (SC. 2.0) 0.25 0.22 0.19


37

Table 4a Performance and Package Chips: Pads, Cost, and Frequency,On- Chip Wiring Levels—Near Term Years

YEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90 nm2005

Chip Frequency (MHz)

On-chip local clock, (high-performance ) (1999) 1,250 1,486 1,767 2,100 2,490 2,952 3,500

(SC. 2.0) 1620 2,100 2,490 2,952 3,500 4,150

On-chip, across-chip clock (high-performance) (1999) 1,200 1,321 1,454 1,600 1,724 1,857 2,000

(SC. 2.0) 1,386 1,600 1,724 1,857 2,000 2,155

On-chip, across-chip clock, high-performance ASIC (1999) 500 559 626 700 761 828 900

(SC. 2.0) 592 700 761 828 900 980

On-chip, across-chip clock (cost-performance) (1999) 600 660 727 800 890 989 1,100

(SC. 2.0) 693 800 890 989 1,100 1,225

Chip-to-board (off-chip) speed(high-performance, reduced-width, multiplexed bus) (1999)

1,200 1,321 1,454 1,600 1,724 1,857 2,000

(SC. 2.0) 1386 1,600 1,724 1,857 2,000 2,155

Chip-to-board (off-chip) speed(high-performance, for peripheral buses) (1999)

480 589 722 885 932 982 1,035

(SC. 2.0) 480 693 800 862 929 1000 1078

Maximum number wiring levels—maximum (1999)/ (SC. 2.0) 7 7 7 8 8 8 9

Maximum number wiring levels—minimum (1999)/ (SC. 2.0) 6 6 7 7 8 8 8


38

Table 4b Performance and Package Chips: Pads, Cost, and Frequency, On- Chip Wiring Levels —Long Term Years

YEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 NM]

2011[40 NM]

2014[30 NM]

Chip Frequency (MHz)

On-chip local clock, (high-performance ) (1999) 6,000 10,000 13,500

(SC. 2.0) 7,115 11,050 14,920

On-chip, across-chip clock (high-performance) (1999) 2,500 3,000 3,600

(SC. 2.0) 2,655 3,190 3,825

On-chip, across-chip clock (high-performance ASIC) (1999) 1,200 1,500 1,800

(SC. 2.0) 1,295 1,595 1,913

On-chip, across-chip clock (cost-performance) (1999) 1,400 1,800 2,200

(SC. 2.0) 1,522 1,925 2,350

Chip-to-board (off-chip) speed(high-performance, reduced-width, multiplexed bus) (1999)

2,500 3,000 3,600

(SC. 2.0) 2,655 3,190 3,825

Chip-to-board (off-chip) speed (high-performance, for peripheral buses) (1999) 1,285 1,540 1,800

(SC. 2.0) 1328 1595 1913

Maximum number wiring levels—minimum (1999)/ (SC. 2.0) 9 10 10

Maximum number wiring levels—minimum (1999)/ (SC. 2.0) 9 9 10


39

Table 5a Electrical Defects—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005

Defect Reduction

DRAM at production electrical D0 chip size at 85% yield (d/ m2) § (1999) 1,249 1,193 1,140 1,089 1,040 994 950

(SC. 2.0) 1,259 1,282 1,302 1,170 1,050 942 1126

MPU at production electrical D0

chip size at 75% yield (d/ m2) §§ (1999)

1,742 1,742 1,742 1,552 1,383 1,321 1,262

(SC. 2.0) 1,742 1,742 1,742 1,664 1,590 1,519 1,452

ASIC first year electrical D0 at 65% yield (d/ m2) (1999) 562 562 562 562 562 562 562

(SC. 2.0) 562 562 562 562 787 787 787

Minimum, mask count—maximum (1999) 24 24 24 24 25 25 26

(SC. 2.0) 24 24 24 25 25 26 26

Minimum, mask count—minimum (1999) 22 23 23 24 24 24 24

(SC. 2.0) 22 23 24 24 24 24 24


40

Table 5b Electrical Defects—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 NM]

2011[40 NM]

2014[30 NM]

Defect Reduction

DRAM at production electrical D0 chip size at 85% yield (d/ m2) § (1999) 828 723 630

(SC. 2.0) 807 865 660

MPU at production electrical D0 chip size at 75% yield (d/ m2) §§ (1999) 1,101 960 837

(SC. 2.0) 1,266 1,104 963

ASIC first year electrical D0 at 65% yield (d/ m2) (1999) 562 562 562

(SC. 2.0) 787 787 787

Minimum, mask count—maximum (1999) 28 28 30

(SC. 2.0) 28 28 30

Minimum, mask count—minimum (1999) 26 28 29

(SC. 2.0) 26 28 29

D0 —defect density


41

Table 6a Power Supply and Power Dissipation—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005

Power Supply Voltage (V)

Minimum logic Vdd (V)—maximum (for maximumperformance) (1999)

1.8 1.8 1.5 1.5 1.5 1.2 1.2

(SC. 2.0) 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Minimum logic Vdd (V)—minimum (for lowest power)

(1999)

1.5 1.5 1.2 1.2 1.2 0.9 0.9

(SC. 2.0) 1.5 1.5 1.2 1.2 0.9 0.9 0.8

Maximum Power

High-performance with heatsink (W) 90 100 115 130 140 150 160

(SC. 2.0) 90 108 130 140 150 160 170

Battery (W)—(hand-held) (1999) 1.4 1.6 1.7 2.0 2.1 2.3 2.4

(SC. 2.0) 1.4 1.7 2.0 2.1 2.3 2.4 2.6


42

Table 6b Power Supply and Power Dissipation—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE ((NOTE THAT PROPOSED NODE YEARS ARE NOW 2007/65NM; 2010/45NM;2013/33NM; 2016/23NM) (SC. 2.0)

2008[60 NM§]

2011[40 NM§]

2014[30 NM§]

Power Supply Voltage (V)

Minimum logic Vdd (V)—maximum (for maximum performance) (1999) 0.9 0.6 0.60

(SC. 2.0) 0.9 0.6 0.60

Minimum logic Vdd (V)—minimum (for lowest power) (1999) 0.6 0.5 0.30

(SC. 2.0) 0.6 0.5 0.30

Maximum Power

High-performance with heatsink (W) (1999) 170 174 183

(SC. 2.0) 171 177 186

Battery (W)—(hand-held) (1999) 2.0 2.2 2.4

(SC. 2.0) 2.1 2.3 2.5


43

Table 7a Cost—Near Term YearsYEAR OF PRODUCTION


180 nm2000 2001 2002

130 nm2003 2004 2005

100 nm

YEAR OF PRODUCTION


180 nm2000 2001

130 nm2002 2003 2004

90nm2005

Affordable Cost per Function ++

DRAM cost/ bit at (packaged microcents) at samples/ introduction (1999)/ (SC. 2.0)

42 — 21 — 11 — 5.3

DRAM cost/ bit at (packaged microcents) at production § (1999)/ (SC. 2.0) 15 — 7.6 — 3.8 — 1.9

Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at introduction §§ (1999)/ (SC. 2.0)

1,735 — 868 — 434 — 217

Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at production §§ (1999)/ (SC. 2.0)

1,050 — 525 — 262 — 131

High-performance MPU (microcents/ transistor) (including on-chip SRAM) at production §§ (1999)/ (SC. 2.0)

245 — 123 — 61 — 31

Cost-Per-Pin (see Table 4) (1999)/ (SC. 2.0) — — — — — — —

Test

Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—maximum (1999)/ (SC. 2.0)

8 7 7 6 6 5 5

Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—minimum (1999)/ (SC. 2.0)

4 3 3 3 3 2 2

Volume tester cost/ pin ($K/ pin) (cost-performance MPU) (1999)/ (SC. 2.0) 8 8 7 7 6 6 5


44

Table 7b Cost—Long Term YearsYEAR OF PRODUCTION


70 nm2011

50 nm2014

35 nm

YEAR OF PRODUCTION

TECHNOLOGY NODE


2008[60 NM]

2011[40 NM]

2014[30 NM]

Affordable Cost per Function ++

DRAM cost/ bit (packaged microcents) at samples/ introduction (1999)/ (SC. 2.0) — 0.66 —

DRAM cost/ bit (packaged microcents) at production § (1999)/ (SC. 2.0) — 0.24 —

Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at introduction §§ (1999)/ (SC. 2.0)

— 27 —

Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at production §§ (1999)/ (SC. 2.0)

— 16 —

High-performance MPU (microcents/ transistor)(including on-chip SRAM) at production §§ (1999)/ (SC. 2.0)

— 3.8 —

Cost-Per-Pin (see Table 4) (1999)/ (SC. 2.0) — — —

Test

Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—maximum (1999)/ (SC. 2.0)

5 5 5

Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—minimum (1999)/ (SC. 2.0)

N/A N/A N/A

Volume tester cost/ pin ($K/ pin) (cost-performance MPU) (1999)/ (SC. 2.0) 4 2 2

++ Affordable packaged unit cost per function based upon Average Selling Prices (ASPs) available from various analystreports less Gross Profit Margins (GPMs); 35% GPM used for commodity DRAMs and 60% GPM used for MPUs;0.5/ two years inTER-generation reduction rate model used; .55/ year inTRA-generation reduction rate model used;DRAM unit volume life-cycle peak occurs when inTRA-generation cost per function is crossed by next generation,typically 7–8 years after introduction; MPU unit volume life-cycle peak occurs typically after four years, when the nextgeneration processor enters its ramp phase (typically two years after introduction).

Documents

ITRS 2000 Update - Taipei, Taiwan, 11/06/00 1 ITRS/ORTC Tables Technology Node, DRAM Chip Size, Logic Chip Size, and key TWG Line-items (1999 refers to