1 Overall Roadmap Technology Characteristics (ORTC) 2012 For ITRS San Francisco Mascone Center Thursday, 7/12/12 1-3:30pm ITRS Public Conference Tracks

1

Overall Roadmap Technology Characteristics(ORTC) 2012

For ITRS San Francisco Mascone Center Thursday, 7/12/12

1-3:30pm ITRS Public Conference Tracks

[Final Rev 6 - includes only Backup I]

1. ITRS Front End of Line Technologies - TechXPOT South, 1-3:30pm• ORTC – Alan Allan

2. ITRS Back End of Line Technologies - TechXPOT North, 1-3:30pm• ORTC – Bob Doering

3. ITRS CrossCut Technologies - Extreme Electronics Stage, South Hall, 2-3:30pm• ORTC – Paolo Gargini

2

ITRS CrossCut Technologies (Extreme Electronics Stage, South Hall, 2:00pm-3:30pm)2:00-2:05 Greeting from the ITRS IRC Chair IRC Session Chair from Korea2:05-2:20 Overall Roadmap Technology Characteristics

(ORTC)IRC member – Paolo Gargini

2:20-2:35 Factory integration Gopal Rao2:35-2:50 Environment, safety, and Health Leo Kenny2:50-3:05 Metrology Alain Diebold3:05-3:20 Yield enhancement (YE) Lothar Pfitzner3:20-3:25 Q and A 3:25-3:30 Closing remarks IRC Session Chair

ITRS Public Conference Thursday, 07/12/12

ITRS Back End of Line Technologies TechXPOT North (1:00pm-3:30pm)1:00-1:05 Greeting from the ITRS IRC Chair IRC Session Chair from Japan-Hidemi Ishiuchi1:05-1:20 Overall Roadmap Technology Characteristics

(ORTC)IRC member – Bob Doering

1:20-1:40 More than Moore IRC member from Europe1:40-1:55 Interconnect Paul Zimmerman1:55-2:10 Assembly and packaging Bill Bottoms2:10-2:25 Test and Test Equipment Roger Barth2:25-2:40 Micro-electro-mechanical systems (MEMS) Michael Gaitan2:40-2:55 RF and analog/mixed-signal technologies

(RFAMS)Jack Pekarik

2:55-3:00 Q and A 3:00-3:15 Closing Remarks IRC Session Chair

ITRS Front End of Line Technologies - TechXPOT South (1:00pm-3:30pm)1:00-1:05 Greeting from the ITRS IRC Chair IRC Session Chair from Taiwan—Carlos Diaz1:05-1:20 Overall Roadmap Technology Characteristics

(ORTC)IRC member – Alan Allan

1:20-1:35 System drivers Juan-antonio Carballo1:35-1:50 Design Andrew Kahng1:50-2:05 Modeling and simulation Juergen Lorenz2:05-2:20 Process integration, devices, and structures

(PIDS)Kwok Ng

2:20-2:35 Lithography Mark Neisser2:35-2:50 Front end processes (FEP) Mike Walden2:50-3:05 Emerging research devices (ERD) Victor Zhirnov3:05-3:20 Emerging research materials (ERM) Michael Garner3:20-3:25 Q and A 3:25-3:30 Closing remarks IRC Session Chair

3

1) Unchanged for 2012: MPU contacted M11) 2-year cycle trend through 2013 [27nm (“14nm” node)]; then 3-year trend to 20262) 60f2 SRAM 6t cell Design Factor3) 175f2 Logic Gate 4t Design Factor2) Unchanged for 2012 Tables: MPU Functions/Chip and Chip Size Models 1) Design TWG Model for Chip Size and Density Model trends – tied to technology

cycle timing trends and cell design factors2) ORTC line item OverHead (OH) area model, includes non-active area3) Unchanged for 2012 Tables: MPU GLpr, GLph – trends “smoothed” by 2011

PIDS modeling4) Unchanged for 2012 Tables: Max Chip Frequency trends (reset in 2011 to

3.6Ghz/2010 plus 4% CAGR trend)5) Unchanged for 2012 Tables: Vdd High Performance, Low operating and standby

line items from 2011 PIDS model track “smoothed” gate length changes

Note: See PIDS tables for 2012 Update to be released at end of 2012 for impact due to acceleration of MugFET and FDSOI “Equivalent Scaling” timing into 2012

2012 Update ITRS ORTC Technology Trend Summary

4

6) Unchanged for 2012 Tables: DRAM contacted M1:1) One-year M1 acceleration2) New for 2012: 4f2 one-year delay to 2014

7) Unchanged for 2012 Tables: Flash Un-contacted Poly:1) 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to

2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm2) and 3bits/cell extended to 2018; 4bits/cell delay to 2022

8) Unchanged for 2012 Tables: DRAM Bits/Chip and Chip Size Model:1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for

smaller chip sizes <30mm2 – 2x/2.5yrs)9) Unchanged for 2012 Tables: Flash Bits/Chip and Chip Size Model:

1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr acceleration; then flat @ 1-2Tbits; keep chip size <160mm2)

2) 3D on-chip bit layers with relaxed half-pitch tradeoffs are included for maximum bits per chip

1) New 2012 Update Survey Emphasis: 2016-2025 layer range from 8/32nm -128/18nm Layers to 16/48nm – 256/24nm Layers (option C in 2011 ORTC Table 2)

2012 Update ITRS ORTC Technology Trend Summary (cont.)

5

10) Unchanged for 2012 Tables: ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, 1) Flash Survey inputs Unchanged for 20122) IC Knowledge (ICK) model contribution extends mask levels range to 2024

2) Possible 2012 Update consideration: update ICK model to 2011 Mask Counts (only YE impacted)

11) Unchanged for 2012 Update: IRC 450mm Timing Graphic Position: 1) Timing Status to be reviewed with G450C in July, 2012)

1) Consortia work underway2) IDM and Foundry Pilot lines: 2013-14; 3) Production: 2015-16 [corrected early target in 2012 Update]2) G450C Consortium continues good progress on 450mm program activities to meet the ITRS Timing

1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development

2) 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers’ schedules for target “1xnm technology” goal

3) 450mm increasing silicon demand is needed from consortium demonstrations to support development

3) Europe Position Unchanged – EEMI450 status was reviewed with IRC in Netherlands Apr’124) 300mm wafer generation in parallel line item header with 450mm; 1) Including Technology upgrade assumptions2) Assuming compatibility of 300mm productivity extensions into the 450mm generation; 5) ITRS-based ICK Strategic Model commercially available and updated to 2011 ITRS, including

300mm and 450mm 2009-2026 Range Scenarios for silicon and equipment demand 12) Unchanged for 2012 Update: More than Moore white paper online at www.itrs.net 1) MtM Workshop completed in Netherlands, in April and reviewed at Summer ITRS meeting

1) Europe workshop included new iNEMI applications presentation (Grace O’Malley/Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al)

2) ITRS MEMS TWG and Chapter cross-roadmap work underway for 2013 iNEMI Roadmap

2012 Update ITRS ORTC Technology Trend Summary (cont.)

6

Technology Pacing Cross-TWG Study Group (CTSG) 2012 work underway to preparation for 2013 ITRS Renewal (kickoff Dec’12), including:

2013 Renewal Preparation ITRS ORTC Technology Trend Summary (cont.)

– IRC Equivalent Scaling Graphic Update• Proposals for timing placement of MuGFET, FDSOI, and III/V Ge Timing; now based on one

IDM or Foundry company, who may lead technology production ramp

– Design and FEP Logic Technology Trends• Monitor and Update MPU and Leading Edge Logic technology trends, including• Ongoing- evaluate alignment of “nodes” with latest M1 industry status• Consider High Performance vs. Low Power transistor type needs• Consider extending 2yr cycle to 2017/14nm (”7nm” node)• Functions/Chip and Chip Size Models tbd; based on final consensus of new proposals• On-Chip Frequency Proposals – Align with PIDS modeling and evaluate/update to industry

trends

– PIDS and FEP Memory Survey Proposal Updates • Monitor and Update DRAM and Flash technology trends

– Litho and FEP (and PIDS and Design) Survey for CD Variability and Control• Monitor and Update Litho and Etch Gpr/Gph Ratio for CD control trends

– A&P/Design Power (Thermal) Model• Develop proposals for Power Dissipation "hot spot" model rather than chip area basis

– PIDS/Design Max On-chip Frequency vs Intrinsic Modeling• Targeted for 8% (vs. 13%) CAGR (1/CV/I) intrinsic transistor performance (to align with 2011

ITRS 4% Design Frequency trend)• Consider Intrinsic Transistor and Ring Oscillator model Changes • Including MASTAR static modeling near-term and TCAD dynamic long-term modeling• Including “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling

– YE Defect Density Modeling• Update ORTC Defect Density model work to latest Litho Mask Count Model – still seeking

defect modeling resources support

7

More than Moore: DiversificationM

ore

Mo

ore

: M

inia

turi

zati

on

Combining SoC and SiP: Higher Value SystemsBa

se

lin

e C

MO

S:

CP

U,

Me

mo

ry,

Lo

gic

BiochipsSensors

Actuators[e.g. MEMS]

HVPower

Analog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm

16 nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Beyond CMOS

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Source: 2011 ITRS - Exec. Summary Fig. 4

Figure 4 The Concept of Moore’s Law and More

Work in Progress - Do Not Publish8

Months

0-24

Alpha

Tool

12 24-12

Development Production

Beta

Tool

Pre-Production

Tool

First

Conf.

Papers

First 1-2 Companies

Reaching

Combined Production 2

20

200

2K

20K

200K

AdditionalLead-time:ERD/ERM

Research andPIDS Transfer

Volum

e (Wafers/M

onth)

Source: 2009 ITRS - Exec. Summary Fig. 2a

Figure 2a- (within an established wafer generation*)- *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also- Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production “Ramp Curves”

Production Ramp-up Model and Technology/Cycle Timing

2012 UpdateNote:Fewer leadingIDM Companies Requires Adaption of DefinitionTo allow oneIDM CompanyOr a Foundry RepresentingMany Fabless CompaniesTo Lead aTechnology Production Ramp Timing

Production

9

Months

Alpha

Tool


Beta

Tool

Pre-

Production

Tool

Vol

ume

(Waf

ers/

Mon

th)

2

20

200

2K

20K

200KResearch

-72 0 24-48 -24-96

Transfer to PIDS/FEP(96-72moLeadtime)

First Tech. Conf.

Device PapersUp to ~12yrs

Prior to Product

20192017201520132011 2021Hi-Channel

Example:

1st 1-2 Co’s

Reach

Product

First Tech. Conf.

Circuits PapersUp to ~ 5yrs

Prior to Product

Hi-Channel Proposal - for 2013 ITRS work

Source: 2011 ITRS - Exec. Summary Fig. 2b; plus:

Figure 2b A Typical Technology Production “Ramp” Curve for ERD/ERM Research and PIDS Transfer timing - including an example for III/V Hi-Mobility Channel Technology Timing Scenario

- Acceleration to 2015 Scenario for the 2012 Update work

[http://www.eetimes.com/electronics-news/4087596/Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option ]

Production

10

2012 ITRS Update* 450mm Production Ramp-up Model[ 2011 ITRS Executive Summary Fig. 6 - A Typical Wafer Generation Pilot Line and Production “Ramp” Curve]

Source: 2011 ITRS - Executive Summary Fig. 6

*Note: the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 Update Roadmap guidance; based on SEMATECH guidance

Vo

lum

e

Years

Alpha

Tool

Beta

Tool

Silicon is supporting development using partially-patterned and processed test wafers ------ IDM & Foundry ------

Pilot Lines

Manufacturing

Demonstrations focus on 1xnm M1 half-pitch capable tools


Increasing450mm Silicon Demand

From DemonstrationsBeta

Tool

Pre-Production

Tool

<---------------------------------------- Consortium -------------------------------------------Demonstration

2010 2011 2012 2015 20162013 2014

Production

Backup I – Final Rev 51. First (1-10) foils – Public ORTC for Thursday, 7/12 in S.Francisco;

Including Backup I (11-24) Foils for the Public Conference

2. (12) ORTC Fig. 3 Memory Trends

3. (13) ORTC Fig. 4 MPU Trends

4. (14) ORTC Fig. 4 MPU Trends with Memory Trends Overlay

5. (15) ORTC Fig. 4 MPU Trends with Memory Trends and Equivalent Scaling Trends Overlay

6. (16) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Leading Company PIDS 2012 ITRS Timing

7. (17) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Fast Follower and 2013 ITRS Timing

8. (18) ORTC Fig. 6 Function Sizes in 2012 ITRS Timing

9. (19) ORTC Fig. 7 Memory Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing

10. (20) ORTC Fig. 8 MPU Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing

11. (21) ORTC Table 1 plus 2013 ITRS considerations

12. (22) SICAS Capacity analysis update

13. (23,24) DRAM and Flash Functions/Chip 2009 ITRS vs. 2011 ITRS (2 foils)

11

12

2011 ITRS Figure 3 2012 update; add 3D Flash layer-range emphasis – ORTC Table 1 Graphical Trends – Memory Half Pitch

[With 2011 Flash 3D Scenario Overlay]

Source: 2011 ITRS - Executive Summary Fig 3

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production

2011 ITRS - Technology Trends

2011 ITRS Flash ½ Pitch (nm) (un-contacted Poly) -[2-yr cycle to 2009; then 8-yr cycle to 2020; then 3-yr cycle to 2022/8nm; then flat]

2011 ITRS DRAM ½ Pitch (nm) (Contacted M1) -[2.5-yr cycle to 2008; 45nm pull-in to 2009; then 3-yr cycle to 2026]

2011 ITRS: 2011-2026

3D - 8 layers

3D - 128 layers

PIDS 3DFlash :

Looser Polyhalf-pitch

2016-18/32;Then

2019-21/28nmThen

2022-25/24nmThen

2025-26/18nm ~5.5-yr Cycle

Long-Term ’19-’26

16nm

3D -16layers/48nm

3D -256layers/24nm4-yr cycle

5.5-yr cycle

2012 Update: DRAM: 4f2/’14;

Flash: 3D on-chip2016/16 Layers

@ 48nm – option Cemphasis

13

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production


2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]

2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]

2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]

2011 ITRS: 2011-2026


16nm

2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length


2013 CTSGWORK; Update

Proposals tobe considered

14

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production





2011 ITRS: 2011-2026


16nm



Flash Trends

DRAM Trends

[ MPUvs. Memory

Half-Pitches ]

15

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production





2011 ITRS: 2011-2026


16nm


Flash Trends

DRAM Trends

2012 ITRS Update Unchanged: “22nm” (ITRS 2011 Planar M1=38nm ; GL=24nm);3-year Logic M1 Technology Pace after 2013

2-yearM1 pace

extension to

2017 ; then 3yrs

again

2013 ITRS Work Consider: “7nm” pull-in to 2017 (from ITRS 2011 Planar M1=14nm/’19)?; III/V Ge pull-in to 2015?; 2019 ITRS GLph = 11.7nm unchanged?;

Logic and Flash (3yr cycle) both drive Lithography after 2017; Logic M1 after 2022?

MuG-FET

FDSOI

[ MPUIncluding PIDS

MugFET and FDSOI Acceleration]


Hi-u,(tbd)

[ also includingMemory

Half-PitchesCartoon trends

For comparison ]

2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and FDSOI (2012) ITRS acceleration

Metal

High kGate-stack material

2009 2012 2015 2018 2021

Bulk

FDSOI

Multi-gate(on bulk or SOI)Structure

(electrostatic control)

Channelmaterial

Metal

High k

2nd generation

Si + Stress

S D

High-µ InGaAs; Ge

S D

PDSOI

Metal

High k

nth generation

PossibleDelay

Possible Pull -in

16

68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :

2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm

MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16/14nm” “11/10nm” “8/7nm”

2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm

2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm

45nm 32nm 11nm2011 ITRS Flash Poly : 54nm2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021

PIDS Acceleration - for 2012 ITRS Update

22-248nm

20248nm

22nm 15nm

11nm


2012 Update Note:Leadership company First Manu-facturingcould set more Aggressive first production target, since “fast followers” may trail 1-3 years

[ PIDS/FEP/DesignHP/LOP/LSTP

Sub-Team Transistor

Modeling Work Underway for2013 ITRS ]

450mm1st Production


2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and FDSOI (2012) and III/V Ge (2013) ITRS acceleration

Metal

High kGate-stack material

2009 2012 2015 2018 2021

Bulk

FDSOI

Multi-gate(on bulk or SOI)Structure

(electrostatic control)

Channelmaterial

Metal

High k

2nd generation

Si + Stress

S D

High-µ InGaAs; Ge

S D

PDSOI

Metal

High k

nth generation

PossibleDelay

Possible Pull -in

17

68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :

2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm

MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16nm/14nm” “11/10nm” “8/7nm”

2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm

2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm

45nm 32nm 11nm2011 ITRS Flash Poly : 54nm2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021

PIDS Acceleration - for 2012 ITRS Update

22-248nm

20248nm

22nm 15nm

11nm

Proposal - for 2013 ITRS prep.

2012MPU =DRAM

2015 onM1 2-yrCycle?

2013-14 MPU <DRAM

2017 onM1 2-yrCycle?

FDSOI MugFET pull-in to “14nm”/2014?

Multiple companies with Bulk MugFET pull-in to “14nm”/2014?

2012 UpdateNote:Leadership company First Manu-facturingcould set more Aggressive first production target, since “fast followers” may trail 1-3 years

18

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1995 2000 2005 2010 2015 2020 2025 2030

Sq

uar

e M

illi

met

ers

Year of Production

2011 ITRS - Function Size

2009 DRAM Cell area per bit (1 bits/cell) (um2)

2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)

2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)



2011 SRAM Cell (6-transistor) Area (um2)

2011 Logic Gate (4-transistor) Area (um2)


2011 ITRS: 2011-2026

PIDS NAND Flash Multi-Layer 3D Model

vs. “Slower” Poly half-pitch Dimensional Reduction Rate affects 3D Bit size & density (not graphed)

2011 ORTC Figure 6Product Function

Size Trends Unchanged; except 4f2 moved to 2014 [transistor + capacitor]


Updated06/24/12

FOR 2012 CTSGWORKMPU/ASIC

AlignmentDesign TWG

Actual SRAM [60f2]& Logic Gate [175f2]

DRAM4f2

AddedWAS:Begin in

2011IS: DelayedTo 2013 ‘14

Flash [4f2]1) 2-yr CycleExtended to 2010;2) 3 bits/cell added2009-2011[and extended to 2026 in the 2011 ITRS];3) 4 bits/cell movedfrom 2012 [to 2021 in the 2011 ITRS]

3D - 8 layers

3D - 128 layers

3D -16layers/48nm?

3D -256layers/24nm?

4-yr cycle?

5.5-yr cycle

Flash Impact of:

Vs:

0.01

0.10

1.00

10.00

100.00

1000.00

10000.00

1995 2000 2005 2010 2015 2020 2025 2030

Gig

abit

s (1

e9)

and

Sq

uar

e M

illi

met

ers

Year of Production

2009 ITRS - Functions/chip and Chip Size

2011 ITRS DRAM Functions per chip (Gbits)

2011 ITRS Flash (Gbits) SLC [2-year cycle]

2011 ITRS Functions per chip (Gbits) MLC (2 bits/cell)

2011 ITRS Functions per chip (Gbits) MLC (3 bits/cell)

2011 Functions per chip (Gbits) MLC (4 bits/cell)

2011 Flash Chip size at production (mm2)

2011 DRAM Chip size at production (mm2)

Flash"Hwang's

Law"~ 2x/1yr

Flash~ 2x/3yrs

Flash MLCExceeds1Tera-bit

Average "Moore's Law" = 2x/2yrs

<160mm2(18 x 9)

<30mm2(8 x 4)

DRAM~ 2x/2.5yrs

Flash~ 2x/1.25yrs


2011 ITRS: 2011-2026

2011

19

Figure 7 2011 ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged for the 2012 Update]


4Tbits Possible with PIDS NAND Flash Multi-Layer

3D Model Scenario Option3D - 128 layers/ ‘25

2025/32nm/3bits/cell4Tbits =128x33Gbits

2025/18nm/3bits/cell13Tbits =128x99Gbits

DRAM4f2

AddedWAS:Begin in

2013IS: DelayedTo 2013 ‘14

20

10

100

1000

10000

100000

1000000

10000000

1995 2000 2005 2010 2015 2020 2025 2030

Mil

lio

n T

ran

sist

ors

(1e

6) a

nd

Sq

uar

e M

illi

met

ers

Year of Production

2011 ITRS - Functions/chip and Chip Size

2011 ITRS Cost-Performance MPU Functions per chip at production (Mtransistorst)

2011 ITRS High-Performance MPU Functions per chip at production (Mtransistors)

2011 Cost-Performance MPU Chip size at production (mm2)

2011 High-Performance MPU Chip size at production (mm2)

<260mm2

<140mm2

MPU= 2x/3yrsMPU

= 2x/2yrs

Average "Moore's Law"

= 2x/2yrs


2011 ITRS: 2011-2026

2011ITRS:

Unchanged, but Extend ed

Transistors/chip& Chip Size

Modelsto 2026

On 3-yearCycle

MPU/hpASICM1 Technology Cycle and MPUTransistors/chip

areOn 3-year

Cycle after 2013

vs.Average

2-yearHistorical

Moore’s Law

“22nm”/(38nm M1)MPU Model Generations

Figure 8 2011 ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged for 2012 Update]


Work in Progress - Do Not Publish21

Year of Production 2019 2020 2021 2022 2023 2024 2025 2026Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 10.9 10.0 8.9 8.0 8.0 8.0 8.0 8.0DRAM ½ Pitch (nm) (contacted)[1,2] 14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0

MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 6.79 5.87

MPU High-Performance Physical Gate Length (GLph) (nm)[1] 11.7 10.6 9.7 8.9 8.1 7.4 6.6 5.9

ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 6.8 5.8ASIC/Low Operating Power Physical Gate Length (nm)[1] 11.9 10.8 9.8 8.9 8.1 7.3 6.5 5.8ASIC/Low Standby Power Physical Gate Length (nm)[1] 12.7 11.4 10.2 9.2 8.2 7.4 6.6 5.9MPU High-Performance Etch Ratio GLpr/GLph [1] 1.2013 1.1725 1.1444 1.1169 1.0901 1.0640 1.0315 1.0000MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.1766 1.1558 1.1352 1.1151 1.0953 1.0759 1.0372 1.0000

Long-term Years

Table ORTC-1 ITRS Technology Trend Targets

Year of Production 2011 2012 2013 2014 2015 2016 2017 2018Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 22 20 18 17 15 14.2 13.0 11.9DRAM ½ Pitch (nm) (contacted)[1,2] 36 32 28 25 23 20.0 17.9 15.9MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 38 32 27 24 21 18.9 16.9 15.0

MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 35 31 28 25 22 19.8 17.7 15.7

MPU High-Performance Physical Gate Length (GLph) (nm)[1] 24 22 20 18 17 15.3 14.0 12.8

ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 41 35 31 25 22 19.8 17.7 15.7ASIC/Low Operating Power Physical Gate Length (nm)[1] 26 24 21 19.4 17.6 16.0 14.5 13.1ASIC/Low Standby Power Physical Gate Length (nm)[1] 30 27 24 22 20 17.5 15.7 14.1MPU High-Performance Etch Ratio GLpr/GLph [1] 1.4589 1.4239 1.3898 1.3564 1.3239 1.2921 1.2611 1.2309MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.5599 1.4972 1.4706 1.2869 1.2640 1.2416 1.2196 1.1979

Near-term Years

2011 ORTC Table 1 [Unchanged for 2012 Update; tbd 2013 ITRS Renewal]

450mm Production Target : 2015-2016

‘11 ITRS EUV Intro:DRAM&Flash: 2013MPU: 2015

MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0”

2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021 2023 2025

2-year “Node” Cycle (@ 0.7071/2yrs = 0.8409/yr

2011 ITRS M1 2yr cyc(nm): 76 65 54 45 38 32 27 22.5 19 16 13.4 11.25 9.5 8.0 6.7 5.6 4.73 4.0 3.34

2011 ITRS M1 3yr cyc (nm): 76 65 54 45 38 32 26.8 23.8 21.2 18.9 16 .9 15.0 13.4 11.9 10.6 9.5 8.43 7.5 6.69 ??

*Note: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of 1Q11. The detailed data are available to the public online at the SIA website, www.sia-online.org, and data is located at http://www.sia-online.org/industry-statistics/semiconductor-capacity-utilization-sicas-reports/

22

* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 1Q data for 2011. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.

2.5-Year DRAM Cycle ; 2-year Cycle Flash and MPU

2010 2013

2-Year DRAM

Cycle

3-Year Cycle

Fea

ture

Siz

e (H

alf P

itch)

(m

)

Year

>0.7m

0.7-0.4m

0.4-0.3m

0.3- 0.2m

0.2- 0.16m

0.16-0.12m

0.08-0.06m

0.12-0.08m

0.2- 0.12m

0.4-0.2m

<0.06m

W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS

0.01

0.1

1

10

200620052004

W.P.C.

2000

W.P.C.

2001

W.P.C.

2002

W.P.C.

2003

W.P.C. W.P.C.

2007 2008 2009

W.P.C. W.P.C. W.P.C. W.P.C. W.P.C.

2010 2011

W.P.C.

1998 2015

= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09/11 ITRS DRAM Contacted M1 Half-Pitch Target = 2009/11 ITRS Flash Un-contacted Poly Half Pitch Target = 2009/11 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target

4-Year Cycle for Flash after2010 Flash pull-in;

MPU 3-yr cycle after 20133-yr cycle for DRAM after pull-in

Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution

Source: 2011 ITRS - Exec. Summary Fig. 3

Work in Progress – Do Not Publish!23

Flash (NAND) Product Size Generations

2009 ITRS Renewal:

PIDS Flash Size: 2007 2011 2016 2020

2007 ??? ??? ??? ???

4x/4-5yrs WAS'09 16G 64G 256G 1T

Interim Generations: 2009 2014 2018 2022

??? 2007 ??? ??? ??? ???

4x/4-5yrs WAS'09 32G 128G 512G 2T

5yrs 4yrs 4yrs

2011 ITRS Renewal (PIDS 2010 Update Proposal):

PIDS Flash Size: 2007 2010 2011 2014 2016 2019 2020

4x/4-5yrs WAS'09 16G 64G 256G 1T

4x/4-5yrs IS'11 64G 256G 1T

Interim Generations: 2008 2009 2012 2014 2017 2018 2021 2022 2026

4x/4-5yrs WAS'09 32G 128G 512G 2T n/a

4x/4-5yrs IS'11 32G 128G 512G 2T 2T

4yrs 5yrs 4yrs ??yrs

Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/2022-26

Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G

128Gbit chip will be available in 2012.

NAND Cell Array Efficiency unchanged from 56% in ITRS 2010

Work in Progress – Do Not Publish!24

DRAM Product Size Generations

2009/10 ITRS Renewal:

PIDS DRAM Size: 2010 2011 2016 2017 2022 2023

4x/6yrs 2007 4G 16G 64G

WAS'09/10 4G 16G 64G

Interim Generations: 2008 2013 2014 2019 2020

4x/5-6yrs 2007 2G 8G 32G

4x/6yrs WAS'09/10 2G 8G 32G

5yrs 6yrs

2011 ITRS Renewal (PIDS 2010 Update Proposal):

PIDS DRAM Size: 2011 2017 2018 2023 2025

4x/6yrs WAS'09/10 4G 16G 64G n/a

4x/7yrs IS'11 4G 16G 64G

Interim Generations: 2008 2014 2020

4x/6yrs WAS'09/10 2G 8G 32G

4x/6yrs IS'11 2G 8G 32G

6yrs 6yrs 7yrs?

DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026

DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025

DRAM Cell size factor: 4F2 cell will be available in 2013. Delay 2years from ITRS2009/10

DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010

Documents

1 Overall Roadmap Technology Characteristics (ORTC) 2012 For ITRS San Francisco Mascone Center Thursday, 7/12/12 1-3:30pm ITRS Public Conference Tracks