Spiking-Timing-Dependent Learning in Memristive Device

Yi KaijunDSI

Jan 12 2011

Background

• Current CMOS scaling problem: tunneling effect, defects, faults, failures, variability, drift, etc.

• Adaptive, neuromorphic circuits and system (intelligent, low power consumption, error tolerance, etc.)

Neuromorphic Device

• Very-large-scale integration (VLSI) systems containing electronic analog circuits that mimic neuro-biological architectures present in the nervous system.

• Both analog, digital or mixed-mode analog/digital VLSI systems that implement models of neural systems (for perception, motor control, sensory processing, learning, etc.) as well as software algorithms.

Hebbian Learning

• If two neurons on either side of synapse (connection) are activated simultaneously, then the strength of that synapse is selectively increased.

• If two neurons on either side of a synapse are activated asynchronously, then that synapse is selectively weakened or eliminated.

Spiking Timing Dependence Spiking

• Spike-timing-dependent plasticity (STDP) is a biological process that adjusts the strength of connections between neurons in the brain. The process adjusts the connection strengths based on the relative timing of a particular neuron's output and input action potentials (or spikes).

• Timing-based learning law

Spiking Timing Dependence Spiking

STDP with CMOS

J. V. Arthur and K. Boahen, “Learning in Silicon : Timing is Everything”, NIPS, 2006

Memristor in a nutshell

8

RHIGH RLOW

A two-terminal device Resistance state (RHIGH/RLOW)

depends on the voltage applied across

Resistance state remains after the removal of the electrical stimulus

Reversible switching of resistance states

Memristor – Device realization

Resistance change (∆R) as a result of morphological change of materials– Can be initiated by the electrode

or within the insulator– Global vs. local– Semi-permanent, i.e. R remains

after removal of electrical bias– Reversible

9

metal electrode resistive layerconductive layer conductive filament

Memristor – Two basic operation schemes1

Unipolar:– Switching depends on amplitude of

the applied voltage but not the polarity

– VSET always higher than VRESET

Bipolar– Directional switching depending on

the polarity of the applied voltage– VSET and VRESET at opposite polarities

101Waser, R. et al., Adv. Mater., 21, 2632 (2009). 2Waser, R. , Microelectron. Eng., 86, 1925 (2009).

Unipolar and bipolar switching.2 CC denotes the compliance current, often needed to limit the ON current.

STDP with Memristor

Neurons and Synapse

CMOS

Memristor

STDP Device

Neuromorphic Network

Key Ideas

• Define two synaptic state variables for pre- and post-synaptic neurons

• To separate computational communication from learning by time-division multiplexing (TDM) of pulse-width modulation (PWM) signal through synapses

Two State Parameters

• Long Term Potentiation (LTP): a long-lasting enhancement in signal transmission between two neurons that results from stimulating them synchronously.

• Long Term Depression (LTD): an activity-dependent reduction in the efficacy of neuronal synapses lasting hours or longer.

TDM and PWM

• TDM: a type of digital or (rarely) analog multiplexing in which two or more signals or bit streams are transferred apparently simultaneously as sub-channels in one communication channel, but are physically taking turns on the channel.

• PWM: A technique to provide logic “1” and logic “0” for a controlled period of time. The information is encoded as pulse duration.

Time-division Multiplexing of Signals through Synapses

Signal Definition

• COMM (Time Slot 0): communication of spikes from pre to post in order to compute inner products or matrix products.

• LTP+/- (Time Slot 1/2): communicate LTP timing information from Pre to post with PWM encoding.

• LTD+/- (Time Slot 3/4): communicate LTD timing information from post to pre with PWM.

Pulse-width Modulation within a timeslot

Transmission of LTD and LTP Timing Curves Through Synapses

Post Spiking After Pre Spiking Induces LTP

Pre Spiking After Spiking Induces LTD

Block Diagram of A Neuron

A Memristor Nanodevice at HP

Advantages

• Better control over power consumption• Fewer constraints on memristor used for

synapses• Greater freedom in learning algorithm• Greater control over precise timing control for

STDP learning• Adaptable for other learning law• Better circuit diversity

Drawbacks

• Neuron element is too complicated to be integrated in large scales.

• This is only the concept, more realistic protocols and concrete devices should be developed.

• No demonstration is provided.