Memory Testing

  • View
    17

  • Download
    0

Embed Size (px)

DESCRIPTION

testing of memory

Text of Memory Testing

  • Testing Semiconductor MemoriesLab for Reliable ComputingDept. Electrical EngineeringNational Tsing Hua UniversityCheng-Wen Wu

    Cheng-Wen Wu, NTHU

  • OutlineIntroductionRAM functional fault models and test algorithmsRAM fault-coverage analysisCocktail-March for testing word-oriented memoriesTesting multi-port RAMsTesting CAMsTesting flash memories

    Cheng-Wen Wu, NTHU

  • IntroductionMemory testing is a more and more important issueRAMs are key components for electronic systemsMemories represent about 30% of the semiconductor marketEmbedded memories are dominating the chip yieldMemory testing is more and more difficultGrowing density, capacity, and speedEmerging new architectures and technologiesEmbedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc.Cost drives the need for more efficient test methodologiesIFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.Test automation is requiredFailure analysis, fault simulation, ATG, and diagnosticsBIST/BIRA/BISR generation

    Cheng-Wen Wu, NTHU

  • Typical RAM Production FlowWafer

    Cheng-Wen Wu, NTHU

  • Scope of RAM TestingParametric Test: DC & ACReliability ScreeningLong-cycle testingBurn-in: static & dynamic BIFunctional TestDevice characterizationFailure analysisFault modelingSimple but effective (accurate & realistic?)Test algorithm generationSmall number of test patterns (data backgrounds)High fault coverageShort test time

    Cheng-Wen Wu, NTHU

  • RAM ModelsBehavior LevelVerilog/VHDLFunction LevelVerilog/VHDL/Block diagramNormally not synthesizableCircuit LevelSpice/SchematicLayout LevelGDS-II/GeometryWho should provide the model?

    Cheng-Wen Wu, NTHU

  • Memory Function Model Example

    Cheng-Wen Wu, NTHU

  • RAM Fault Models (Static)Address-Decoder Fault (AF)No cell accessed by certain addressMultiple cells accessed by certain addressCertain cell not accessed by any addressCertain cell accessed by multiple addressesStuck-At Fault (SAF)Cell (line) SA0 or SA1Transition Fault (TF)Cell fails to transit from 0 to 1 or 1 to 0

    Cheng-Wen Wu, NTHU

  • RAM Fault Models (Static)Bridging Fault (BF)Short between cellsAND type or OR type Stuck-Open Fault (SOF)Cell not accessible due to broken lineNeighborhood Pattern Sensitive Fault (NPSF)Active (Dynamic) NPSFPassive NPSFStatic NPSF

    Cheng-Wen Wu, NTHU

    N

    W

    BC

    E

    S

  • RAM Fault Models (Static)Coupling Fault (CF)State Coupling Fault (CFst)Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given stateInversion Coupling Fault (CFin)Transition in coupling cell complements (inverts) coupled cellIdempotent Coupling Fault (CFid)Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0

    Cheng-Wen Wu, NTHU

  • RAM Fault Models (Dynamic)Recovery Fault (RF)Sense Amplifier Recovery Fault (SARF)Sense amp saturation after reading/writing long run of 0 or 1Write Recovery Fault (WRF)Write followed by reading/writing at different location resulting in reading/writing at same locationWrite-after-write recovery faultRead-after-write recovery faultResults in functional faults---detected at high speed (e.g., GALROW/GALCOL)Disturb Fault (DF)Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same cell)

    Cheng-Wen Wu, NTHU

  • RAM Fault Models (Dynamic)Data Retention Fault (DRF)DRAMRefresh FaultRefresh-Line Stuck-At FaultLeakage FaultSleeping Sickness---loose data in less than specified hold time (typically tens of ms)SRAMLeakage FaultStatic Data Losses---defective pull-upCheckerboard pattern triggers max leakageBIST good for sync with refresh mechanism

    Cheng-Wen Wu, NTHU

  • Test Time Complexity (100MHz)

    Cheng-Wen Wu, NTHU

    Size

    N

    10N

    NlogN

    N1.5

    N2

    1M

    0.01s

    0.1s

    0.2s

    11s

    3h

    16M

    0.16s

    1.6s

    3.9s

    11m

    33d

    64M

    0.66s

    6.6s

    17s

    1.5h

    1.43y

    256M

    2.62s

    26s

    1.23m

    12h

    23y

    1G

    10.5s

    1.8m

    5.3m

    4d

    366y

    4G

    42s

    7m

    22.4m

    32d

    57c

    16G

    2.8m

    28m

    1.6h

    255d

    915c

  • RAM Test AlgorithmA test algorithm (or simply test) is a finite sequence of test elementsA test element contains a number of memory operations (access commands)Data pattern (background) specified for the Read operationAddress (sequence) specified for the Read and Write operationsA march test algorithm is a finite sequence of march elementsA march element is specified by an address order and a number of Read/Write operations

    Cheng-Wen Wu, NTHU

  • Classical Test AlgorithmsZero-One Algorithm [Breuer & Friedman 1976]Also known as MSCANFor SAFSolid background (pattern)Complexity is 4N

    Cheng-Wen Wu, NTHU

  • Classical Test AlgorithmsCheckerboard AlgorithmZero-one algorithm with checkerboard patternComplexity is 4NFor SAF and DRF

    Cheng-Wen Wu, NTHU

    1

    0

    1

    0

    1

    0

    1

    0

    1

  • Classical Test AlgorithmsGalloping Pattern (GALPAT)Complexity is 4N**2---only for characterizationAll AFs,TFs, CFs, and SAFs are located1. Write background 0;2. For BC = 0 to N-1 { Complement BC; For OC = 0 to N-1, OC != BC; { Read BC; Read OC; } Complement BC; }3. Write background 1;4. Repeat Step 2;

    Cheng-Wen Wu, NTHU

    BC

  • Classical Test AlgorithmsSliding (Galloping) Row/Column/DiagonalBased on GALPAT, but instead of a bit, a complete row, column, or diagonal is shiftedComplexity is 4N**1.5

    Cheng-Wen Wu, NTHU

    1

    1

    1

    1

    1

  • Classical Test AlgorithmsButterfly AlgorithmComplexity is 5NlogN1. Write background 0;2. For BC = 0 to N-1 { Complement BC; dist = 1; While dist
  • Classical Test AlgorithmsMoving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976]For functional and AC parametric testFunctional (13N): for AF, SAF, TF, and most CFParametric (12NlogN): for Read access time2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bitRepeat T2~T5 for each address bitGALPAT---all 2-address sequences

    Cheng-Wen Wu, NTHU

  • Classical Test AlgorithmsSurround Disturb AlgorithmExamine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; }2. Repeat Step 1 with complementary data;

    Cheng-Wen Wu, NTHU

  • Classical Test AlgorithmsZero-one and checkerboard algorithms do not have sufficient coverageOther algorithms are too time-consuming for large RAMTest time is the key factor of test costComplexity ranges from N2 to NlogNNeed linear-time test algorithms with small constantsMarch test algorithms

    Cheng-Wen Wu, NTHU

  • March TestsZero-One (MSCAN)Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979]OR-type address decoder faultAND-type address decoder faultMATS+ [Abadir & Reghbati 1983]For both OR- & AND-type AFs and SAF

    Cheng-Wen Wu, NTHU

  • March TestsMarching 1/0 [Breuer & Friedman 1976]For AF, SAF, and TFMATS++ [Goor 1991]Also for AF, SAF, and TFComplete and irredundant

    Cheng-Wen Wu, NTHU

  • March TestsMarch XFor AF, SAF, TF, & CFinMarch C [Marinescu 1982]For AF, SAF, TF, & all CFs---redundantMarch C- [Goor 1991]Also for AF, SAF, TF, & all CFs---irredundant

    Cheng-Wen Wu, NTHU

  • March TestsLimitationsSequential faults in address decodersRFNPSF(9N-2) for 2-CF [Marinescu 1982](2NlogN+11N) for 3-CF [Cockburn 1994]SolutionsAddress sequence variationHoppingPseudorandom

    Cheng-Wen Wu, NTHU

  • Coverage of March Tests Extended March C- (11N) has a 100% coverage of SOF

    Cheng-Wen Wu, NTHU

    MATS++

    March X

    March Y

    March C-

    SAF

    1

    1

    1

    1

    TF

    1

    1

    1

    1

    AF

    1

    1

    1

    1

    SOF

    1

    .002

    1

    .002

    CFin

    .75

    1

    1

    1

    CFid

    .375

    .5

    .5

    1

    CFst

    .5

    .625

    .625

    1

  • Testing Word-Oriented RAMBackground bit is replaced by background wordMATS++:Conventional method is to use logm+1 different backgrounds for m-bit wordsm=8: 00000000, 01010101, 00110011, and 00001111Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N

    Cheng-Wen Wu, NTHU

  • Cocktail-March AlgorithmsMotivation:Repeating the same algorithm for all logm+1 backgrounds has redundancyDifferent algorithm targets different faultsApproach:Use multiple backgrounds in a single algorithm runMerge and forge different algorithms and backgrounds into a single algorithmGood for word-oriented memories

    Cheng-Wen Wu, NTHU

  • March-CWAlgorithm:March C- for solid background (0000)Then a 5N March for each of other standard backgrounds (0101, 0011):Result:Complexity is (10+5logW)N, where W is word length and N is word countTest time is reduced by 39% if W=4, as compared with extended March C-Improvement increases as W increases

    Cheng-Wen Wu, NTHU

  • Comparison (Full Coverage)

    Cheng-Wen Wu, NTHU

  • Testing NPSFNPSF test

Recommended

View more >