Memory Testing Algorithm

5/22/2018 Memory Testing Algorithm

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Memory Fault Models and

Testing Algorithms

Hardik Doshi


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Memory Functional Faults

Stuck at Faults (SAF)

Transition Faults (TF)

Coupling Faults (CF) Neighborhood Pattern Sensitive Faults (NPSF)

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Stuck at Faults (SAF)

The logic value of a cell or line is stuck at always 0 or 1.

Stuck at 0 (SA0) If stuck at always is 0 logic value.

Stuck at 1 (SA1) if stuck at always is 1 logic value.

From each cell, a 0 and 1 must be read.

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Stuck at Fault

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Transition Fault (TF)

A special case of SAF is Transition Fault (TF).

A cell or line which fails to undergo a from 0 to 1 when it is

written is said to contain an up transition fault .

A cell or line which fails to undergo a from 1 to 0 when it is

written is said to contain an down transition fault.

Each cell must undergo a transition and a transition, andbe read after each transition before any further transitions.

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Transition Fault (TF)

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transition fault


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Coupling Faults (CF)

Write Operation which transits or in one cellchanges the contents of a second cell.

Ci coupled to Cj means that an transition incell j causes or transition in cell i.

Inversion Coupling Faults (Cfin)

Idempotent Coupling Faults (Cfid)

Bridging and State Coupling Faults

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State Transition Diagram of Two Good

Cells, iand j

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Sij represent the state of cell i and j.


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Inversion & Idempotent Coupling Faults

An or transition in one cell inverts thecontents of the second cell is called inversion

coupling cell (Cfin).

Ci is coupled to Cj means transition inCj inverts the content of the Ci.

Ci Cj coupled to Cj means transition inCj inverts the content of the Ci.

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Inversion Coupling Cfin

Sij represent the state of cell i and j

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Coupling Fault (CF)

A CF is called Asymmetric fault when the coupled cell only undergoes from0 to 1 or a 1 to 0 transition due to fault.

A CF is called Symmetric fault when the coupled cell undergo both from 0 to1 and from 1 to 0 due to fault.

The Cfid is asymmetric fault and the Cfin is a symmetric fault.

A CF is called one way CF if the CF is sensitized only upon one transition ofthe coupling cell.

A CF is called two way CF if the CF is sensitized upon either transition of thecoupling cell.

Single Cfid is a one way, asymmetric CF.

Combination of the Cfids and is a two way asymmetric CF. 11


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Idempotent Coupling Fault(Cifd)

An or transition in one cell force thecontents of the second cell to a particular

value 0 or 1 is called inversion coupling cell

(Cfid).

Ci is coupled to cj means transition in cell j would make 0 in cell i.

Ci Cj , Ci Cj, Ci Cj12


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Idempotent Coupling Fault Cfid

Sij represent the state of cell i and j

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Neighborhood Pattern Sensitive Faults(NPSF)

The content of a cell is influenced by the contents of all other cells in thememory. The content consists of a pattern of 0s and 1s, or changes inthese contents.

Its also considered as K-coupling fault.

Active NPSF

Passive NPSF

Static NPSF

Memory Array

b : Base cell

d : Deleted Neighborhood cell

b+d : Neighborhood

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d

d b d

d


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Active NPSF

The base cell changes its contents due to a change in the

deleted neighborhood pattern.

This transition is in only one deleted neighbor cell whileother neighbor and bas cell contain a certain pattern.

Example Ci,j

where Ci,j is location of base cell.

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Passive & Static NPSF (PNPSF & SNPSF)

The content of the base cell cant be changed due tocertain deleted neighborhood pattern.(PNPSF)

The content of the base cell is forced to certain state dueto certain deleted neighborhood pattern.(SNPSF)

Ci,j < 0,0,1,1; /x >

Ci,j < 0,1,0,0; -/0 >

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Address Decoder Faults (AF)

Fault 1 Ax

Fault 2 Cx

Fault 3 Cx

Ay Cy

Fault 4 AxAy Cx

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Address Decoder Fault Combinations(AF)

Fault A:- (1+2) Ax Cx

Fault B:- (1+3) Ax Cx

Ay Ay Fault C:- (2+4) Ax Cx

Ay Cy

Fault D:- (3+4) Ax Cx

Ay Cy

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Condition for detection AF

The in a march element indicates thepresence of read or write operations.

1. (rx,,wx)

2. (rx,,wx)

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Linked and Unlinked Faults

When the fault may influence the behavior of the other

faults is called Linked Faults.

When the fault does not influence the behavior of otherfaults called Unlinked Faults.

SAF linked with TFs and CFs

TFs linked with CFs

Afs linked with SAFs/TFs/CFs

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Zero-One

(w0);(r0);(w1);(r1);

This test algorithm has minimum set to detect

the fault

All SAFs are detectable.

TF is not detectable.

CFs , and are not detectable.

Not all Afs are detectable.

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Checkerboard

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Cells are divided in two groups cell-1 & cell-2.

0s and 1s are written alternate pattern and make the

checkerboard pattern.

All SAFs are detectable.

Not all Afs ,TFs and CFs are detectable.

Mainly used for sleeping sickness in DRAM chip.

Pattern 1 Pattern 2

1 0 1 0

0 1 0 1

1 0 1 0

0 1 0 1

0 1 0 1

1 0 1 0

0 1 0 1

1 0 1 0


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Walking 1/0

Memory is filled with 0s(or 1s) except for the base-cell, whichcontains 1(respectively a 0).

During Test, the base cell walks through the memory.

All cells read with the base cell last.

All Afs, SAF, TFs, Coupling faults are detectable.

0 0 0 0

0 1 0 0

0 0 0 0

0 0 0 0

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GALPAT

Memory is filled with 0s(or 1s) except for the base-cell,which contains 1(respectively a 0).

During Test, the base cell walks through the memory.

Base cell is read after each cell of memory read.

0 0 0 0

0 1 0 0

0 0 0 0

0 0 0 0

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Sliding Diagonal

Uses diagonal of base cell instead of single base cell because eachcell has a different row and column address so that it checking the

row and column simultaneously.

Writes diagonal 1s to background of 0s. All memory cells are read,after which diagonal is shifted until all diagonal are not covered.

1 0 0 0 0 0 1 0

0 1 0 0 0 0 0 1

0 0 1 0 1 0 0 0

0 0 0 1 0 1 0 0

First Diagonal Third Diagonal

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MATS Algorithm MATS requires total 4*n operations.

(w0); (r0,w1); (r1) ;

M0 M1 M2

M0=(w0); M1=(r0,w1); M2=(r1);

M0:for :=0 to n-1 do

begin

A[i]:=0;

end; Same for M1 and M2;

Fault coverage is very poor not capable of detection of

Coupling Faults.

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Moving 1/0 Algorithm

(w0); (r0,w1,r1); (r1,w0,r0); (w1); (r1,w0,r0);(r0,w1,r1); Here ji (;) Operation Cj Ci

M5 on Cj r0 0 0

M5 on Cj w1 1 1

M5 on Cj r1 1 1

M5 on Ci r0 1 1

j


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MATS++ Algorithm

(w0);(r0,w1);(r1,w0,r0);

SAFs :- (M1) and (M2)

TFs :- (M1 and M2) and (M2) Afs are detected by given above conditions.

This algorithm cant detect any coupling faults.

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March X Algorithm

(w0);(r0,w1);(r1,w0)(r0);

All Afs are detected.

SAF :- (M1 or M3) and (M2)

TFs :- (M1 followed by M2) and (M2 followed by M3)

Cfin (ji) :- Ci Cj detected by M1 followed by M2

Ci Cj detected by M2 Idempotent faults ,(only when j


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March C- Algorithm

(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0);

Unlinked Idempotent Coupling Faults(Cfid), SAF, TFS, Cfin, Afs.

Ci Cj :- M3 followed by M4 and M1 followed by M2

Ci is coupled to Cj means transition in j cell causes cell i to 0 logicvalue.

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ji Operation Cj Ci

M1 on Ci r0 0 0

M1 on Ci w1 0 1M1 on Cj r0 0 1

M1 on Cj w1 1 0

M2 on Ci r1 1 0


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March C- Algorithm (w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0);

Ci Cj :- M1 and M3

Ci Cj :- M4 followed by M5 and M2 followed by M3

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ji (;1) Operation Cj Ci

M3 on Cj r0 0 0

M3 on Cj w1 1 1

M3 on Ci r0 1 1

ji (;1) Operation Cj Ci

M2 on Ci r1 1 1

M2 on Ci w0 1 0

M2 on Cj r1 1 0

M2 on Cj w0 0 1

M3 on Ci r0 0 1


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March C- Algorithm

(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0);

Ci Cj :- M2 and M4

Ci Cj :- M1 as well as M3 followed by M4 and M3

Ci Cj:- M2 as well as M4 followed by M5 and M4

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j


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March A Algorithm

(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0);

AFs,SAFs Unlinked TFs

Unlinked Cfins

Linked Cfids

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March A Algorithm


Ci Cj:- M2 and M1 as well as M4

Ci Cj :- M1 as well as M2 and M4

Ci Cj & Ci Cj:- M1 and M3

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j


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March A Algorithm



Ci Cj (possibly Ci Cj or Ci Cj) :- M2

Ci Cj (possibly Ci Cj or Ci Cj) :- M1

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j


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March A Algorithm


Ci Cj (not possibly Ci Cj or Ci Cj) :- M2 Ci Cj (not possibly Ci Cj or Ci Cj) :- M1

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j


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March A Algorithm



Ci Cj (possibly Ci Cj or Ci Cj ) :- M3 Ci Cj (possibly Ci Cj or Ci Cj ) :-M4

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j>i (;0) Operation Cj Ci

M3 on Cj r1 1 1

M3 on Cj w0 0 0

M3 on Cj w1 1 0/1

M3 on Cj w0 0 0

M4 on Ci r1 0 0


M4 on Cj r0 0 0

M4 on Cj w1 1 0/1

M4 on Cj w0 0 1

M4 on Ci r0 0 1


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March A Algorithm



Ci Cj (not possibly Ci Cj or Cj) :- M3

Ci Cj (not possibly Ci Cj or Cj) :-M4

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M3 on Cj r1 1 1

M3 on Cj w0 0 1

M3 on Cj w1 1 0

M3 on Cj w0 0 0

M4 on Ci r1 0 0


M4 on Cj r0 0 0

M4 on Cj w1 1 1

M4 on Cj w0 0 1

M4 on Ci r0 1 1


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March Y Algorithm

(w0);(r0,w1,r1);(r1,w0,r0);(r0);

AFs,SAFs are detectable.

TFs,Cfins are detectable. TFs linked with Cfins.

Ci Cj, Ci Cj Idempotent Faults are detectable.(j>i and j


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March Y Algorithm

(w0);(r0,w1,r1);(r1,w0,r0);(r0);

Ci Cj :- M2 (j>i)

Ci Cj :- M1 (j


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March B Algorithm

(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0);

Afs ,SAFs are detectable.

TFs ,CFs are detectable.

TF Linked Cfins & Cfids are detectable due to extra read operation is

performed immediately after the transition.

This extra read is not allowed TFs to masked by CFs because no

other write operations are performed to other cells.

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Comparison Between March Algorithms

Algorithms No. of Operation Fault Coverage

Mats 4n SAF, Some AF

Mats++ 6n SAF,AF

March X 6n SAF, AF, TF, Cfin

March C- 10n SAF, AF, TF,CF

March A 15n SAF, AF, TF, Linked Cfid ,Cfin

March Y 8n SAF, AF, Linked TF with Cfin

March B 17n SAF, AF, Linked TF with CFin &

CFid

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Moving Inversion (MOVI)

(w0);(r0,w1,r1);(r1,w0,r0);(r0,w1,r1);(r1,w0,r0)

MOVI used for functional test as well as the AC Parametric

test.

Any read or write operation in cell j disturb the content ofcell i will detect and also determine best & worst access

time with different address and different data pattern of

the chip.

Memory initialized to contain all 0s then this string of 0s isinverted successively to become all 1s and vice versa.

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Detection of read /write disturbances

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Operation on

bit j

Disturbance of bit i Fault detected by

j>i i>j

r0 M3 M1 M4 M2

r1 M3 M1

M4 M2

w0 M2-M3 M0-M1

M4 M2

w1 M3 M1

M1-M2 M3-M4


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Determination of the access time

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Current Next Performed by

March

element

Address Operation Address Operation

Ax r0 Ay r1 M2

Ay r0 Ax r1 M4

Ax r1 Ay r0 M1

Ay r1 Ax r0 M3


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Future Work

Test time and test operations are crucial factor formemory testing.

Develop such algorithm that find the maximum fault

coverage with efficient test time and test operation.

Develop effective algorithm which can find the

dynamic and physical defect fault with functional

faults.

Write recovery, Refresh line stuck-at, Sleepingsickness, Static data loss.

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Conclusion

Zero-one, Checkerboard are simple algorithms to test only SAFs

and address decoder faults.

GALPAT, Sliding window are used to test for coupling faults.

March algorithms are very well suitable with different patterns

to detect the common memory functional faults.

March B and March Y are covered to detect most of the

functional faults but it requires many operations and too much

time so that trade off requires between time of test, operation

to fault detection.

NPS fault are also crucial in large density memory to test but

these types of faults are complicated, not easy to locate and

requires large time to test them.

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Reference

Testing Semiconductor Memories by Van De

Goor

Design For Testability by wang-wu-wen

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Any Question


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Thank You

Documents

Memory Testing Algorithm