Random access memory testing : theory and practice .Random access memory testing : theory and practice

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  • Random access memory testing : theory and practice :the gains of fault modellingVeenstra, P.K.

    Published: 01/01/1986

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    Download date: 18. Aug. 2018

    https://research.tue.nl/en/publications/random-access-memory-testing--theory-and-practice--the-gains-of-fault-modelling(74053ef0-7871-47f1-9f25-efdce22baf37).html

  • Random Access Memory Testing: Theory and practice The Gains of Fault Modelling

    by P.K. Veenstra

    EUT Report 86-E-161 ISBN 90-6144-161-7 ISSN 0167-9708 October 1986

  • Eindhoven University of Technology Research Reports

    EINDHOVEN UNIVERSITY OF TECHNOLOGY

    Department of Electrical Engineering

    Eindhoven The Netherlands

    RANDOM ACCESS MEMORY TESTING: THEORY AND PRACTICE

    The Gains of Fault Modelling

    by

    P.K. Veenstra

    EUT Report 86-E-161

    ISBN 90-6144-161-7

    ISSN 0167-9708

    Coden: TEUEDE

    Eindhoven

    October 1986

  • CIP-GEGEVENS KONINKLIJKE BIBLIOTHEEK, DEN HAAG

    Veenstra, P.K .

    . Random access memory testing: theory and practice. The gains of fault modelling / by P.K. Veenstra. - Eindhoven: University of Technology. - Fig., tab. - (Eindhoven University of Technology research reports / Department of Electrical Engineering, ISSN 0167-9708; 86-E-161) Met lit. opg., reg. ISBN 90-6144-161-7 SISO 664.2 UDC 621.382.001.42 NUGI 853 Trefw.: elektronische schakelingen; tests.

  • - III -

    ABSTRACT

    i"unct:ioflal b~st_ ing of Random Access Memories gives more and more IJroblems. At the one hand, the dimensions are growing rapidly and the denser devices result in multiple failure modes. At the other hand, the accessibility of embedded memory elements on modern VLSI circuits decreases. The goal of the research was the evaluation and the mutual comparison of the eXisting methods and ideas in this field, eventually followed by setting up methodologies to improve the testability of embedded RAM's. After the literature has been inventoried, the decision was made to examine the large diversity of test patterns by means of large-scale measurements. Such a session has been executed two times and the results affirm the previous assumptions, namely:

    1. the use of a well-defined fault model translates itself into a better fault coverage and more efficient test patterns;

    2. time-dependent failures require specific measures.

    SAMENVATTING

    Het functioneel testen van Random Access Memories leidt in toenemende mate tot problemen. Enerzijds nemen de dimensies steeds grotere vormen aan en veroorzaakt de schaalverkleining een veelvoud van foutenbronnen. Anderzijds ontstaan moeilijkheden met be trekking tot de toegankelijkheid van geintegreerde geheugenmodulen in VLSI-schakelingen. Doel van de opdracht betrof.het evalueren en onder ling vergelijken van de reeds voorhanden zijnde methoden en ideeen op dit gebied, alsmede het opstellen van methodieken om de geintegreerde geheugenelementen beter testbaar te maken, zover als de tijd dit toelaat. Na een inventarisatie van de literatuur werd besloten de grote verscheidenheid aan testpatronen middels groot-schalige metingen te onderzoeken. Tot tweemaal toe is een dergelijke meetsessie uitgevoerd en de resultaten bevestigen eerdere veronder-stellingen, namelijk:

    1. het hanteren van een goed gefundeerd foutmodel vertaalt zich in een betere foutdetectie en efficientere testpatronen;

    2. de tijdsafhankelijke fouten vereisen specifiekere maatregelen.

    Veenstra, P.K. RANDOM ACCESS MEMORY TESTING: Theory and practice. The gains of fault modelling. Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands, 1986. EUT Report 86-E-161

  • - IV -

    PREFACE

    The research was conducted within the scope of the training for the M.Sc. degree in electrical engineering at the Eindhoven University of Technology. The Philips Research Laboratories in Eindhoven offered me the opportunity and had the disposal of the necessary facilities to do the investigations.

    The work was carried out within the group "CAD for VLSI systems" in close co-operation with the group "test and analysis".

    The appointed task was to draw up an inventory of the existing Random Access Memory testing methods and to compare their properties with respect to fault coverage and complexity.

    The time was spent as follows:

    from mid September 1985 to mid November 1985: study of literature from mid November 1985 to mid February 1986: setting up test program from mid February 1986 to mid March 1986: analysis of the results from mid March 1986 to mid April 1986: setting up test program from mid April 1986 to end April 1986: analysis of the results

    1

    2

    from beginning May 1986 to end May 1986: first edition of the thesis from beginning June1986 to mid July 1986: speeches,

    The work was supervised by:

    Prof. ir. A. Heetman and ir. M.J.M. van Weert, Group of Digital Systems, Department of Electrical Engineering,

    final thesis,

    Eindhoven University of Technology, The Netherlands

    and

    ir. F.P.M. Beenker and Dr. J.J.M. Roomen, Philips Research Laboratories, Eindhoven, The Netherlands

    paper.

  • - v -

    TABLE OF CONTENTS

    PREFACE

    1 COMPONENT TESTING: A SURVEY

    1.1 1.2 1.3 1.4 1.5 1.6 1.6

    Introduction Logical Fault Models Testing Problems Design for Testability Macro Testing Future Developments Considerations

    2 RANDOM ACCESS MEMORIES

    2.1 2.1.1 2.1. 2 2.1. 3

    2.2 2.2.1 2.2.2 2.2.3 2.2.4

    2.3 2.3.1 2.3.2 2.3.3 2.3.4

    2.4

    Dynamic versus Static RAMs Operation of a DRAM cell Operation of a SRAM cell Application Areas

    Internal Organization of a RAM Memory Array Addressing Mechanism Data Flow Control Circuitry

    Large Density RAMs Developments Diagnostic Tools Built-in Redundancy Address Scrambling

    Embedded RAMs

    3 MEMORY TESTING: A SURVEY

    3.1

    3.2 3.2.1 3.2.2

    3.3 3.3.1 3.3.2 3.3.3

    3.4

    Introduction

    Failure Modes Testing Methods Typical Malfunctions in a RAM

    Ad-hoc Test Procedures Historical Background Test Time Considerations and Fault Coverage Engineering Area . .

    Stuck-at Faults in RAMs

    IV

    1 1 2 3 5 5 6

    7 7 7 8

    9 9

    11 11 12

    13 13 13 14 15

    16

    17

    18 18 19

    21 21 21 22

    22

  • 3.5 3.5.1 3.5.2 3.5.3 3.5.4

    3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6

    3.7 3.8

    3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6

    - VI -

    Testing for 2-Coupling Faults Fault Model for 2-Coupling Ad-hoc Test Procedures Tests for Coupling Faults Considerations

    Pattern-Sensitive Faults Historical Background Neighborhood. . Tiling of the Memory Array Types of Pattern-Sensitive Test Procedures Considerations

    Structural Testing Review of the Test Procedures

    Self-test and Embedded RAMs Large Density RAMs Embedded RAMs

    Faults

    Faults

    Self-Test Circuit with a PLA Self-Test Program in ROM Other Developments Considerations

    4 MEMORY TESTER AND MEMORY TEST PROGRAMS

    4.1

    4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5

    4.3

    4.4 4.4.1 4.4.2 4.4.2

    Introduction

    Memory Test System System Architecture Address Counters Data Generation Signal values and Timing Software Environment

    Analysis Tools of the Tester

    Memory Test Programs Starting Points Memory Test Program 1 Memory Test Program 2

    5 DISCUSSION OF THE RESULTS

    5.1 5.2

    5.3 5.3.1 5.3.2

    Introduction . . .. .... Techniques to Analyse the Test Results

    Results of Memory Test Program 1 Discussion of the Time-Dependent Faults Discussion of the Permanent Faults

    24 24 24 25 27

    28 28 28 29 30 30 31

    32 33

    35 35 36 37 38 38 39

    40

    40 40 42 43 44 44

    46

    47 47 48 50

    52 53

    55 56 61

  • - VII -

    5.4 5.4.1 5.4.2

    Results of Memory Test Program 2 ..... Discussion of the Time-Dependent Faults Discussion of the Permanent Faults

    5.5 5.5.1 5.5.2

    Summary and Memory Test Strategies Summary of the Test Results Memory Test S

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