Memory Testing and Built -In Self -Test - Elsevier Chapter 08... · Memory Testing and Built -In Self -Test. ... – High fault coverage – Short test time. ... Sequential ATPG is

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 1

    Chapter Chapter 88

    Memory Testing and BuiltMemory Testing and Built--In SelfIn Self--TestTest

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 2

    What is this chapter about?What is this chapter about?

    Basic concepts of memory testing andBIST

    Memory fault models and test algorithms

    Memory fault simulation and test algorithm generation RAMSES: fault simulator

    TAGS: test algorithm generator

    Memory BIST BRAINS: BIST generator

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 3

    Typical RAM Production FlowTypical RAM Production Flow

    WaferWafer Full Probe Test

    Marking

    Final Test ShippingQA Sample TestVisual Inspection

    Burn-In (BI)Post-BI Test

    Laser Repair Packaging

    Pre-BI Test

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 4

    OffOff--Line Testing of RAMLine Testing of RAM

    Parametric Test: DC & AC

    Reliability Screening Long-cycle testing

    Burn-in: static & dynamic BI

    Functional Test Device characterization

    Failure analysis

    Fault modeling Simple but effective (accurate & realistic?)

    Test algorithm generation Small number of test patterns (data backgrounds)

    High fault coverage

    Short test time

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 5

    DRAM Functional ModelDRAM Functional Model

    Read/write &

    chip enable

    Address latch Column decoder

    Memory cell

    array

    Row decoder

    Refresh logic

    Write driver

    Data registerSense amplifiers

    AddressRefresh

    Data out

    Data in

    Data flow

    Control flow

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 6

    DRAM Functional Model ExampleDRAM Functional Model Example

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 7

    Functional Fault ModelsFunctional Fault Models

    Classical fault models are not sufficient to

    represent all important failure modes in RAM.

    Sequential ATPG is not possible for RAM.

    Functional fault models are commonly used

    for memories:

    They define functional behavior of faulty

    memories.

    New fault models are being proposed to

    cover new defects and failures in modern

    memories:

    New process technologies

    New devices

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 8

    Static RAM Fault Models: SAF/TFStatic RAM Fault Models: SAF/TF

    Stuck-At Fault (SAF)

    Cell (line) SA0 or SA1

    A stuck-at fault (SAF) occurs when the value of a cell or

    line is always 0 (a stuck-at-0 fault) or always 1 (a stuck-

    at-1 fault).

    A test that detects all SAFs guarantees that from each

    cell, a 0 and a 1 must be read.

    Transition Fault (TF)

    Cell fails to transit from 0 to 1 or 1 to 0 in specified

    time period.

    A cell has a transition fault (TF) if it fails to transit from 0

    to 1 (a TF) or from 1 to 0 (a TF).

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 9

    Static RAM Fault Models: AFStatic RAM Fault Models: AF

    Address-Decoder Fault (AF)

    An address decoder fault (AF) is a functional fault in the address decoder that results in one of four kinds of abnormal behavior:

    Given a certain address, no cell will be accessed

    A certain cell is never accessed by any address

    Given a certain address, multiple cells are accessed

    A certain cell can be accessed by multiple addresses

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 10

    Static RAM Fault Models: SOFStatic RAM Fault Models: SOF

    Stuck-Open Fault (SOF)

    A stuck-open fault (SOF) occurs when the cell cannot be accessed due to, e.g., a broken word line.

    A read to this cell will produce the previously read value.

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 11

    RAM Fault Models: CFRAM Fault Models: CF

    Coupling Fault (CF)

    A coupling fault (CF) between two cells occurs when the logic value of a cell is influenced by the content of, or operation on, another cell.

    State Coupling Fault (CFst) Coupled (victim) cell is forced to 0 or 1 if coupling

    (aggressor) cell is in given state.

    Inversion Coupling Fault (CFin) Transition in coupling cell complements (inverts) coupled

    cell.

    Idempotent Coupling Fault (CFid) Coupled cell is forced to 0 or 1 if coupling cell transits

    from 0 to 1 or 1 to 0.

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 12

    IntraIntra--Word & InterWord & Inter--Word CFsWord CFs

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 13

    RAM Fault Models: DFRAM Fault Models: DF

    Disturb Fault (DF)

    Victim cell forced to 0 or 1 if we

    (successively) read or write aggressor cell

    (may be the same cell):

    Hammer test

    Read Disturb Fault (RDF)

    There is a read disturb fault (RDF) if the cell

    value will flip when being read (successively).

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 14

    RAM Fault Models: DRFRAM Fault Models: DRF

    Data Retention Fault (DRF)

    DRAM

    Refresh Fault

    Leakage Fault

    SRAM

    Leakage Fault

    Static Data Losses---defective pull-up

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 15

    Test Time Complexity Test Time Complexity (100MHz)(100MHz)

    Size N 10N NlogN N1.5

    N2

    1M 0.01s 0.1s 0.2s 11s 3h

    16M 0.16s 1.6s 3.9s 11m 33d

    64M 0.66s 6.6s 17s 1.5h 1.43y

    256M 2.62s 26s 1.23m 12h 23y

    1G 10.5s 1.8m 5.3m 4d 366y

    4G 42s 7m 22.4m 32d 57c

    16G 2.8m 28m 1.6h 255d 915c

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 16

    RAM Test AlgorithmRAM Test Algorithm

    A test algorithm (or simply test) is a finite

    sequence of test elements:

    A test element contains a number of memory

    operations (access commands)

    Data pattern (background) specified for the Read and Write operation

    Address (sequence) specified for the Read and Write operations

    A march test algorithm is a finite sequence of

    march elements:

    A march element is specified by an address order and a finite number of Read/Write operations

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 17

    March Test NotationMarch Test Notation

    : address sequence is in the ascending order

    : address changes in the descending order

    : address sequence is either or

    r: the Read operation Reading an expected 0 from a cell (r0); reading an expected

    1 from a cell (r1)

    w: the Write operation Writing a 0 into a cell (w0); writing a 1 into a cell (w1)

    Example (MATS+): )}0,1();1,0();0({ wrwrw c

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 18

    Classical Test Algorithms: MSCANClassical Test Algorithms: MSCAN

    Zero-One Algorithm [Breuer & Friedman 1976]

    Also known as MSCAN

    SAF is detected if the address decoder is correct

    (not all AFs are covered):

    Theorem: A test detects all AFs if it contains the march

    elements (ra,,wb) and (rb,,wa), and the memory is initialized to the proper value before each march

    element

    Solid background (pattern)

    Complexity is 4N

    )}1();1();0();0({ rwrw cccc

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 19

    Classical Test Algorithms: CheckerboardClassical Test Algorithms: Checkerboard

    Checkerboard Algorithm

    Zero-one algorithm with checkerboard pattern

    Complexity is 4N

    Must create true physical checkerboard, not

    logical checkerboard

    For SAF, DRF, shorts between cells, and half of

    the TFs

    Not good for AFs, and some CFs cannot be detected

    1 0 1

    0 1 0

    1 0 1

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 20

    Classical Test Algorithms: GALPATClassical Test Algorithms: GALPAT Galloping Pattern (GALPAT)

    Complexity is 4N**2only for characterization

    A strong test for most faults: all AFs, TFs, CFs, and

    SAFs are detected and located

    1. Write background 0;

    2. For BC = 0 to N-1

    { Complement BC;

    For OC = 0 to N-1, OC != BC;

    { Read BC; Read OC; }

    Complement BC; }

    3. Write background 1;

    4. Repeat Step 2;

    BC

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    VLSI Test Principles and Architectures Ch. 8 - Memory Testing & BIST - P. 21

    Classical Test Algorithms: WALPATClassical Test Algorithms: WALPAT

    Walking Pattern (WALPAT)

    Similar to GALPAT, except that BC is read only

    after all others are read.

    Complexity is 2N