Lab3: Pipeline

Lab3: Pipeline

Dimitar Nikolov

Lund University / Electrical and Information Technology / 1

Goal

• Understand how pipelining works

• Learn what happens in different pipeline stages

• Leran how to avoid pipeline hazzards


Tools

• Tools used for this exercise:

– MipsIt.exe

– MipsPipeS.exe

Used for program editing

Used for simulation


Online test

• The online test is scheduled on Monday 23th November

• Access the test from the course web-page

• Example of an online test is provided


Overview

• Background

• Simulation


Motivation

• Instructions are exectued one at a time

• Each instruction occupies a set of resources

– access to memory

– access to registers

– access to ALU

• Resources are not occupied all the time

• Execution of an instruction can be split into a number of

stages

• Overlap execution of instructions

• Goal: improve throughput (number of instructions over time)


Pipeline

• Execution of instructions is split into a sequence of

dependent stages

• Once an instruction has completed with one stage it can

proceed to the next stage, and a new instruction can take

over the stage that has been released

• The time to execute a single instruction is not altered

• The number of executed instructions over time is increased


MIPS pipeline

• Five stages, one step per stage

1. IF: Instruction fetch from memory

2. ID: Instruction decode & register read

3. EX: Execute operation or calculate address

4. MEM: Access memory operand

5. WB: Write result back to register


IF (Instruction Fetch)


ID (Instruction decode & register read)


EX (Execute operation or calculate address)


MEM (Access memory operand)


WB (Write result back to register)


Potential hazards

• Structural hazards

– A resource is used by two instructions that are in

different pipeline stages

• Data hazards

– Due to data dependencies between instructions

• Control hazards

– Due to branch instructions


Structural hazards

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

Memory

read

IF ID EX MEM WB

time

Use separate Instruction and Data Cache


Data hazards

ADD $s0, $t0, $t1

SUB $t2, $s0, $t3 Read after Write (RAW) dependency


Data hazards

Need to stall

for one cycle

Forwarding


Data hazards

Stall inserted

here


Control hazards

• Branch is taken or not taken

• The next instruction to be fetched might depend on the

branch condition

• The condition may not be evaluated before the branch

instruction reaches the MEM stage in the pipeline

• Unneeded instructions are already in the pipeline


Control hazards

• To avoid:

– Delayed branching (place the branch instruction earlier

in the code, without violating data dependencies, and

proceed with the instructions that must be executed

irrespective of the evaluation of the branch condition)

– Delayed branching (add nops after the branch

instruction, such that in case the branch is taken the

nops will fill in the pipeline prior to the execution of

instructions that should be executed when the branch

is taken)


Overview

• Background

• Simulation


Compile, Build and Upload


MipsPipeS

Click to see the pipeline


MipsPipeS Simulate by stepping


Documents

Lab3: Pipeline