Cells Manipulation in L-Edit
Digital System Layout options:1. Full Custom. Every detail of the integrated circuit layout needs to be completed. All gates y g y p gmust be designed, drawn, and simulated.
Advantages: reduced area and performance improvements. Disadvantages: Disad antages: increased man fact ring and design time more complexity in the manufacturing time, comple it computer-aided design (CAD) system, and a much higher skill requirement on the part of the design team. It is appropriate for chips having large production runs.
Cell Based. Layout designs are based on exiting layout cells stored in a libraries. These librariesare provided by the device manufacturer. Using the software, the interconnections can be done manually or automatically by what is called Place and Routing..
Advantages: Fast, design can be changed easily and not need much higher skills in layout. Disadvantages: increased area, less performance. In this session you start layout a digital system according to cell based.
Cells Manipulation in L Edit L Edit L-Edit Cells Maniulation in L-Edit L-Edit provides very p p y powerful commands for creating, editing, and g g applying cells in layout drawings. These are accessed from the Cell Window of the Menu Bar. cell libraries will be available when the file is opened.
Cells Manipulation in L Edit L-Edit Every drawing in L-Edit is labeled with a file name, y g , with the default name being Layout1. The cell name is assigned to the drawing on the screen; the default g g ; name is cell0.
Cells Manipulation in L Edit L-Edit It is possible to create cells and store them in the memory. Stored cells can be accessed using the Instance Command. When this command is executed, a list of currently available cells is displayed. The
Cells Manipulation in L Edit L-Edit All integrated circuits require power distribution bus lines to supply current to the gates. In CMOS, usually a positive VDD and a ground or VSS must be routed across the die. It is g important to use geometrical structure that accommodates the shape of the logic cell as shown in the figure below.
Cells Manipulation in L-Edit p
power di t ib ti distribution bus lines
Cells Manipulation Example p p Suppose you want to draw the layout of the following D-Flip Flop. If you have the layout of 3-inputs Nand as a standard cell in your Library then it will be easier to draw the layout. But if you dont have that Library, create a cell for the 3-inputs Nand and use it to create the D-Flip Flop. Thats will be done in this session.
DFF Cells Manipulation Example RunLEditandSavethefileasprogect.tdb p g
DFF Cells Manipulation Example p p From main menu, select Cell>> Rename and change cell name from Cell0 to nand3
DFF Cells Manipulation Example p p Draw the layout of the 3-input nands as below, check the design rules, rules extract to spice and simulate to be sure the layout is correct. correct
DFF Cells Manipulation Example p p From main menu, select Cell>> New ,put the new cell name as dfilipflop as below
DFF Cells Manipulation Example p p New empty cell will be opened, with dflipflop as a name in the project.tdb file project tdb file.
DFF Cells Manipulation Example p pFrom main menu, select Cell>> Instance ,and select nand3 cell.
DFF Cells Manipulation Example p pThe nand3 cell will be inserted in the dflipflop cell.
DFF Cells Manipulation Example p pYou needs six nand3 cells, select Cell>> Instance ,and choose nand3 cell again because you need extra five cells. d ll i b d fi ll
DFF Cells Manipulation Example p p
DFF Cells Manipulation Example p pThe six nand3 cells are shown but without connections between them. them
DFF Cells Manipulation Example p pDo the extra connection to have D Flip Flop. Check design rules, extract to spice and make sure that the layout work correctly as DFF. DFF
Cells Manipulation Assignment Before you have created a file that contains two cells, the cells inverter cell and the 2-inputs Nand cell. Modify the layout of the Nand gate such that it has the same p speed of the inverter. In the same file create a new cell for 2-input Nor also has the p same speed of the inverter. Use the three previous cells, to draw a 3-inputs And gate. Verify the layout with SPICE.