Introduction to Sigma Delta Converters

8/4/2019 Introduction to Sigma Delta Converters

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Introduction to Sigma Delta

Converters

P.V. Ananda Mohan

Electronics Corporation of IndiaLimited,

Bangalore


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How to reduce analog part?

Use Sigma-Delta Conversion

Front-end simple active RC Filter

SC/Gm-C Sigma- Delta converter working at highsampling frequency

Digital Decimation Filter using DSP

Scalable with digital technology Only few OTAs or opamps, one comparator

needed, MOS switches needed


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MODERN CODEC-FILTER

Active RCFilter

input

SIGMA-DELTA

Converter

DecimationDigital

Filter Digital

outputOver

sampling

ClockDigitalFilter

clocks


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What is sigma-delta conversion?

Similar to Delta Modulation but can code dc(i.e.Slowly varying signals)

Generates One bit output sequence Output word is obtained from this sequence by

finding the average using a decimator.

Also called Pulse density modulation

Also called over-sampled A/D conversion High resolution up to 19 bits

Uses Oversampling and Noise shaping

Trades off accuracy in amplitude with accuracy intime


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Advantages

Analog part small area

Over sampling ratio typically 8 to 256.

Megahertz range up to 16 bits

Band-pass Sigmadelta solutions are also

available.


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First-Order Sigma Delta Modulator

+

-

+

-

I bit DAC

Integrator

Comparator

Differenceamplifier

V1Vin

Vref

V2

Consider Vin=0.2 volts and Vref=1 volt.Number V1 V2 V0 Dout1 .2 .2 1 1

2 -.8 - .6 0 - 1

3 1.2 .6 1 1

4 - .8 - .2 0 - 1

5 1.2 1.0 1 1

6 -.8 .2 1 17 - .8 -.6 0 -1

8 1.2 .6 1 1

9 -.8 - .2 0 -1

Average of Dout = (-1+1-1+1+1)/5 = 1/5 = 0.2

Result for 20 samples

Input volts Sequence of output bits

0.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0.1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1

0.2 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1

0.7 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 10.9 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

1.0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Vo(z)= Vi(z)+en.(1-z-1)

Vo


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Two-loop Sigma-delta modulator

Vo(z)=Vi(z)+en.(1-z-1)2 Second order noise

shaping

+Integrator

z-1

/(1-z-1

)

+Integrator

z-1

/(1-z-1

)

comparator

latch

input+

output

clock

2

Latch


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Quantization noise of a linear

A/D

Difference between staircase and linear is a

triangular waveform.

/2

-/2

input

output


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Linear models for Analysis

Vo(z)= Vi(z)+en.(1-z-1)

Input low-pass and en high-pass transfer

function; Shaping the Quantization noise!!!

+

-

+

-

I bit DAC

Integrator

Comparator

Differenceamplifier

V1Ain

Vref

V2

en

Integrator

z-1/(1-z-1)Vi Vout

-

z

-1

Integrator or

Accumulator


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Quantization noise for an A/D converter

12..

12

2/

2/

22

eee qqn d

If peak to peak is FSR (Full scale range) , RMSvalue is FSR/(22).

02.6

76.1

)76.102.6(02.678.702.62

6log.20

2

6

22

12

12

22

12

2

22

2

SNRENOB

dBNN

FSR

FSR

SNR

N

dB

NN

N

RMS

SNR

V


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Quantization noise of a Sigma

delta converter

Noise shaping function (1-z-1) L

(1-z-1) L =(1-e-jT) L = (e-jT/2)L.(ejT/2 -e-jT/2)L

|(1-z-1

)L

|

=

| (ejT/2

-e-jT/2

)L

| = 2. Sin(f/fs)

= (2f/fs)L

12.

12.

12.

12.

12

11

22

12

122

2

2

22

2

1

Ls

Ls

dfNoise

LL

L

L

L

Tejz

L

s

f

ff

f

zf


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Candys Formula

M

ff

L

LL

L

L

Ls

DRRangeDynamic12

22

2

12

2

.12

.2

3

12.

12.

22

02.6

76.1DRdB

ENOB


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Advantages

(1-z-1)L has L zeros at dc

Signal and Quantization noise are treated

differently.

Output word is obtained from a sequence

of coarsely sampled input samples.

Analog part small area

Typical oversampling ratio 8 to 256.


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For a Nyquist rate ADC DR2 = 3.22B-1

For Second Order Sigma delta Converter,

16.5.23 5

4

DR

16.

7.

2

3 7

6

DRM16, L=3

M=16, L=2

Ratio is 15.6 dB.

For M = 256, Ratio is ?????


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Decimation filter

Occupies large area and consumes power.

Linear Phase FIR filter can be used.

Comb filters preferred since the input datais one bit wide only.

Can Reduce sampling rate to four times the

Nyquist rate. Lth order Noise shaping function, L+1th

order decimator is required.


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Decimation filter

Local average can be computed efficiently

by by a decimator.

Frequency response

)sin(

)sin(.

1

11

1

Tsf

TsfD

Dz

z Dk

k


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Decimation filter

Decimation is reduction of sampling rate

Comb filters are used

Fixed coefficient FIR filters

One,Two or Three stages

Some designs use fixed coefficient IIR filters

Second order Sigma delta converter neds third-order decimator filter.


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Decimation filter example

input

output

clockAccumulator

Latch

Input

Stream

Output

word

Lower

Clock

H(z) = (1-z-64)/(1-z-1)


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DECIMATION FILTERS

Second order Decimator

H(z) = (1-z-64)2/(1-z-1)2

Third-Order Decimator H(z) = (1-z-64)3/(1-z-1)3

Design is slightly involved-Three parallel

processors Coefficient generation is dynamic for both

designs


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ARCHITECTURES


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ARCHITECTURES

Single stage Multiloop feedback

Multistage Noise Shaping (MASH)

Cascade Designs

Leslie-Singh Architecture


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Fifth order single stage delta sigma

modulator

+ ++

+

z-1/(1-z-1)

z-1/(1-z-1)

z-1/(1-z-1)

z-1/(1-z-1)

Q

z-1/(1-z-1)

in

a1 a3 a4 a5a2

+- - - -

-

Q Quantizer n bit Output

Fifth O d L F Si D lt


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Fifth-Order Leap-Frog Sigma-Delta

Modulator

-

-

B2 b4b5

a1 a2 a3 a4a5

z-1/(1-z-1)

z-1/(1-z-1)

z-1/(1-z-1)

z-1/(1-z-1)

z-1/(1-z-1)

ADC

DAC

OUT

b1 b3b5

-

--

-

IN


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Single Loop Designs

No non linearity of DAC problems: only two

levels one and zero. Quantization noise power is very high and hence

Need large over-sampling ratio

Single loop Sigma-delta modulators, gainprogressively increases and overloads thecomparator.

Delay also. Input change is felt after five stages.

High coefficient spread (large area)


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Single Loop Designs

High coefficient sensitivity

Poor stability

All known digital filter structures cascade,

direct form, Leap frog can be used.

Single loop Sigma delta modulators reduce

integrator gin to achieve stability.

M l i i h i (MASH) A hi


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Multi stage noise shaping (MASH) Architecture

-

-

-

-

C1

X(z)

1/(1-z-1)

z-1

Cpmparator

-

1/(1-z-1)

z-1

Cpmparator

-

1/(1-z-1)

z-1

Cpmparator

-

-

z-1

C3

C2

z-1z-1


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MASH

Leakage is proportional to 1/Av2

Leakage is proportional to C2


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MASH Only last stage noise ideally remains.

Noise, distortion performance and Powerdissipation dependent largely on the first stageleakage.

Digital Noise cancellation circuits.

Output is a word not a bit as in the case of Singlestage 1 bit A/D based design.

Complicates digital filters following the Analogblocks.

Linear single bit Quantizer in the first stage

MASH needs to have low leakage, high opampgain 90dB low voltage applications not easily

realizable.


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MASH

Leakage of Quantization noise from each

stage is because of the finite gain of the OA

Capacitor mismatch also leads to leakage.

Many versions available called as 1-1-1,1-

2-1, etc indicating the order of the loop in

each stage.

Upto fifth order modulators built.

Leslie Singh Architecture


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L(z) N-bitADC

1/L(z)

1-bitDAC

N N

1

N+1

+

-

L(z) 1-bitADC

H1(z)

1-bitDAC

N N

1

N+1

+

-

N-bitADC

H2(z)


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This Architecture avoids matching problems of DAC

in first stage. Uses Two ADCs in effect.

1-bit

ADC

2z-1-z-2

1-bitDAC

N N-N+1

+-

N-bitADC

(1-z-1)2

Z-1 Z-1


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Why Multi-bit Sigma delta

converters? SNR can be improved by using multi-bit without

clocking fast, Candys formula

Problem of mismatch of resistors/capacitorsoccurs

Nonlinearity of DAC is troublesome

Number of bits increases exponentially thecomplexity (number of capacitors/resistors)

Typically restricted to 4 or 5 bits. Can be used as single stage Multibit or one stage

of MASH


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Bandpass Sigma Delta

Advantage immune to 1/f noise

No need for matching I and Q signals

Resonator

-

Input


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Band-Pass Sigma delta

Modulator

H(z)=z-2 and N(z)=(1+z-2)2 Transmission

zeroes at fs/4, Obtained by z-1 toz-2

transformation.

z-1/

(1+z-2)

z-1/

(1+z-2)

Compara

tor

z-1z-1

1-1

1/2

X(z)

Y(z)


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IMPLEMENTATION OPTIONS


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Implementation Options

Switched Capacitor

OTA-C

Continuous-time

Combinations


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SC Filters


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SC solution

SC preferred because of accurate control ofintegrator gains.

Fully Differential design increases signal

swing by two and dynamic range by 6dB. Common mode signals such as supply lines,

substrate are rejected

Charges injected by switches are cancelled.


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First integrator is important regarding noise,

linearity, settling behavior since second stage

Folded cascode Opamps recommended. Nonidealities of comparator undergo noise

shaping and hence not very critical.

Comparator can be simple.

Capacitors chosen based on noise requirements.

St I iti I ti


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Stray-Insensitive Inverting

Integrator

Vi

C1

C2

Vo

1

2

1

2


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Stray-Insensitive Non-inverting Integrator

Vo

1

2

Vi

C1

C21

2

Typical Fully Differential SC


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Typical Fully Differential SC

integrator

CC1d

2

_

+

Y YB1

2

1

Y

YB

1d

VREF+ VREF-

VREF- VREF+

Y

YB

2C

2C


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Timing to avoid charge injection

1

2

1d

2d


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Switch Implementation

Low ON resistance

Clock Feed-through (reduced by NMOS

transistor shunted by PMOS transistor)

Effect is to cause dc offset due to aliasing!

S

G

D

Inverter


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Auto Zero-ed Integrator

Haug-Maloberti-Temes

Cancels noise, offset and finite gain effects

Output held over a clock period.

-

+

C2

C4

C3

C1

o

e

o

e

o

e

o

e

o

ViVo


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Switch Non-idealities

Fully-differential circuits recommended Duplicated hardware; more area

Noise of switch due to ON resistance

kT/C noise, large capacitors need to be used forlow noise, noise independent of Switch ONresistance Ron

Charging and discharging time dependent on

SC Sigma delta modulators OA of largebandwidth at least five times the samplingfrequency and high gain are required.

CO A A O S


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COMPARATORS

Similar to OPAMPS but need logic leveloutputs

Input referred offset of MOSOpamps/comparators is quite high.

Offset compensation mandatory.

10 bit ADC with 1V signal, accuracy of acomparator is 1mV. Thus, residual offset

has to be much smaller than 1mV.

A MOS comparator Combining gain


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A MOS comparator Combining gain

stage and latch

Out+

M7M6

M5

M4

M3

M1 M2

In-

VB2

M9

M8

Out-

In+

VB1

StrobeStrobebar

T i l Bi l C


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Typical Bipolar Comparator

Latch is a regenerative (positive feedback ) circuit

Input

Vout

CKCKINV

Latch

Preamplifier

Fl h A hit t f M ltibit


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Flash Architectures for Multibit

Sigma delta converters Quite fast

Number of comparators needed exponentially

increases with bit length.

Resistor ladders needed.

Usually 4 to 5 bit Flash A/D used to reduce

area.

Fl h hi


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Flash architecture

Comparators

inputVref

Thermometercode

Polysilicon

Resistor Ladder


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Flash D/A converter Imperfections

Integral non-linearity

Differential non-linearity

Ac bowing due to input bias current drawn

by comparators.

Comparator kickback noise during transit

from latching to tracking


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CT Sigma Delta Modulators


56/72

CT loopfilter

ADC

DAC

_Input

CT Si D lt M d l t


57/72


Help to increase the clock frequency

Consume less power

OSR needs to be reduced for high bandwidthapplications.

No settling behavior problems. Relaxed sampling networks

More sensitive to clock jitter

ADC jitter not much trouble

But DAC jitter troublesome. Since it is not noiseshaped

Non-zero excess loop delay


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Large RC time constant variation

Mismatch between analog noise shaping anddigital noise shaping

CT Filters several alternative technologiesabvailable:

Active RC linear, not tunable

Gm-C less power consumption,High frequency,tunable

MOSFET-C non-linearity, advantage of tunability


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First stage is very important

Mixture of Active RC ,Gm-C used.

First stage Active RC for good linearity

Compensation capacitors not needed for

Gm-C since integrator capacitor can

compensate the OTA


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Sigma delta DAC

More tolerant to component mismatch and

circuit non-idealities

More digital

Keeping circuit noise low, and meeting

linearity are the challenges.


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Sigma Delta DAC

DigitalInput

Interpolation

Digital CodeConversion

0= 100000 =-1

1= 011111=+1

Digitalfiter

MSB

-VREF

-VREF

AnalogLow-passfilter

VREF

DAC

fN fS

fS =M.fN

fS

fS

Analog

Output


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How to combat Nonlinearity of

DAC? Capacitors/Resistors do have mismatch.

Randomize the mismatch.

In DWA, same set of DAC elements are used

cyclically and repeatedly under the guide of asingle pointer.

The element mismatch errors translate to tones atthe DAC output when the DAC input has aperiodic pattern.

DEM Logic must be optimized for low delay.

DEM


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DEM Flash output Thermometer code0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 =5

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 =9

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 =30 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 =12

-

+

C

C

C

C

Sixteen capacitors

1

2

15

16

x x x x X

x x x x x x x x x

x x x

x x x x x x x x x x x x


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General Guidelines


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General Guidelines

Stability (Overload)

Long strings of ones or zeroes are detected andreset is given to integrators to improve stability.

Stabilization techniques needed e.g. clamping ofintegrator outputs.

Extensive simulation needed e.g Matlab SigmaDelta Tool Box R.Schrier

Rules of Thumb

Maximum of Magnitude of H(z) shall be


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General Guidelines

Thumb rule GB of OA > 2.5FS

Switch resistances can be as low as 150 Ohms.

Offset of Comparator


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General Guidelines

OPamps with large dc gain in first stage.

Cancellation of even harmonics feasible by

fully differential circuits Top plates of capacitors to virtual grounds

of Opamps

Full switches parallel NMOS and PMOS forinput whereas only NMOS for those feedingvirtual ground.


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General Guidelines

Comparator metastability

Effect of clock jitter is independent of the

order or structure of the modulator. Clock A cos(ot) becomes due to jitter A

cos(o(t+Sin(t)).This adds to the inputand sidebands are formed: o+ , and o- )

of amplitude A o/2

SNR is affected by A2o2/2

Sigma Delta Frequency Synthesizer


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Sigma Delta Frequency Synthesizer

Frequencyreference

Multimodulusfrequency divider

VCOLoop FilterPhaseDetector

Sigma-DeltaModulator

PrecompensationFilter

GaussianFilter

DataSequence


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Conclusion

More than 400 papers IEEE press books

Simulation tools

Months of simulation may be needed toweed out problems.

Several solutions

Applications emerging for 802.11, BlueTooth, CDMA/GSM/3G handsets


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Contact

[email protected]

[email protected]


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Thank You

Documents

Introduction to Sigma Delta Converters