AN OVERVIEW OF SIGMA-DELTA CONVERTERS

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AN OVERVIEW OF SIGMA-DELTA CONVERTERS

G. S. VISWESWARAN

PROFESSOR

ELECTRICAL ENGINEERING DEPARTMENT

INDIAN INSTITUTE OF TECHNOLOGY, DELHI

NEW DELHI 110 016

Email: [email protected]

Telephone: (011) 2659 1077; (011) 2685 2525

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Signal bandwidth converted

Sigma Delta

Successive Approx

Subranging/Pipelined

Flash

DOMAIN OF CONVERTERS

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E[n] is a sample sequence of a random process uncorrelated with the sequence x[n].

The probability density of the error process is uniform over the range of quantization error i.e over /2

The error is a white noise process

PCM NYQUIST RATE A/D CONVERTERS

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The variance of the noise power for a quantization level is given by

2

N

2

N

22e

2

V2121

12

V2121

12S

)dB(N02.677.4V

Slog10

S

Slog10SNR

2

2x

2e

2x

This gives us an SNR


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In a Nyquist converter, the maximum signal to noise ratio that can be obtained for a sinusoidal input with a peak voltage of V is given by:

Every additional bit 6dB of SNR. eg. Digital audio with signal bandwidth = 20kHz. If desired resolution = 18 bits

SNR 110dB.

dB76.1N02.6SNR


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What is the problem with getting 18 bits of resolution ? 1. Nyquist rate converters essentially obtain output by comparing the input voltage to various reference levels. These reference levels are obtained by a process of reference division; using resistors or capacitors. Any mismatch in the resistors/capacitors results in loss of accuracy.2. For an ‘N’ bit converter, the required matching of elements is at least 1 part in 2N. Matching of components to > 10 bits (or > 0.1 %) is difficult.3. Nyquist rate converters require a sharp cutoff anti-aliasing filter.


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OVERSAMPLED PCM CONVERTERS

Oversampled converters attempt to use relatively imprecise analog components with additional digital signal processing circuits to achieve high resolution. This is done using

Oversampling - the sampling frequency is much higher than the signal frequency

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Noise spectrum when sampled at fS >> 2fB

Assume quantization noise is uniformly distributed, white and uncorrelated with the signal.

Noise power folds back to –fS/2 to fS/2, oversampled converters have lower noise power within the signal band.

Out of band noise can be removed by a digital filter following the PCM converter.


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We define Power Spectral Density of the output random Process is given by

2eeey

2xxxy )f(H)f(PPand)f(H)f(PP

For an oversampled PCM converter |Hx(f)| = |He(f)| = 1. White noise assumption states that Pe(f) = Se

2(f)/fs which implies Pey(f) = Sey2(f)/fs. Thus the in

band noise power is given by

S

B2e

f

0ey

f

fey

2ey f

f2Sdf)f(P2df)f(PS

BB

B


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We now see that the SNR ratio for this converter is

)dB(OSR02.3N02.677.4

V

Slog10

ff2S

Slog10

S

Slog10SNR

2

2x

SB2e

2x

2ey

2x

The spectrum of the (over) sampled signal can represented as follows:

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“16-bit resolution digital audio” Oversampled 8-bit converter to be used. To get an SNR = 110dB with fB = 20kHz, we need fS 2.64GHz.

This is still not good enough since the sampling frequency is too high. Further improvement can be obtained if noise shaping is used.


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We see that for an A/D converter the output is given in general by Y(z) = X(z)Hx(z) + E(z)He(z)

We have seen OS PCM converter using | Hx(z)| = | He(z)| = 1. We can however realize another converter using | Hx(z)| = 1 but choose He(z) to shape the noise spectrum to improve the noise performance. Noise shaping or modulation further attenuates noise in the signal band to other frequencies. The modulator output can be low pass filtered to attenuate the out of band noise and finally down sampled to get Nyquist rate samples.

NOISE SHAPED OVERSAMPLED

PCM CONVERTERS

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OVERSAMPLED NOISE SHAPING

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Noise is high pass filtered to get additional resolution

Simplest z- domain high pass filter: 1 –z-1 We want an output Y(z) that contains the sun of the input and quantzation noise that is high pass filtered. i.e.

Y(z) = X(z) + (1-z-1)E(z)

or

= z-1X(z) + (1- z-1)E(z)


PCM CONVERTERS

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1z1

1

Analog

Digital

One possibility is to first integrate the analog input, quantize it and then high pass filter it.


PCM CONVERTERS

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FIRST ORDER MODULATION

The naïve system proposed has its own problems. The first problem is that since it is an open loop system, the integrator will saturate. It also requires matching between analog and digital portions of the circuit.

)z(Ez1

z))z(Y)z(X()z(Y

)z(E)z(Xz1

zz1

z1)z(Y

)z(E)z(Xz1

zz1)z(Y

1

1

1

1

1

1

1

1

1

Y(z) = z-1X(z) + (1 – z-1) E(z)

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Linearized ‘z’ domain model gives

Hx(z) = STF = z-1

He(z) = NTF = 1-z-1

Assuming that the quantization noise is uncorrelated with the signal,

Sxy(f) = Sx(f)Hx(f) 2

Sey(f) = Se(f)He(f) 2


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If fB<< fS

2s

22

2

sey

f

f4

12f1

(f)S

Thus we obtain the Noise Power as

3

22

noise

f

feynoise

OSR

136

)( P

df)f(S PB

B


21

Taking OSR to be of the form 2r we can obtain the SNR as

)dB(r03.93

log10S

Slog10SNR

2

2e

2x

22


Noise power coming out of First Order Modulator for an OSR of 128.

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Before we proceed to implement the transfer function we need to look in to certain realizatios in the sampled data domain. As the word implies there is an integration involved. In the continuous domain, this requires resistance and capacitance.

As a designer we have the Capacity to Design but not the Resistance.


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SWITCHED CAPACITOR CIRCUITS

DOYEN OF SAMPLED DATA DESIGNS

Sampled Signals:

k

tj

skss

seT1

)kTt()t(x)t(x

This gives a z transform

k

kss z)kT(x)z(X

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Realizing resistors for Sampled Data Circuits

i2i1

The average value of current i1 or i2 is given by

)VV(CT1

dqT1

dtiT1

i 21

2/T

01

2/T

011

This emulates a resistance of value R = T/C = 1/fC

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OTHER REALIZATIONS OF R

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SWITCHED CAP INTEGRATORS

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During 1

)nT(V)2/TnT(V)2/TnT(V 11Cs

During 2

)nT(V)T)1n((V(C)nT(VC ooF1s

Using z transforms, this reduces to

111

1Fs

1

o z)z(H)z1(

z)C/C()z(H

)z(V)z(V


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If << 1/T, and using z = exp(jT) we get H(ejT) as

FF

sTj

RC1

j1

j1

TCC

)e(H

This circuit is then an integrator with a delay using the transformation s = (z-1)/T and is called the Forward Euler Integrator.


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This is another integrator that gives a non inverting integration at the output and uses the transformation s = (1-z-1)/T and is called the Backward Euler Integrator.


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The sampling capacitor Cs is now effectively Cs + CP, thus making the realized resistance R = T/(Cs + CP), different from the intended value --- needs correction, look for parasitic insensitive configuration.


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At 1 Cs gets charged to Vin(nT) and

During 2 )nT(V)T)1n((V(C))nT(V(C ooFins

Giving us

)z1(

z)C/C()z(H

)z(V)z(V

1

1Fs

1

o


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This configuration gives

)z1(

)C/C()z(H

)z(V)z(V

1Fs

1

o


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BACK TO SIGMA DELTA CONVERTERS

Implementation Imperfection in the first order sigma-delta modulator

Finite op-amp gain

Capacitance mismatch

Incomplete settling

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FINITE OPAMP GAIN

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FINITE OPAMP GAIN

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Using charge conservations at the nth clock cycle, we have:

CSVI[n]- CSVd[n] = CF [Vo[n]+ Vd[n] – Vo[n-1] - Vd[n-1]]]1n[V]n[V]n[V

CC

]1n[V]n[VCC

]n[V dddF

Soi

F

So

Using Vo[n] = Avd[n] and writing in z domain

A2

1

A1

1;

A2

1

1g,CCfor

z1

gz

CC

1A1

1

A1

11

CC

1A1

1

zCC

)z(Vin

)z(V

FS

1

1

z

F

SF

S

1

F

S

o

1

FINITE OPAMP GAIN

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Output of the modulator is now given by

))z(H1()z(E

)z(X)z(H1

)z(H)z(Y

1

1

1

1

z)g(1

z1NTFand

z)g(1

gzSTF

where NTF denotes the noise transfer function and STF denotes the signal transfer function,

NTF ‘0’ is shifted away from DC. Neglecting the effect of the pole in the NTF,

FINITE OPAMP GAIN

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sez f

fzNTF j

2,|1||| 212

= 1 +2-2 cos

For small

21cos

2

Noise power at the output is then

3

222

2

2f

f

2

s

2f

f

2

snoise

OSR

13

412

)1(12OSR

1

df12f

1df)1(

12f1

PB

B

B

B

FINITE OPAMP GAIN

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2

2

F

S

2

2

A

1

A2

1

A1

1CC

for

A2

1

A1

11)1(

3

22

2

2

3

222

2

noise

OSR

13

412A

112OSR

1

OSR

13

412

)1(12OSR

1P

FINITE OPAMP GAIN

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EFFECT OF FINITE BANDWIDTH

F

SF

uF

S

F

S

i

o

C

CCSCC

1A1

1

CC

VV

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)e1(CC

V)t(Vs1

CC

VV t

F

Sio

u

F

S

i

o u

Larger feedback factor lower gain faster setting

Settling determines maximum clock frequency

eg: CS = CF = 1pF = 0.5

Assume u = 100 MHz

If we want setting to 1% error, time required 14.6ns clock frequency = 34MHz.

EFFECT OF FINITE BANDWIDTH

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TIME DOMAIN BEHAVIOUR

Y[n] = Y [n-1] + (X[n-1] – V[n-1])

if Y[n] 0

Y[n] = 1.0

else Y[n] = - 1.0

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TIME DOMAIN BEHAVIOUR

For example, for a DC input = , the time domain output for the first six clock cycles is given by:

Y[n] V[n]

0 0.0

1 0.33 1

2 -0.33 -1

3 1 1

4 0.33 1

5 -0.33 -1

6 1 1

It can be seen that the average value of the output is 1/3

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TIME DOMAIN BEHAVIOUR (Non Linear)

Quantization error spectrum is not white; successive output levels may be correlated.

Limit cycle oscillations that lead to tones in the output

eg. DC input X[n] = x

For a limit cycle of period T;

V[n] = V[n+T]

Y[n] = Y[n+T]

Since the input is DC, the input to the integrator will also be periodic.

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TIME DOMAIN BEHAVIOUR (Non Linear)

Now Y[n] – Y[n-1] = X – V[n-1].

Write this equation for ‘T’ time instances and add; we get

T

1i

T

1i]1n[VX]0[Y]T[Y

but Y[T] = Y [0]

VT

NP]1n[V

T1

XT

1i

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PATTERN NOISE IN MODULATOR

It should be clear that the MODULATOR is expected to give out the output equal to the DC input. Only limited no. of levels are allowed to the output , therefore output has to toggle from one level to another in order to keep average output equal to the DC input.

For eg. Input=0.5 Levels allowed are 0 and 1

Then the output will toggle between 0 and 1. If average is taken then the value of output of SDM is 0.5.

Therefore the output is oscillating with a frequency half of that of fs. That means in frequency domain the output will have tones at fs/2 and fs.

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Similarly for dc level of 1/256, the output will have, one one and 255 zeroes in 256 clocks (fs) this means the output will oscillate at a frequency of (fs/256). Hence it will have tones lying at multiples of this frequency. As the dc level comes closer to zero the tonal frequency decreases. The tones are completely harmless till they are out of the signal bandwidth.

The thing to note over here is that these tones represent noise as the information or signal is at 0 frequency rest of the frequency components are noise. This effect is very much prominent in I order modulators. Another important fact is that the amplitudes of the tones decrease as they come closer to the signal bandwidth. It is always better to analyze them by using simulations.


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The question to be asked is why are this tones dangerous in the signal bandwidth? The answer to this question lies in the fact that all the analysis made earlier on was based on the white noise approximation and the problem with the tones is that they are much above the expected noise floor. Hence the true signal to noise ratio is much lesser than what was expected from the analysis.


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It’s generally said that the pattern noise is visible only for slow moving inputs (not just DC). To understand this more clearly assume the input signal is a sinusoid with an input frequency of fm. If fm is a factor of fs then every time a new period of the sine wave starts the SDM will generate the same output as it generated in the earlier period. This means the output will also be changing with a frequency of fm. Hence the output will have tones at the harmonics of the input sinusoidal signal. If fm is very small then some of these harmonics will lie in signal bandwidth and the SNR will be lesser than expected.


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Pattern Noise Reduces Effective Bits.

The frequency domain output of the SDM shows tones and a noise floor. Consider them this noise to be made of two components 1. Tones 2. Random noise. Therefore in time domain these tones will give rise to impulses (if a large number of tones exist in the signal bandwidth). Since there is random noise, the impulse train will have a slightly varying magnitude but the frequency of repetition will be equal to the fundamental frequency. When these impulses are of the order of 2 or 3 LSBs. This means ENOB is lesser then was expected.


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SECOND ORDER MODULATOR

The 2nd order modulator has one delaying and one non-delaying integrator. Note that the last loop with the quantizer must have one unit of delay for stability. The z-domain transfer function of the second order modulator is given by:

Y(z) = z-1X(z) +(1-z-1)2 E(z)

NTF = (1-z-1)2

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We can calculate the in band noise power of a second order modulator to obtain

542

noise OSR1

512P

Giving us a noise figure of

)dB(r05.155

log10S

Slog10SNR

4

2e

2x

55


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INTEGRATOR OVERLOAD

In second order modulator with a single delaying integrator, simulations show that the maximum outputs of the two integrators increase as the signal level increase. Very often, they are several times the full scale analog input range. The following table contains data from simulations. The output levels indicated are the maximum levels at the output of the two integrators.

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INTEGRATOR OVERLOAD

It is seen that the levels increase as the input value increases. This reduces the dynamic range of the modulation since the integrations will now saturate. The 2nd order modulator can be modified as follows:

Input level (dB)

Ist integrator output level

2nd integrator level

-40-20-13.9-10.45-7.95-6.02-4.43-3.09-1.9

0.330.960.991.091.221.331.371.491.43

2.622.772.83.033.513.994.085.385.21

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INTEGRATOR OVERLOAD

The linearized transfer function is

Y(z) = X (z) . z-2 + (1 – z-1)2E(z)

The signal levels at the output of the integrators are now the following

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INTEGRATOR OVERLOAD

The signal levels at the first integrator output is reduced. However the second integrator output levels are still high.

The SNR in the two cases remains the same.

The circuit specifications are now more relaxed since there are two units of delay in the loop.

Input level (dB)


2nd integrator level

-40-20-13.9-10.45-7.95-6.02-4.43-3.09-1.9

0.330.960.991.091.221.331.371.491.43

2.622.772.83.033.513.994.085.385.21

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INTEGRATOR OVERLOAD

We need to reduce the output levels in the second integrator. For this we need to alter the gain just before the second integrator. Let us see the effect of altering this gain.

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INTEGRATOR OVERLOAD

1

1

1

1

1

1

1

1

1

1

z)k1(1

)z1)(z(E

z)k1(1

kz)z(X)z(Y

z1

z)k1(1)z(Y)z(E

z1

kz)z(X

)z(Y)z(Ez1

kz)]z(Y)z(X[

Clock cycle

Output

2345678

11-1111-1

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INTEGRATOR OVERLOAD

Therefore, even though the linearized transfer function has changed, there is no change in the actual output. This is because we have a two level quantizer, the output of which depends only on the polarity and not the magnitude of the input. The quantizer effectively acts as an AGC and makes the overall gain 1.

The second integrator gain can be adjust to reduce the integrator output levels. Typically it is made less than one. For a gain of ½, the integrator output levels are the following

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INTEGRATOR OVERLOAD

Signal level (dB)


2nd integrator output level

-40-20-13.9-10.45-7.95-6.02-4.43-3.09-1.9

0.830.960.991.091.221.331.371.491.43

0.6550.690.70.750.870.991.021.341.3

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CIRCUIT NOISE

The sizes of the input capacitors should be chosen both on the basis of slow rate as well as thermal noise considerations. Thermal noise is basically introduced by non-zero resistance of the sampling switches.

The baseband component of this noise is approximately proportional to (kT/C)(1/OSR) where ‘C’ is the sampling capacitor. If the OSR = 256, C = 1pF , the noise power will be 1.625 x 10-11 Joules. The total quantization noise power in baseband at this OSR, with quantizer levels = 1 is 5.9 x 10-12

Joules. Choose larger capacitance.

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SAMPLING JITTER

Sampling Clock Jitter results in non uniform sampling, increasing total noise power in the quantizer output.

For a sinusoidal input with amplitude A and frequency fx

)tf2cos(A.f2.dtdX

.)t(X)t(X

xx

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SAMPLING JITTER

Since this is assumed to be white, the total error power in baseband is

OSR)f2(

8P

2x

2

2x

2)f2(

2A

P

If the jitter is assumed to be an uncorrelated Gaussain random process (‘white’), with standard deviation t, the average power of this error signal is

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IMPLEMENTATION IMPERFECTIONS

Supposing the two integrators have the following transfer functions

12

12

11

1

z1

zgand

z1

g

2221

121221

12

11

2221

121221

121

12

12

11

1

z)ga(z)ggga(1

)z1)(z1(NTF&

z)ga(z)ggga(1

zggSTF

)z(Y)z(Ez1

zgY

z1

g))z(Y)z(X(

68


Assume A1=A2 (the two opamp have the gain). Generally we can neglect the effect of the denominator and obtain NTF = (1 – z-1)2

22224sez

412

)1(2)1(

ff2

,||z1||NTF| j

(1-)4 is the unshaped noise, 2(1-)2 2 is the 1st order shaped noise and 2 4 is the 2nd order shaped noise.

To make sure we get second shaped, we need A OSR.

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Attenuation

Maximum Integrator

Output levels

SNR (OSR = 256) Input =

-20dB

0.9 5.98, 9.9 70

0.8 3.56, 4.26 83.15

0.7 2.05, 1.86 84.73

0.6 1.29, 0.9 83.59

0.5 0.962, 0.693 86.69

0.4 0.693, 0.625 86.71

0.3 0.510, 0.589 85.93

0.2 0.34, 0.562 77.45

AD Converter

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SIGNAL OUTPUTS OF MODULATOR

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D/A CONVERTER

The sigma Delta D/A converter has a similar topology to the A/D converter. Here the input digital signal first goes through an interpolation filter, where it is upsampled and low pass filtered. After this it is fed to the modulator. The output of the modulator is a single bit signal, that comes at rate much higher than the Nyquist rate. The output of the modulator is ample and held and low pass filtered to give the analog output.

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D/A CONVERTER

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D/A CONVERTER

The input to the modulator is a 12 bit signal that is upsampled. The clock rate is much higher than the Nyquist rate. The modulator is a second order modulator and the topology is the same as the A/D converter. All numbers are in the 2’s complement form. A one bit quantizer in this case, would simple keep the MSB and throw out all the other bits. The D/D converter converts the one bit quantized output to 14 bit positive or negative number as shown.

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AN OVERVIEW OF SIGMA-DELTA CONVERTERS