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7/28/2019 Ch 8 Delta-Sigma ADCs With Multibit Internal Converters

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Richard L. CarleyRichard SchreierGabor C. Ternes

8.1 INTRODUCTION

Chapter 8DeltaSigma ADCswith Multibit InternalConverters

One-bit noise-shaping modulators have achieved popularity for use in integrated circuitdata converters [14]. In part, their attractiveness for IC systems that incorporate digitalfiltering and signal processing with analog-to-digital and/or digital-to-analog conversionis due to the fact that they employ a l -bi t internal DAC that does not require precisioncomponent matching. Delta-sigma modulators can be implemented using a standard digital CMOS process without the economically costly addition of precision thin-film resistors or the use of laser trimming. However, as was shown in Chapter 4, the resolution thata I-bit L1L modulator can achieve at a given oversampling ratio is limited. Although theachievable resolution does improve with increasing loop filter order, these improvementsdiminish rapidly due to instability. In addition, because of the substantial out-of-bandquantization noise power in L1L modulators, the design of analog output filters for oversampled DACs can be quite difficult [5]. One solution to the above problems is to use amultibit quantizer in the oversampled converter loop.

The primary advantage of noise-shaping modulators employing multibit quantizers isthat the ratio of the total quantization noise power to the signal power at the modulator's output is dramatically reduced from that of a I-bit modulator; typically by 6 dB per additionalbit. Therefore, we can increase the overall resolution of any oversampled data converter,without increasing the oversampling ratio, simply by increasing the number of levels in theinternal data converters. Equivalently, the multibit noise-shaping coder can achieve resolution comparable to that of a single-bit modulator at a lower sample rate. For example, theprototype noise-shaping DAC presented in [6], which operated at 3.2 MHz and employeda 3-bit internal quantizer, achieved performance comparable to that of the dL modulator pre-

244

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Multibit Noise-Shaping Modulator Architectures 245sented in [2], which operated at 11.3MHz and employed a I-bit internal quantizer. This performance increase can be a significant advantage in applications requiring high bandwidth;for example, digitizing video signals. Another advantage of the lower clock rate possiblewith multibit modulators is the decreased power consumption in the digital circuitry [7].The same decrease in the quantization noise power that improves resolution alsorelaxes the requirements on the output filter that must remove the out-of-band quantization noise power. The use of a multibit internal quantizer in the oversampled feedbackloop also facilitates the design of feedback loops with high-order transfer functionsbecause the low-frequency oscillations sometimes observed in higher order ~ L modulators [81 0] are a result of the I-bit quantizer being overloaded [10, 11]. As Chapter 14will explain in detail, a quantizer can be made overload free, for a given modulator andinput magnitude, if it has enough levels. Assuming that quantizer overload does not occur,the design of multibit noise-shaping loops is quite simple compared to the design of l-bit~ L modulators, This simplicity is realized because the gain of the quantizer is known(1 LSB per digital level), because the quantization error is bounded between +! LSB and-!LSB and because the quantization error can be accurately modeled as an additive noisethat is independent of the input signal [12-14].Nonlinear numerical techniques have beenapplied to optimize the conversion system's performance for a given internal DACthrough the choice of the loop filter pole and zero locations [12, 13].

A notable disadvantage of multibit systems is that they lack the ability of single-bitsystems to achieve excellent integral linearity without the use of matched components.The integral linearity of a noise-shaping conversion system is no better than the integrallinearity of the multibit internal DAC [1,7,15]. Therefore, achieving high integral linearity and low total harmonic distortion (fHD) appears to require precisely matched components. As the smallest component mismatch that can be achieved is on the order of 0.1-0.5% in the inexpensive CMOS IC fabrication technologies normally employed for consumer electronics [16-18], the harmonics created by multibit modulators can approach-60 dB relative to a full-scale fundamental. A secondary disadvantage of multibit modulators is that more analog circuitry, which is generally more difficult to design than digitalcircuitry, is required.

In this chapter we consider a number of alternative approaches to achieving highintegral linearity while requiring only modest component matching-at a level substantially lower than the required integral linearity. The approaches that will be considered runthe gamut from circuit techniques for electronic trimming of element values to digitalcharacterization and correction of element mismatches to interconnections of multiplemodulator loops that achieve multibit performance.

8.2 MULTIBITNOISESHAPING MODULATOR ARCHITECTURESNoise-shaping modulators employing multibit internal quantizers can be used for bothADCs and DACs (see Figure 8.1).

In the case of an ADC system, the quantizer is a true ADC in its own right and iscommonly implemented with a bank of comparators. In the case of a DAC system, thequantizer merely corresponds to a truncation of the digital word at the output of the accumulator. In both systems, a multibit DAC is necessary. As shown in Figure 8.1, the DAC

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246 8 Delta-SigmaADCs with Multibit Internal Converters

Analoginput DigitaloutputLN

(a)

Digital!z.input fs

Analogoutput(b)

Figure 8.1 Oversampled multibit (a) ADC and (b) DAC block diagrams.is inside the feedback loop for a multibit ADC system, whereas for a multibit DAC systemthe DAC is outside the feedback loop. In order to reduce system complexity, there aregenerally only a few quantizer and DAC levels: 4-16 levels (2-4 bits) are typical.

A notable limitation of multibit systems is that the property of perfect linearity characteristic of single-bit systems is lost. We can model the nonlinearities in an ADC systemas additive noise sources, as shown in Figure 8.2. The quantizer is replaced by two additive noise sources. The one labeled e(n) represents the quantization errors of an ideal converter while c(n) represents the errors caused by the deviation of the comparator switchingthresholds from their ideal values. Similarly, d(n) represents the errors due to the deviation of the internal DAC outputs from their ideal values. For noise shaping to occur, thegain of L(z) must be large at low frequencies. Therefore, both quantization errors c(n) ande(n) are reduced by this large gain when referred back to the input u(n). However, thenonlinearity of the internal DAC, den), resides in the feedback path where its nonlinearities due to mismatches in levels are not reduced by the negative feedback. Similarly, DACsystems have an M-bit DAC sitting outside of the noise-shaping loop where its nonlinearities clearly are not mitigated by negative feedback. Thus, the ultimate linearity of both

u(n

d(n)

v(n)

Figure 8.2 Simplified block diagram of an oversampled ADC system withsources indicating the quantization error, internal ADC nonlinearity, and internal DAC nonlinearity.

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DAC Architectures for Improved Linearity 247ADC and DAC systems is no better than the linearity of the N-bit internal DAC. Forexample, 16-bit linearity in an oversampled DAC system can only be achieved if the internal DAC has its levels placed with an accuracy better than 1 part in 100,000. Although thisdegree of matching can be obtained by careful trimming after fabrication [19,20] (e.g., bylaser trimming of resistors), architectural changes and circuit design techniques [21, 22,23] that avoid the need for this high degree of matching may result in substantially lowermanufacturing costs. Because it is the internal DAC that controls the performance, we willconcentrate on its design and ignore the design of the internal multibit ADC, which is usually implemented as a parallel bank of comparators (i.e., as a flash ADC [20]).

8.3 DAC ARCHITECTURES FOR IMPROVED LINEARITYIn this section, we consider the design of the internal DAC for multibit systems. First,the most common architecture for internal DACs will be described and its overall accu

racy will be derived. Then, various approaches for improving the overall accuracy of theinternal DACs will be described.8.3.1 Internal DAC Topology

Although there are a great variety of circuit topologies that can be used to implementa DAC [20], one common architecture [1,6, 24, 25J employs 2N parallel unit elements ofapproximately equal value, where N is the number of bits (see Figure 8.3). Note that an N-bit parallel-unit-element DAC can actually be implemented using only 2N 1 elementssince the possible digital output levels range from 0 elements being active up to 2N 1elements being active. However, because it simplifies the analysis, we will add one extraunit element to bring the number of elements in an N-bit parallel-unit-element DAC up to2N . in a parallel-unit-element DAC, the Kth output level is generated by activating Kapproximately equal-valued elements (typically resistors, transistor current sources, orcapacitors) and summing up their charges or currents. The novel characteristic of the internal DAC