CALIBRATION TECHNIQUESIN NYQUISTA/D CONVERTERS

Hendrik van der Ploeg and Bram Nauta

Hendrik van derPloeg and Bram Nauta

CALIBRATION TECHNIQUES INNYQUISTA/D CONVERTERS

CALIBRATION TECHNIQUES IN NYQUIST A /D CONVERTERS

THE INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University

Related Titles: WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS

Doris,Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: 0-387-30415-0

METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES

Pastre, Marc, Kayal, Maher Vol. 870, ISBN: 1-4020-4252-3

HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: 0-387-28591-1

LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: 1-4020-4139-X

DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifänio da Franca, José Vol. 867, ISBN: 0-387-26121-4

DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José(Eds.) Vol. 860, ISBN: 0-387-25902-3

ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: 0-387-25746-2

DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC’S Claes and Sansen Vol. 854, ISBN: 1-4020-3208-0

MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: 0-387-24314-3

LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and steyaert Vol. 843, ISBN: 1-4020-3190-4

SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN: 1-4020-3173-4

LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION Van der Meer, van Staveren, van Roermund Vol. 841, ISBN: 1-4020-2848-2

WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE CANCELLATION Bruccoleri, Klumperink, Nauta Vol. 840, ISBN: 1-4020-3187-4

CMOS PLL SYSTHESIZERS: ANALYSIS AND DESIGN Shu, Keliu, Sánchez-Sinencio, Edgar Vol. 783, ISBN: 0-387-23668-6

SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS Bajdechi and Huijsing Vol. 768, ISBN: 1-4020-7945-1

OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENT Ivanov and Filanovsky Vol. 763, ISBN: 1-4020-7772-6

STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEED D/A CONVERTERS Van den Bosch, Steyaert and Sansen Vol. 761, ISBN: 1-4020-7761-0

DESIGN AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR Xdsl Piessens and Steyaert Vol. 759, ISBN: 1-4020-7727-0

LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS Silveira and Flandre Vol. 758, ISBN: 1-4020-7719-X

MIXED-SIGNAL LAYOUT GENERATION CONCEPTS Lin, van Roermund, Leenaerts Vol. 751, ISBN: 1-4020-7598-7

and

Philips Research, Eindhoven, The Netherlands

University of Twente, Enschede, The Netherlands

Hendrik van der Ploeg

By

Bram Nauta

CALIBRATION TECHNIQUES IN NYQUIST

A/D CONVERTERS

A C.I.P. Catalogue record for this book is available from the Library of Congress.

Published by Springer,P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

Printed on acid-free paper

All Rights Reserved

No part of this work may be reproduced, stored in a retrieval system, or transmittedin any form or by any means, electronic, mechanical, photocopying, microfilming, recording

or otherwise, without written permission from the Publisher, with the exceptionof any material supplied specifically for the purpose of being entered

and executed on a computer system, for exclusive use by the purchaser of the work.

Printed in the Netherlands

© 2006 Springer

www.springer.com

ISBN-10 1-4020-4634-0 (HB)ISBN-13 978-1-4020-4634-6 (HB)ISBN-10 1-4020-4635-9 (e-book)ISBN-13 978-1-4020-4635-9 (e-book)

Aan Ria en mijn ouders

Table of contents

List of abbreviations

List of symbols

Preface

1 Introduction 11.1 A/D conversion systems . . . . . . . . . . . . . . . . . . . . . . 11.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 51.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Accuracy, speed and power relation 72.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8

2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 82.2.22.2.3 Matching versus noise requirements . . . . . . . . . . . . 11

2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4 Maximum speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.5 . . . . . . . . . . . . . . . . . . . . . 152.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 A/D converter architecture comparison 213.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 Full flash . . . . . . . . . . . . . . . . . . . . . . . . . . 233.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 263.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 333.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10

CMOS technology trends

xi

xiii

xvii

Table of contents

3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 543.7 Theoretical power consumption comparison . . . . . . . . . . . . 56

3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 573.7.2 Architecture comparison as a function of the resolution . . 573.7.3 Architecture comparison as a function of the sampling speed 65

3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4 Enhancement techniques for two-step A/D converters 674.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.2 Error sources in a two-step architecture . . . . . . . . . . . . . . 674.3 Residue gain in two-step A/D converters . . . . . . . . . . . . . . 69

4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 694.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 714.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 754.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 754.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 754.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 834.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 834.5.2 Offset extraction from digital output . . . . . . . . . . . . 844.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 884.5.4 Offset extraction and analog compensation . . . . . . . . 914.5.5 Offset extraction in a dual-residue two-step converter . . . 934.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102

5 A 10-bit two-step ADC with analog online calibration 1035.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.2

5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 1065.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 1075.2.3 Coarse and fine A/D converter references . . . . . . . . . 1085.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109

5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 1115.3.2 Coarse A/D, D/A converter and subtractor . . . . . . . . . 1115.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 1125.3.4 Offset compensated residue amplifier . . . . . . . . . . . 1135.3.5 Fine A/D converter . . . . . . . . . . . . . . . . . . . . . 1145.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

viii

Two-Step architecture . . . . . . . . . . . . . . . . . . . . . . . 105

Table of contents

5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 1175.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6 A 12-bit two-step ADC with mixed-signal chopping and calibration 1236.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236.2 Two-step architecture . . . . . . . . . . . . . . . . . . . . . . . . 126

6.2.1 Interleaved sample-and-hold . . . . . . . . . . . . . . . . 1276.2.2 Coarse A/D converter . . . . . . . . . . . . . . . . . . . . 1286.2.3 Switching and residue signal generation . . . . . . . . . . 1296.2.4 Residue amplifiers . . . . . . . . . . . . . . . . . . . . . 132

6.3 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 1336.3.1 Residue amplifier offset . . . . . . . . . . . . . . . . . . 1346.3.2 Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . 1346.3.3 Digital extraction . . . . . . . . . . . . . . . . . . . . . . 135

6.4 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366.4.1 Interleaved sample-and-hold . . . . . . . . . . . . . . . . 1366.4.2 Coarse A/D converter . . . . . . . . . . . . . . . . . . . . 1376.4.3 Residue amplifier with offset compensating current D/A

converter . . . . . . . . . . . . . . . . . . . . . . . . . . 1386.4.4 Folding-and-interpolating fine A/D converter . . . . . . . 139

6.5 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 1416.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7 A low-power 16-bit three-step ADC for imaging applications 1497.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497.2 Three-step architecture . . . . . . . . . . . . . . . . . . . . . . . 151

7.2.1 Sample-and-hold . . . . . . . . . . . . . . . . . . . . . . 1537.2.2 Resolution distribution . . . . . . . . . . . . . . . . . . . 1547.2.3 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.3 Noise considerations . . . . . . . . . . . . . . . . . . . . . . . . 1567.4 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 158

7.4.1 Mid and fine residue amplifier stage calibration . . . . . . 1587.4.2 Quick calibration . . . . . . . . . . . . . . . . . . . . . . 160

7.5 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 1627.7 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

ix

Table of contents

8 Conclusions 169

A Static and dynamic accuracy requirements 173A.1 Static error requirments . . . . . . . . . . . . . . . . . . . . . . . 173A.2 Dynamic error requirements . . . . . . . . . . . . . . . . . . . . 175

References 177

Index 189

x

List of abbreviations

A/D analog-to-digitalADC analog-to-digital converterAMP amplifierATV analog televisionCCD charge-coupled deviceCDS correlated double samplingCMOS complementary metal oxide semiconductorCVBS composite video baseband signalD/A digital-to-analogDAC digital-to-analog converterDC direct currentDNL differential non-linearityDSP digital signal processorDTV digital televisionEDGE enhanced data rates for GSM evolutionENOB effective-number-of-bitsEPROM electrically-programmable read-only memoryERBW effective resolution bandwidthGSM global system for mobile communicationIC integrated circuitINL integral non-linearityINT integratorLSB least-significant-bitMSB most-significant-bitMSCC mixed-signal chopping and calibrationOPAMP operational amplifierOR over-rangePCB printed circuit boardPROM programmable read-only memory

xi

List of abbreviations

RAM random-access memoryRF radio frequencyROM read-only memorySAR successive approximationSFDR spurious free dynamic rangeS/H sample-and-holdSHA sample-and-hold amplifierSINAD signal-to-noise and distortionSiP system-in-packageSNR signal-to-noise ratioSoC system-on-a-chipSUB subrangeT/H track-and-holdTHA track-and-hold amplifierTHD total harmonic distortionUR under-rangeVGA variable gain amplifierXOR exclusive orYUV luminance and chrominance signals

xii

List of symbols

a ratio between fin, fs and fc -A gain factor -AC capacitor mismatch process parameter

√C

Afa folding amplifier gain -AVT

threshold mismatch process parameter mVµmAβ current factor mismatch process parameter %µmC symbol for capacitance FCgs gate-source capacitance FCintr minimum required capacitance FCLOAD load capacitance FCmatching capacitance resulting from matching requirement FCminimum minimum required capacitance FCnoise capacitance resulting from noise requirement FCox oxide capacitance per unit area F/m2

Cp parasitic capacitance FCx F

DRpp peak-to-peak signal to rms noise dBENOB, DC effective-number-of-bits at DC -f−3dB 3 dB frequency HzFf folding factor -Fint interpolation factor -FoM figure-of-merit pJFoMVpp figure-of-merit normalized to 1 Vpp V2pJfc chop signal frequency HzfENOB,DC−0.5 frequency with 0.5 ENOB loss in ENOB w.r.t.

ENOB, DCHz

fin input signal frequency Hzfs sample frequency Hz

requirementscapacitance determined by noise or matching

−

xiii

□

□

List of symbols

gm transconductance A/VGR gain ratio -Ids drain-source current Ak Boltzmann’s constant, 1.3805·10−23 J/KK circuit implementation factor V2

L channel length of a MOS transistor µmM(n) integrator content at sample n -mult circuit multiplication factor -N number of bits -NC number of coarse bits -NEF noise excess factor -NF number of fine bits -Nint number of interpolation stages -Nlinear number of pre-amplifier stages in linear region -Npeak number of chopping frequencies -Npreamps number of pre-amplifiers -offset red offset reduction -#ORC number of over-range comparators -p number of out-of-range pre-amplifiers -P power WPnoise,tot total integrated noise power WPnoise,tot,circuit total integrated noise power of a circuit WPnoise,tot,MOS total integrated noise power of a MOS transistor WPx W

R symbol for resistance �

s (effective) oxide scaling factor -Sv2 spectral noise power density V2/HzT temperature Ktox (effective) oxide thickness mts settle time sts,min minimum sample period sVamp,choppeak amplitude at chop frequency VVdd supply voltage VVfull scale full scale input signal VVgs gate-source voltage VVgt gate overdrive voltage VVLSB LSB voltage VVnoise,rms rms value of the noise voltage V

requirementspower determined by noise or matching

xiv

List of symbols

Voffset offset voltage VVpp peak-to-peak voltage VVrms rms value of the voltage VVshift,n nth reference voltage VVsignal,rms rms value of the signal voltage VVT threshold voltage VW channel width of a MOS transistor µmx ratio between coarse comparator and residue

amplifier offset-

xNF normalizing factor for equal data rate -β current factor µA/V2

�C error in the capacitance Fε settling error -εcoarse quantization coarse quantization error -εfine quantization fine quantization error -εfine range fine range error -εgain gain error -εoffset offset error -εreference reference error -εsubtraction subtraction error -γ white noise factor -µn,p mobility of electrons, holes cm2/Vsπ pi, 3.141593 -σ standard deviation -σC spread of the capacitance FσVoffset spread of the offset voltage Vτ time constant sτmin minimum achievable time constant sτunit time constant of one buffer unit s

xv

□

Preface

The advances in Integrated Circuits brought us advanced electronic systems avail-able for large groups of people. By putting more and more functionality on an in-tegrated circuit (IC) these systems could become cheap in mass production. Many

Today, most electronic systems process signals in digital format. This way low-cost accurate circuits with a very high density can be made. The signals in the

It is beneficial to integrate these A/D and D/Aconverters in the same IC as the digital functions for cost and size reasons. Sincethe digital ICs are generally implemented in CMOS technology, this requires A/Dand D/A converters in CMOS as well, which poses quite some challenges in thedesign since CMOS technology is optimized for digital circuits.

Analog-to-digital converters can roughly be split in two families. The first fam-ily is the one of the high accuracy and low speed converters, often referred to asoversampled converters, typically used for audio and low MHz range. In theseconverters the speed of the technology is exploited to relax the accuracy demandsof the analog circuits. The second family is the one of the high speed, mediumaccuracy converters, also referred to as Nyquist converters. Here oversamplingcannot be used and the accuracy has to come from the analog circuits itself. Ac-curacy is generally achieved by relying on matching of equally designed on-chipcomponents, which works better for larger-size components on a chip. However iflarge components have to work at high speed, this requires high power dissipation.So these converters generally have a trade-off in power, speed and accuracy.

This book deals with Nyquist-type converters. The basic idea exploited here is touse the available digital processing power of the CMOS technology to calibratecritical analog parts of the A/D converter. This way the analog accuracy demandsof the components can be relaxed and smaller sized-components can be used, res-ulting in a reduction in power consumption. This book starts with an introductionin the field, exploring the power, accuracy and speed space. The conclusion is thattwo-step converters form a good base for investigating the calibration techniques.

researchers work on the advances in integration of complex systems.

to-analog converters are required.real world however are all analog, and therefore analog-to-digital and digital-

xvii

Preface

In the remaining chapters several calibration algorithms are described, and severalIC realizations of calibrated two-step converters are presented.

The book was originally the PhD thesis of Hendrik van der Ploeg who wrote itafter 9 years of experience in A/D converter design at Philips Research laborat-ories. I really enjoyed working with Hendrik to prepare his thesis and now I feelvery happy that it has been published as a book. I believe this book is really worthreading for a broad group of scientists and engineers.

Bram Nauta,Professor,University of Twente,The Netherlands

Enschede, January 2006

xviii

Chapter 1

Introduction

1.1 A/D conversion systems

In modern systems, most of the signal processing is performed in the digital do-main. Digital circuits have a lower sensitivity to noise and are less susceptibleto fluctuations in supply and process variations. Unlike with analog circuits, sig-nal processing in the digital domain offers greater programmability, error correc-tion and storage possibilities. Since the world around us is analog and humans

They are found inmany systems that require digital signal processing. This book focuses on A/Dconverters. A/D converters can be classified into two groups. There are A/D con-verters with a high accuracy and a low sample rate and A/D converters with a lowaccuracy and a high sample rate. This is illustrated in figure 1.1.

The first group includes sigma-delta converters for audio, signal transmissionand instrumentation systems, while the second group includes video, camera andwide-band signal transmission systems. In order to increase the accuracy or thespeed specifications of the A/D converters in both groups more power is required.The A/D converters from the second group of converters are dealt with in thisbook. They are found in products like television sets, security cameras, medicalimaging devices, instrumentation, etc. The sampling speed required for these ap-plications is generally in excess of 25 MSample/s and the resolution is 10 bits ormore. A few examples of these applications are shown in figure 1.2.

The position of the A/D converter in such systems is shown in figure 1.3. In thisfigure, the signal is conditioned in the analog domain before it is applied to theA/D converter.

1

to-analog (D/A) converters represent important building blocks.perceive information in the analog form, analog-to-digital (A/D) and digital-

2

sample rate [MSps]

resolution [bits]

morepower

lesspower

this work

high resolution,low frequency

low resolution,high frequency

Figure 1.1: High accuracy, low speed A/D converters and low accuracy,high speed A/D converters and the position of this work

Figure 1.2: Systems with A/D converters with sampling speeds in excessof 25 MSample/s and a resolution of 10 bits or more

log world and the digital signal processing and digital memory. For example, theA/D converter converts the down-converted radio frequency (RF) antenna signalto the digital domain. In the case of figure 1.3, the filtering and channel selectionis performed in the analog domain. Another example is an analog video signalwith an aspect ratio of 4:3, which is converted to the digital domain. In the di-gital domain a field memory and additional processing is used to resize the videosignal to an aspect ratio of 16:9. A D/A converter converts this signal back to theanalog domain to be applied to a display [1]. Similar signal processing is required

As shown in figure 1.3, the A/D converters form the connection between the ana-

Introduction

3

MobileCable

ATV/DTV

Communicationpipe

AD

C/D

AC

Sensorpipe

AD

C Storagepipe

AD

C/D

AC

Outputprocessing

DA

C

DigitalProcessing(hardware/software)

Powermanagement

ImageUltrasound

X-ray

OpticalHarddrive

DisplaySound

communication

Power

Figure 1.3: The position of the A/D converter in the system, with signalconditioning in the analog domain

to convert a video signal with a 50 Hz frame rate to a video signal with a 100 Hzframe rate.

The performance level should be such that the system is not affected by the imper-fections of the data converter. Its design is therefore extremely important. Becauseof the trend towards decreasing feature sizes on silicon, it is becoming cheaper toshift analog functions, such as amplifying, filtering and mixing, into the digitaldomain. This involves shifting the A/D converter towards the input of the system;an extreme example of this is shown in figure 1.4.

MobileCable

ATV/DTV

Communicationpipe

AD

C/D

AC

Sensorpipe

AD

C Storagepipe

AD

C/D

AC

Outputprocessing

DA

C

DigitalProcessing(hardware/software)

Powermanagement

ImageUltrasound

X-ray

OpticalHarddrive

DisplaySound

communication

Power

Figure 1.4: The A/D converter shifted towards the input of the system

In order to shift the A/D converter towards the input of such systems, A/D convert-ers are required with a greater dynamic range and higher sampling speeds becausethere is less analog signal conditioning. This makes even higher demands on theA/D converter and potentially increases the power consumption. The calibrationtechniques investigated in this book enables to increase the accuracy without in-creasing the power consumption of the A/D converter.

1.1 A/D conversion systems

4

If the specifications are known from the application, the challenges in the design ofA/D converters arise from the technology used. The application generally determ-ines the integrated circuit (IC) technology, which is mainly a cost-driven choice.Due to the high level of integration of systems on a chip, the digital functional-ity and therefore the area occupied by digital circuitry becomes dominant. Thismeans a technology has to be chosen that is optimized for digital circuitry. In thiscase the technology is optimized for high-density digital circuits, which allows theuse of small feature sizes that achieve a high packing density. The parameters ofthis technology are typically optimized for the digital circuitry and are thereforeless suitable for high-performance analog circuits. On the other hand, there aretechnologies that are better suited for the design of dedicated high-performanceanalog circuits. Although the stand-alone analog circuits can achieve a high per-formance, these components have to be integrated into the overall system at ahigher, system-in- package (SiP) level. This is in contradiction with the increas-ingly higher level of integration of systems-on-a-chip (SoC). However, the useof multi-die packages as shown in figure 1.5 also offers advantages because thedigital circuitry can be designed on a digital chip, in a dedicated digital comple-mentary metal oxide semiconductor (CMOS) technology, whilst the analog cir-cuits are designed in a dedicated analog technology. This allows fast scaling ofthe digital part whilst the analog performance with the analog chip is maintainedand digital cross-talk is prevented.

Figure 1.5: System-in-package (from [2]) with analog TV processor anda digital signal processor

Introduction