Digital Analog Converters

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Characterization of Digital ± Analog Converters

A DAC with a voltage output can be characterized by the block diagram in Figure. 1.2(a). We see that it consists of a digital wordof N-bits (b 0, b1, b2, «..b N-2 , b N-1 ) and a reference voltage V REF. b 0

is called the most significant bit, MSB, and b N-1 is called the leastsignificant bit., LSB. The voltage output vOU T can be expressed as

D KV v REF OUT ! (1.1)

where K is a scaling factor the digital word D is given as

N N

bbbb D

2...

2221

32

21

10! (1.2)



N is the total number of bits of the digital word and b i-1 is the ith-bitcoefficient is either 0 or 1. Therefore, the output of a DAC can beexpressed by combining Eqs. (1.1) and (1.2) to get

¹ º ¸©

ª¨!! N

N REF OUT

bbbb KV v

2...

2221

32

21

10 (1.3)

or

? A N

N REF OUT bbbb KV v ! 2...222

1

3

2

2

1

1

0

(1.4)



Figure 1.1 Digital-analog converter in signal-processingapplications.



Figure 1.2 (a) Digital-analog converter in signal-processingapplications. (b) Clocked digital-analog converter for synchronousoperation. (The asterisk represents a signal that has been sampled

and held.)



I n many cases the digital word is synchronously clocked. I n this

case latches must be used to hold the word for conversion and asample-and-hold circuit is needed at the output, as shown inFigure. 1.2(b).

The basic form of a DAC providing an analog output voltage isshown in more detail in Figure. 1.3. I t includes binary switches, ascaling network, and an output amplifier. The scaling network and binary switches operate on the reference voltage to create avoltage that has been scaled by the digital word. The scalingmechanism may be voltage, current, or charge scaling. The outputamplifier the scaled voltage signal to a desired level and providesthe ability to source or sink current into a load.



Static Characteristics of DACs

The resolution of the DAC is equal to the number of bits in theapplied digital input word. The resolution of a DAC is expressedas N-bits, where N is the number of bits. Figure 1.4 shows theinput and output characteristics of an ideal 3-bit DAC (N = 3). We

see that each of the eight possible digital words has its own uniqueanalog output voltage. These levels are separated by an LSB. Thevalue of the LSB can be defined as

N

REF V

LSB 2! (1.5)



As the digital word increases by 1-bit, the output of the ideal DACshould jump up by 1LSB. We note that the output is 0.0625 V for

the digital input of 000. However, there is no reason why thecharacteristic cannot be shifted downward by a half LSB as shown by the dashed characteristic, which corresponds to 0 V for thedigital input of 000.

Figure 1.3 Block diagram of a digital-analog converter.



Figure 1.4. I deal input-output characteristics of a 3-bit DAC.



Because the resolution of the DAC is finite (3 in the case of Figure.1.4), the maximum analog output voltage does not equal V REF. This

result is characterized by the full scale (FS) value of the DAC. Thefull scale value is defined as the difference between the analogoutput for the largest digital word (1111 «) and the analog outputfor the smallest digital word (0000«). I n general, the full scale of aDAC can be expressed as

Full scale ¹ º ¸©

ª¨!!

N REF REF V LSBV FS 21

1 (1.6)

This definition of FS holds regardless of whether the characteristic

has been shifted vertically by s 0.5LSB. I n the case of Figure. 1.4,FS is equal to 0.875V REF. The full scale range (FSR) is defined as

REF N V FS FSR !!

p

limE (1.7)



Based on the above discussion, let us define several important

quantities that are important for DACs. The first is calledquantization noise. Quantization noise is the inherent uncertaintyin digitizing an analog value with a finite resolution converter. Tounderstand this definition, the characteristic for an infiniteresolution DAC is plotted on Figure. 1.4. This line represents thelimit of the finite DAC characteristic as the number of bits, N,approaches infinity. The quantization noise (or error) is equal tothe analog output of the infinite-bit DAC minus the analog outputof the finite-bit DAC. I f we plot the quantization noise of either of

the 3-bit characteristics in Figure. 1.4, we obtain the result shownin Figure. 1.5. The solid and dashed lines correspond to the solidand dashed staircases, respectively, in Figure. 1.4.



Figure 1.5 Quantization noise for the 3-bit DAC of Figure. 1.4.



We see from Figure. 1.5 that the quantization noise is a sawtoothwaveform having a peak-to-peak value of 1LSB. I t is useful to note

that 0.5LSB is equivalent to FSR/2 N+1

. This noise is a fundamental property of DACs and represents the limit of accuracy of theconverter. For example, it is sufficient to reduce the inaccuracies of the DAC to within s 0.5LSB. Any further decrease is masked by thequantization noise that can only be reduced by increasing theresolution.

The dynamic range (DR) of a DAC is the ratio of the FSR to thesmallest difference that can be resolved (i.e., an LSB). We can

express the dynamic range of the DAC as

N

N FSR

FSR

LSB

FSR DR 2

2/!!! (1.8)



I n terms of decibels, Eq. (1.8) can be expressed as

N d B DR 02.6! dB (1.9)

The signal-to-noise ratio (SNR) for the DAC is defined as the ratioof the full scale value to the rms value of the quantization noise.

The rms value of the quantization noise can be found by taking theroot mean square of the quantization noise. For the quantizationnoise designated by the solid line, this results in

rms(quantization noise) =12212

5.010

2

2 N

T

FSR LSBdt T t LSB

T !!¹

º ¸©

ª¨´

(1.10)



Therefore, the signal-to-noise ratio of the DAC can be expressed as

122/ N OUT

FSR

rmsvS N R ! (1.11)

The largest possible rms value of vOU T is or assuming a sinusoidal waveform. Therefore, the maximum SNR required for a DAC is

2/2/ FSR

22/ REF V

262

122

22max

N

N FSR

FSRS N R !! (1.12)





In teg r al non lin ea r ity (I NL) is the maximum difference between

the actual finite resolution characteristic and the ideal finiteresolution characteristic measured vertically. I ntegral nonlinearitycan be expressed as a percentage of the full scale range or in termsof the least significant bit. I ntegral nonlinearity has severalsubcategories, which include absolute, best-straight-line, and end-

point linearity. The I NL of a 3-bit DAC characteristic isillustrated in Figure. 1.6. The I NL of an N-bit DAC can beexpressed as a positive I NL and a negative I NL. The positive I NLis the maximum positive I NL. The negative I NL is the maximum

negativeI NL.

In Figure. 1.6, the maximum +

I NL is 1.5LSB andthe maximum ± I NL is -1.0LSB.



Diff er en t ial non lin ea r ity (DNL) is a measure of the separation between adjacent levels measured at each vertical jump.

Differential nonlinearity measures bit-to-bit deviations from idealoutput steps, rather than along the entire output range. I f V cx is theactual voltage change on a bit-to-bit basis and V s is the idealchange, then the differential nonlinearity can be expressed as

Differential nonlinearity (DNL) = LSBsV V

V V V

x

c x

s

sc x¹¹ º ¸©©ª

¨!v¹¹ º ¸©©ª

¨ 1%100

(1.15)

For an N-bit DAC and a full scale voltage range of V FSR ,

N FSR

s

V V

2! (1.16)



Figure 1.6 also illustrates differential nonlinearity. Note that DNLis a measure of the step size and is totally independent of how far the actual step change may be away from the infinite resolutioncharacteristic at the jump. The change from 101 to 110 results in amaximum +DNL of 1.5LSBs (V cx/V s = 2.5LSBs). The maximum

negative DNL is found when the digital input code changes from011 to 100. The change is -0.5LSB (V cx/V s = -0.5LSB), whichgives a DNL of -1.5LSBs. I t is of interest to note that as the digitalinput code changes from 100 to 101, no change occurs (point A).Because we know that a change should have occurred, we can saythat the DNL at point A is -1LSB



Figure 1.6 I llustration of I NL, DNL, and nonmonotonicity in a3-bit DAC.



M ono t on icity in a DAC means that as the digital input to theconverter increases over its full scale range, the analog output never exhibits a decrease between one conversion step and the next. I nother words, the slope of the transfer characteristic is never negativein a monotonic converter. Figure 1.6 exhibited nonmonotonic

behavior as the digital input code changed from 011 to 100.O bviously, a nonmonotonic DAC has very poor DNL. As a matter of fact, a DAC that has a ±DNL that is -1LSB or more negative willalways be nonmonotonic.



EX AMPL E 1.1I NL AND DNL O F A N O N I DEAL 4-B I T DAC

The transfer characteristics of an ideal and actual 4-bit DAC areshown in Figure. 1.7. Find the s I NL and s DNL in terms of LSBs. I s the converter monotonic or not?

Figure 1.7 The 4-bit DAC characteristics



Solution:

The worst-case I NL and DNL errors are shown on Figure. 1.7. For this example, + I NL = 1.5LSBs, - I NL = -1.5LSBs, +DNL =1.5LSBs, and ±DNL = -2LSBs. This DAC is not monotonic.



Ex ample 1.2

OP ERAT I O N O F THE SER I AL CHARGE-RED I STR I BU T I O N DAC

Assume that C 1 = C 2 and that the digital word to be converted isgiven as b 0 = 1, b 1 = 1, b 2 = 0, and b 3 = 1. Follow through thesequence of events that result in the conversion of this digital inputword.

Figure 1.8. Simplified schematic of a serial charge-redistribution DAC.





Solution:

The conversion starts with the closure of switch S 4, so that v C2 = 0.Since b 3 = 1, then switch S 2 is closed causing v C1 = V REF. Next,switch S 1 is closed causing v C1 = v C2 = 0.5V REF. This completes theconversion of the LSB. Figure 1.9 illustrates the waveforms acrossC1 and C 2 during this example. Going to the next most LSB, b 2,

switch S 3 is closed, discharging C 1 to ground. When switch S 1closes, the voltage across both C 1 and C 2 is 0.25V REF. Because theremaining 2-bits are both 1, C 1 will be connected to V REF and thenconnected to C 2 two times in succession. The final voltage acrossC1 and C 2 will be V REF. This sequence of events will require ninesequential switch closures to complete the conversion.



From the above example it can be seen that the serial DAC

requires considerable supporting external circuitry to make thedecision on which switch to close during the conversion process.Although the circuit for the conversion is extremely simple,several sources of error will limit the performance of this type of DAC. These sources of error include the capacitor parasiticcapacitances, the switch parasitic capacitances, and the clock feedthrough errors. The capacitors C 1 and C 2 must be matched towithin the LSB accuracy. This converter has the advantage of monotonicity and requires very little area for the portion shown in

Figure 1.8. An 8-bit converter using this technique has beenfabricated and has demonstrated a conversion time of 13.5 Qs.



A second approach to serial digital-analog conversion is calledalgorithmic. Figure 1.10 illustrates the pipeline approach toimplementing a serial algorithmic DAC. Figure 1.10 consists of unit delays and weighted summers. I t can be shown that theoutput of this circuit is

? A REF

N

N

N N

N

N

o ut V zb zb zb zb zV ! 111

222

111

0 22...2

(1.17)

where b i is either s 1. Figure 1.10 shows that it takes N + 1 clock pulses for the digital word to be converted to an analog signal,even though a new digital word can be converted on every clock

pulse.



The complexity of Figure. 1.10 can be reduced using techniques of replication and iteration. Here we shall consider only the iterationapproach. Equation (1.17) can be rewritten as

1

1

5.01!

z

V zb zV REF i

o ut (1.18)

where all b i have been assumed to be identical. The fact that each b i is either s 1 will be determined in the following realization.Figure 1.11 shows a block diagram realization of Eq. (1.18). I tconsists of two switches, A and B. Switch A is closed when the

ith-bit is 1 and switch B is closed when the ith-bit is 0. Then b iVREF is summed with one-half of the previous output and appliedto the sample-and-hold circuit that outputs the result for the ith-bitconversion. The following example illustrates the conversion

process.



Figure 1.10 P ipeline approach to implementing an algorithmicDAC.



Figure 1.11. Equivalent realization of Figure. 1.10 using iterativetechniques.



INTRO DUC TION AND CHA R AC T E RIZ ATION OF ANAL OG- DIGIT AL C ONV E RT E R S

Introduction to ADCs

Figure 1.12 shows a block diagram of a general ADC. A prefilter called anantialiasing filter is necessary to avoid the aliasing of higher frequency signals

back into the baseband of the ADC. O ften, the antialiasing filter is implemented by the bandlimiting characteristics of the ADC itself. The antialiasing filter isfollowed by a sample-and-hold circuit that maintains the input analog signal tothe ADC constant during the time this signal is converted to an equivalent outputdigital code. This period of time is called the conversion time of the ADC. Theconversion is accomplished by a quantization step. The nature of a quantizer isto segment the reference into subranges. Typically, there are 2N subranges,

where N is the number of bits of the digital output code. The quantization stepfinds the subrange that corresponds to the sampled analog input. Knowing thissubrange allows the digital processor to encode the corresponding digital bits.Thus, within the conversion time, a sampled analog input signal is converted toan equivalent digital output code.



The frequency response of the ADC of Figure. 1.12 is important tounderstand. Let us assume that the analog input signal has the

frequency response shown in Figure. 1.13(a). Furthermore, assumethat the frequency, f B ,is the highest frequency of interest of theanalog input signal. When the analog input signal is sampled at afrequency of f S, the frequency response shown in Figure. 1.13(b)results. The spectrum of the input signal is aliased at the sampling

frequency and each of its harmonics. I f the bandwidth of thesignal, f B, is increased above 0.5f S, the spectra begin to overlap asshown in Figure.1.13(c). At this point it is impossible to recover the original signal. This concept is formalized in the Nyquistfrequency or rate, which states that the sampling frequency must beat least twice the bandwidth of the signal in order for the signal to

be recovered from the samples. Consequently, it is necessary toapply the prefilter of Figure. 1.12 to eliminate signals in theincoming analog input that are above 0.5f S.



This is shown in Figure. 1.13(d). The overlapping of the foldedspectra also will occur if the bandwidth of the analog input signalremains fixed but the sampling frequency decreases below 2f

B.

Even if f B is less than 0.5f S as in Figure. 1.13(b), as we have seenin the previous chapter the antialiasing filter is necessary toeliminate the aliasing of signals in the upper passbands into the

baseband which is from 0 to f B.

Figure 1.12. General block diagram for an ADC.



Figure 1.13 (a) Continuous time frequency response of the analoginput signal. (b) Sampled-data equivalent frequency response. (c)Case where f B is larger than 0.5f S, causing aliasing. (d) U se of an

antialiasing filter to avoid aliasing.



I n order to maximize the input bandwidth of the ADC, one desiresto make f B as close to 0.5f S as possible. U nfortunately, this requires

a very sharp cutoff for the prefilter or antialiasing filter, whichmake this filter difficult and complex to implement. The types of ADCs that operate in this manner are called Nyquist analog-to-digital converters. Later we will examine ADCs that have f B muchless than 0.5f S. These ADCs are called oversampling analog-to-

digital converters. Table 1.1 gives the classification of varioustypes of ADCs.



TABL E 1.1 Classification of ADC Architectures

Conversion R ate Nyq uist ADCs O versampled ADCs

Slow Integrating (serial) Very high resolution>14 bits

Medium Successive approximation1-bit P ipelineAlgorithmic

Moderate resolution >10bits

Fast FlashMultiple-bit pipelineFolding and interpolating

Low resolution > 6 bits



Static Characterization of ADCs:

The input of an ADC is an analog signal, typically an analogvoltage, and the output is a digital code. The analog input can haveany value between 0 and V REF while the digital code is restricted tofixed or discrete amplitudes. P opular digital codes used for ADCsare shown in Table 1.2 and include binary, thermometer, Gray, andtwo¶s complement. The most widely used digital code is the binarycode. Some codes have advantages over others that make themattractive. For example, the Gray and thermometer codes onlychange 1-bit from one code to the next.

The static characterization of ADCs is based on the input-outputcharacteristic shown in Figure. 1.14 for a 3-bit ADC. I n this

particular characteristic, the input has been shifted so that the idealstep changes occur at analog input values of 0.5LSB(2i ± 1), wherei varies from 1 to N for an N-bit ADC.



The definitions for dynamic range, the signal-to-noise ratio(SNR), and the effective number of bits (EN O B) of the ADC arethe same as those given for the DAC. These quantities werereferenced to the analog variable and in the case of the ADC arereferenced to the digital output word.

Beneath the input-output characteristic of Figure. 1.14 is a plot of the quantization noise as a function of the input. The quantizationnoise is a plot of the difference between the infinite resolutioncharacteristic and the ideal 3-bit characteristic as a function of theinput voltage. The ideal ADC characteristic will have aquantization noise that lies between s 0.5LSB.

The resolution of the ADC is the smallest analog change that can be distinguished by an ADC. Resolution may be expressed in percent of full scale (FS) but is typically given in the number of bits, N, where the converter has 2 N possible output states.



The primary characteristics that define the static performance of converters are offset error, gain error, integral nonlinearity ( I NL),and differential nonlinearity (DNL). For an ADC with offset, let usshift the infinite resolution characteristic line horizontally until thequantization noise is symmetrical when referenced to this line (herewe assuming that other errors such as gain and nonlinearity are notdominant or have been removed from the characteristic). The

horizontal difference between this line and the infinite resolutioncharacteristic that passes through the origin is offset error. O ffseterror is illustrated in Figure. 1.15(a).



Gain error is a difference between the actual characteristic, andthe infinite resolution characteristic, which is proportional to themagnitude of the input voltage. The gain error can be thought of as a change in the slope of the infinite resolution line above or

below a value of 1. Gain error is illustrated in Figure. 1.15(b).Similar to the DAC, gain error can be measured as the horizontal

difference in LSBs between actual and ideal finite resolutioncharacteristics at highest digital code, i.e., between 110 and 111 onFigure. 1.15(b). I n this example, it is assumed that all other errorssuch as offset and nonlinearity are not present.



Table 1.2 Digital O utput Codes U sed for ADCs

Decimal Binar y T hermometer G ra y Tw o¶s Complement

0 000 0000000 000 000

1 001 0000001 001 111

2 010 0000011 011 110

3 011 0000111 010 101

4 100 0001111 110 100

5 101 0011111 111 011

6 110 0111111 101 010

7 111 1111111 100 001



Figure 1.14. I deal input-output characteristics of a 3-bit ADC.



The definition for integral nonlinearity ( I NL) of the ADC is themaximum difference between the actual finite resolutioncharacteristic and the ideal finite resolution characteristicmeasured vertically in percent or LSBs. With this definition, wefind that only integer values are permitted because the digital

output codes correspond to discrete amplitudes. This is not a problem as the resolution increases and the LSB becomes small.I n addition, when measuring the I NL if the measurementequipment is sufficiently accurate, it is able to resolve the I NL toless than a LSB.





Figure 1.15. (a) Example of offset error for a 3-bit ADC. (b)

Example of gain error for a 3-bit ADC.



Figure 1.16. Example of I NL and DNL for a 3-bit ADC.



Differential nonlinearity (DNL) of the ADC is defined as a

measure of the separation between adjacent codes measured ateach vertical step in percent or LSBs. The differentialnonlinearity of an ADC can be written as

LSBs D D N L c x 1! (1.19)

where D cx is the size of the actual vertical step in LSBs.



EX AMPL E 1.3

I NL AND DNL O F A 3-B I T ADC

Find the I NL and DNL for the 3-bit ADC in Figure. 1.17.

Figure 1.17. Example of nonmonotonic 3-bit ADC.



Solution:

The largest value of I NL for this 3-bit ADC occurs between andor and and is 1LSB. The smallest value of I NL occurs

between and and is ± 2LSBs. The largest value of DNL for

this example occurs at or and is + 1LSB. The smallest valueof DNL occurs at and is -2LSBs, which is where the converter

becomes nonmonotonic.

163

165

167

16

9

1611

1612

16

3

86

16

9



Dynamic Characteristics of ADCs:

The dynamic characteristics of ADCs have the same dependenceas found in DACs, namely, parasitic capacitances and the op amps.I n addition, in all ADCs at least one comparator is used. Thecomparator is used to determine whether the analog input is above

or below a particular voltage.

I n some cases, the ADC may use an op amp that will influence both the static and dynamic performances.



Sample -and -Hold Circuits:

Because the sample-and-hold (S/H) circuit is a key aspect of the

ADC, it is worthwhile to determine its influence on the ADC.Figure 1.18 shows the waveforms of a practical sample-and-holdcircuit. The acquisition time, indicated by t a, is the time duringwhich the sample-and-hold circuit must remain in the sample modeto ensure that the subsequent hold-mode output will be within aspecified error band of the input level that existed at the instant of the sample-and-hold conversion. The acquisition time assumes thatthe gain and offset effects he been removed. The settling time,indicated by t s, is the time interval between the sample-and-hold

transition command and the time when the output transient andsubsequent ringing have settled to within a specified error band.Thus, the minimum sample-and-hold time would be

a s sampl et t T !

(1.20)



Figure 1.18 Waveforms for a sample-and-hold circuit.



The minimum conversion time for an ADC would be equal toTsample and the maximum sample rate is

samp l e samp l e T

f 1

! (1.21)

I n addition to the above characteristics of a S/H circuit, there isan aperture time, which is the time required for the samplingswitch to open after the S/H command has switched from sampleto hold. Another consideration of the aperture time is aperture

jitter, which is a variation in the aperture time due to clock variations and noise. During the hold period of the S/H a kT/Cnoise exists because of the switch and hold capacitor.



Sample-and-hold circuits can be divided into two categories.These categories are S/H circuits with no feedback and S/H with

feedback. I n general, the use of feedback enhances the accuracyof the S/H at the sacrifice of speed. The minimum requirementfor a S/H circuit is a switch and a storage element. Typically, thecapacitor is used as the storage element. A simple open-loop

buffered S/H circuit is shown in Figure. 1.19(a). The unity-gainop amp is used to buffer the voltage across the hold capacitor.The ideal performance of this S/H circuit is shown in Figure.1.19(b). The sample mode occurs when the switch is closed andthe analog signal is sampled on a capacitor C H. During the

switch-open cycle or the hold mode, the voltage is available atthe output.



The S/H circuit of Figure. 1.19(a) is simple and fast. Thecapacitor, C H, is charged with the RC time constant of the switch

on resistance plus the source resistance of v in(t). O ne disadvantageis that the source, v in(t), must supply the current necessary tocharge C H. The unity-gain op amp prevents the voltage fromleaking off the capacitor and provides a low-resistance replica of the held voltage. The dc offset of the op amp and chargefeedthrough of the switch will cause this replica to be slightlydifferent.

An important dynamic limitation of the S/H circuit is the settlingtime of the op amp such as the one used in Figure. 1.19(a).

When an op amp with a dominant pole at [ a and a second pole atapproximately GB is put in the unity-gain configuration thetransfer function of the unity-gain configuration can beapproximated as



22

2

. G B sG B s

G B s A } (1.22)

Figure 1.19. (a) O pen-loop buffered S/H circuit. (b) Waveformsillustrating the operation of the sample-and-hold circuit of (a).



Anytime a change is made on the input of the unity-gain buffer, Eq.(1.22) will determine the response. For example, if a step changeof unity magnitude is made, the output voltage response is

¹¹ º

¸©©ª

¨¹¹ º

¸©©ª

¨! Ut G Bet v t G B

o ut .43

sin34

1 .5.0(1.23)

We know that the settling time is determined by how fast the termmultiplying the sinusoid dies out. I n fact, we can define the error as a function of time between the desired and actual outputvoltage as

t G B

o ut et vt Err o r .5.0

3

41 !!! I (1.24)



I n most ADCs, the error is equal to s 0.5LSB. I n this case, thevoltage is normalized so that we can write

N t G Bt G B N ee 2

3

434

21 .5.0.5.0

1 !p! (1.25)

Solving for the time, t s, required to settle with s 0.5LSB fromEq. (1.25) gives

? A6740.13863.1123

4ln2 !¹¹ º ¸©©ª

¨! N G BG B

t N s

(1.26)



We can easily see from Eq. (1.26) that as the resolution of theADC increases, the settling time for any unity-gain buffer

amplifier will increase. For example, if we are using the S/Hcircuit of Figure. 1.19(a) in a 10-bit ADC, the amount of timerequired for the unity-gain buffer with a GB of 1 MHz to settleto within 10-bit accuracy is 2.473 Qs.

Figure 1.20(a) shows an S/H circuit that charges C to the inputvoltage during the J 1 phase period and inverts and applies this toa buffer amplifier. In order to remove charge injection and clock feedthrough dependent on the input, a delayed J 1 clock, J 1d, is

used. Figure 1.20(b) shows a differential version of this S/Hcircuit. The differential S/H has the advantage of lower P SRR,cancellation of even harmonics, and reduction of the chargeinjection and clock feedthrough.



Figure 1.20. (a) Switched capacitor S/H circuit. (b) Differentialversion of (a).

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