eGaN® FET DATASHEET EPC8010

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC8010 – Enhancement Mode Power Transistor

VDS , 100 VRDS(on) , 160 mΩID , 4 A

EFFICIENT POWER CONVERSION

HAL

G

D

S

EPC8010 eGaN FETs are supplied only in passivated die form with solder barsDie Size: 2.1 mm x 0.85 mm

Applications• Ultra High Speed DC-DC Conversion• RF Envelope Tracking• Wireless Power Transfer• Game Console and Industrial Movement

Sensing (LiDAR)

Benefits• Ultra High Efficiency• Ultra Low RDS(on)

• Ultra Low QG

• Ultra Small Footprint

Maximum Ratings

PARAMETER VALUE UNITVDS Drain-to-Source Voltage (Continuous) 100 V

ID

Continuous (TA = 25°C, RθJA = 27°C/W) 4A

Pulsed (25°C, TPULSE = 300 µs) 7.5

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage –4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Static Characteristics (TJ= 25°C unless otherwise stated)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 100 VIDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V 20 100 µA

IGSSGate-to-Source Forward Leakage VGS = 5 V 0.1 0.5 mAGate-to-Source Reverse Leakage VGS = -4 V 20 100 μA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.25 mA 80 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 120 160 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 2.5 V

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 8.2

°C/WRθJB Thermal Resistance, Junction-to-Board 16

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 82

Specifications are with substrate connected to source where applicable.

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET

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EPC8010

7

6

5

4

3

2

1

00 0.5 1.0 1.5 2.0 2.5 3.0

Figure 1: Typical Output Characteristics at 25°C

I D –

Drai

n Cu

rrent

(A)

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

I D –

Drai

n Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V)

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 3 V

7

6

5

4

3

2

1

01.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

500

400

300

200

100

0

Figure 3: RDS(on) vs. VGS for Various Drain Currents

ID = 0.5 AID = 1 AID = 1.5 AID = 2 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0

500

400

300

200

100

0

Figure 4: RDS(on) vs. VGS for Various Temperatures

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

ID = 1 A

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CISS Input Capacitance

VDS = 50 V, VGS = 0 V

43 55pF

COSS Output Capacitance 25 36

CRSS Reverse Transfer Capacitance 0.3 0.5

RG Gate Resistance 0.3 Ω

QG Total Gate Charge VDS = 50 V, VGS = 5 V, ID = 1 A 360 480

pC

QGS Gate-to-Source Charge 130

QGD Gate-to-Drain Charge VDS = 50 V, ID = 1 A 60 100

QG(TH) Gate Charge at Threshold 100

QOSS Output Charge VDS = 50 V, VGS = 0 V 2200 3300

QRR Source-Drain Recovery Charge 0

Specifications are with substrate connected to source where applicable.

eGaN® FET DATASHEET

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EPC8010 Ca

pacit

ance

(pF)

Figure 5a: Capacitance (Linear Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

80

60

40

20

00 20 6040 80 100

Capa

citan

ce (p

F)

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

100

10

1

0.10 20 40 60 10080

5

4

3

2

1

00 0.1 0.2 0.3 0.4

Figure 6: Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (nC)

ID = 1 AVDS = 50 V

25˚C125˚C7

6

5

4

8

3

2

1

0

VSD– Source-to-Drain Voltage (V)

I SD–

Sour

ce-to

-Dra

in Cu

rrent

(A)

0.5 0 1.0 1.5 2.0 3.02.5 3.5 4.0 4.5 5.0

Figure 7: Reverse Drain-Source Characteristics

1.8

2.0

1.6

1.2

1.0

1.4

0.8 0 5025 75 100 125 150

Figure 8: Normalized On-State Resistance vs. Temperature

ID = 1 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

- R D

S(on

)

TJ – Junction Temperature (°C)

1.2

1.3

1.4

1.1

1.0

0.8

0.7

0.9

0.60 5025 75 100 125 150

Figure 9: Normalized Threshold Voltage vs. Temperature

ID = 0.25 mA

Norm

alize

d Th

resh

old

Volta

ge (V

)

TJ – Junction Temperature (°C)

eGaN® FET DATASHEET

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EPC8010

1.00.90.

80.7

1.2 1.

4 1.6

1.8

2.0

0.6

0.5

0.4

0.3

0.2

0.1

3.0

6.0

8.010

5.0

4.0

20

RF Café2002

100 0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

3.0

4.0

5.0

1.0

0.9

0.8

0.7

1.2

1.4

1.6

1.8

2.0

3.0

6.0

8.010

5.0

4.0

0.6

0.5

0.4

0.3

0.2

0.1

20

S11 – Gate Re�ectionS22 – Drain Re�ectionEPC8010

3 GHz

200 MHz

Figure 11: Smith Chart

S-Parameter CharacteristicsVGSQ = 1.34 V, VDSQ = 50 V, IDQ = 0.50 A

Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω

Figure 12: Gain Chart Figure 13: Device Reflection

Figure 14: Taper and Reference Plane details – Device Connection

Frequency Gate (ZGS) Drain (ZDS)

[MHz] [Ω] [Ω]

200 2.54 – j11.18 22.54 – j23.91

500 1.57 – j4.20 6.01 – j15.53

1000 0.94 – j0.23 1.85 – j6.89

1200 0.97 + j0.89 1.47 – j4.87

1500 0.97 + j2.38 1.51 – j2.52

2000 1.08 + j4.80 2.09 + j0.41

2400 1.21 + j6.74 2.50 + j2.25

3000 1.62 + j10.34 3.05 + j5.00

S-Parameter Table - Download S-parameter files at www.epc-co.com

ZDS

ZGS

Gate Circuit Reference Plane

Drain Circuit Reference Plane

Device Outline

914

1621

1621

149

1000

271

271

All dimensions in µm 914 355

100 1000

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–.0.2

45

40

35

30

25

20

15

10

5

0

Frequency (MHz)

25˚C125˚C

Gmax

EPC8010

Amplitude [dB]

1.0

1.2

0.8

0.4

0.2

0.6

010 32 4 5 6

Figure 10: Gate Leakage CurrentI G

– Ga

te Cu

rrent

(mA)

VGS – Gate-to-Source Voltage (V)

25˚C125˚C

Micro-Strip design: 2-layer½ oz (17.5 µm) thick copper30 mil thick RO4350 substrate

All measurements were done with substrate shortened to source.

eGaN® FET DATASHEET

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 5

EPC8010

Figure 16: Safe Operating Area

0.1

1

10

0.1 1 10 100

I D - D

rain

Curre

nt (A

)

VDS – Drain Voltage (V)

Pulse Width100 ms 10 ms 1 ms 100 µs 10 µs

Limited by RDS(on)

TJ = Max Rated, TC = +25°C, Single Pulse

10-6 10-5 10-4 10-3 10-2 10-1 1

Figure 15: Transient Thermal Response Curves

tp– Rectangular Pulse Duration, seconds

Junction-to-Case

Z θJC N

orm

alize

d Th

erm

al Im

peda

nce

10-5 10-4 10-3 10-2 10-1 1 10+1

Single Pulse

0.020.01

0.5

0.20.10.05

Duty Factors:

Duty Factor = tp/TPeak TJ = PDM x ZθJB x RθJB + TB

Notes:

tp

T

P DM

tp– Rectangular Pulse Duration, seconds

Z θJB N

orm

alize

d Th

erm

al Im

peda

nce

Junction-to-Board

Notes:

tp

T

P DM

Duty Factor = tp/TPeak TJ = PDM x ZθJC x RθJC + TC

0.5

0.20.10.05

Duty Factors:

Single Pulse

0.020.01

1

0.1

0.01

0.001

1

0.1

0.01

0.001

eGaN® FET DATASHEET

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 6

EPC8010

8010 YYYYZZZZ

Die orientation dot

Gate Pad bump is under this corner

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking line 2

Lot_Date CodeMarking Line 3

EPC8010 8010 YYYY ZZZZ

DIE MARKINGS

YYYY8010

ZZZZ

TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel

7” reel

a

d e f g

c

b

Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatepad bump isunder thiscorner

Die is placed into pocketsolder bump side down(face side down)

Loaded Tape Feed Direction

Dimension (mm) target min max a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

EPC8010 (note 1)

eGaN® FET DATASHEET

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 7

EPC8010

850

570

2050

1 2

4

3

6

5

400

190

600 600 400

440

190

190

RECOMMENDED LAND PATTERN (measurements in µm)

Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.

Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

DIE OUTLINESolder Bar View

Side View

DimMicrometers

Min Nominal MaxA 2020 2050 2080B 820 850 880C 555 580 605d 400 400 400e 600 600 600f 200 225 250g 175 200 225h 425 450 475i 175 200 225j 400 400 400

Pad no. 1 is GatePad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are SourcePad no. 4 is DrainPad no. 6 is Substrate*

*Substrate pin should be connected to Source

RECOMMENDED STENCIL DRAWING (measurements in µm)

2050

R60

850

325 200 245 230 450 Blue = bump, Gray = stencil275

272

200

592

250

2001 2

4

3

6

5

B

A

i

1 2

3

4

5

6

j

gx2

e e d f

h

C

i X2

815 M

ax

100 +

/- 20

Seating Plane

(685

)

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

The land pattern is solder mask defined. Solder mask opening is 5 µm smaller per side than bump.

Information subject to change without notice.

Revised August, 2019

Pad no. 1 is GatePad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are SourcePad no. 4 is Drain Pad no. 6 is Substrate*

*Substrate pin should be connected to Source