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eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
EPC2053 eGaN® FETs are supplied in passivated die form with solder bumps.Die size: 3.5 mm x 2 mm
Applications• 48 V Servers• Lidar/Pulsed Power• Isolated Power Supplies• Point of Load Converters• Class D Audio• LED Lighting• Low Inductance Motor Drive
Benefits• Higher Switching Frequency – Lower switching losses and lower drive power• Higher Efficiency – Lower conduction and switching losses, zero reverse recovery losses• Ultra Small Footprint - Higher power density
EFFICIENT POWER CONVERSION
HAL
EPC2053 – Enhancement Mode Power Transistor
VDS , 100 VRDS(on) , 3.8 mΩID , 48 A
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 100V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
ID
Continuous (TA = 25°C) 48A
Pulsed (25°C, TPULSE = 300 µs) 246
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJ Operating Temperature -40 to 150°C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 0.7
°C/W RθJB Thermal Resistance, Junction-to-Board 4.7
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 53Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.4 mA 100 V
IDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V, TJ = 25°C 0.07 0.3 mA
IGSSGate-to-Source Forward Leakage
VGS = 5 V, TJ = 25°C 0.03 4 mA
VGS = 5 V, TJ = 125°C 0.7 9 mA
Gate-to-Source Reverse Leakage# VGS = -4 V, TJ = 25°C 0.03 0.3 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 9 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 3.1 3.8 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2
200
150
100
50
0
200
150
100
50
0
10
8
6
4
2
0
10
8
6
4
2
0
1.0 1.5 2.0 2.5 3.0
VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2.5 2.0 3.0 3.5 4.0 4.5 5.0 2.5 2.0 3.0 3.5 4.0 4.5 5.0
ID = 25 A
25ºC125ºC
VDS = 3 V
25ºC125ºC
Figure 1: Typical Output Characteristics at 25°C
Figure 3: RDS(on) vs. VGS for Various Currents Figure 4: RDS(on) vs. VGS for Various Temperatures
Figure 2: Transfer Characteristics
0 0.5
ID = 12 A ID = 25 A ID = 37 A ID = 50 A
I D –
Drai
n Cu
rrent
(A)
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
I D –
Drai
n Cu
rrent
(A)
VDS – Drain-to-Source Voltage (V) VGS – Drain-to-Source Voltage (V)
VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance#
VDS = 50 V , VGS = 0 V
1453 1924
pF
CRSS Reverse Transfer Capacitance 10.4
COSS Output Capacitance# 642 963
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 50 V, VGS = 0 V
749
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 903
RG Gate Resistance 0.6 Ω
QG Total Gate Charge# VDS = 50 V, VGS = 5 V, ID = 25 A 11.4 14.8
nC
QGS Gate to Source Charge
VDS = 50 V, ID = 25 A
4.1
QGD Gate to Drain Charge 1.5
QG(TH) Gate Charge at Threshold 3.2
QOSS Output Charge# VGS = 0 V, VDS = 50 V 45 68
QRR Source-Drain Recovery Charge 0# Defined by design. Not subject to production test.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 3
Capa
citan
ce (p
F)
1800
1600
1400
1200
1000
800
600
400
200
00 25 50 75
25 50 75
100 0 25 50 75 100
Figure 5a: Capacitance (Linear Scale)
Capa
citan
ce (p
F)
10000
1000
100
10
Figure 5b: Capacitance (Log Scale)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Norm
alize
d On
-Sta
te R
esist
ance
– R
DS(o
n)
2.0
1.8
1.6
1.4
1.2
1.0
0.80 25 50 75 100 125 150
Figure 9: Normalized On-State Resistance vs. Temperature
200
150
100
50
0
Figure 8: Reverse Drain-Source Characteristics
5
4
3
2
1
00
Figure 7: Gate Charge80
64
48
32
16
0
3.5
2.8
2.1
1.4
0.7
0.0
Figure 6: Output Charge and COSS Stored Energy
100 2 4 6 8 10 12
ID = 25 A VDS = 50 V
ID = 11 A VGS = 5 V
Q OSS –
Out
put C
harg
e (nC
)I SD
– So
urce
-to-D
rain
Curre
nt (A
)
V GS –
Gat
e-to
-Sou
rce V
olta
ge (V
)
E OSS –
C OSS St
ored
Ener
gy (µ
J)
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)
2.5 2.0 3.0 3.5 0.5 0.0 1.0 1.5 4.0 4.5 5.0
VGS = 0 V
25ºC125ºC
QG – Gate Charge (nC)
VSD – Source-to-Drain Voltage (V) TJ – Junction Temperature (°C)
0
eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4
Figure 11: Transient Thermal Response Curves
0.001
0.01
0.1
1
10-5 10-4 10-3 10-2 10-1 1 10tp - Rectangular Pulse Duration (s)
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce Duty Factors:
0.50.20.10.05
0.02
0.01
Single PulseNotes:Duty Factor = tp/TPeak TJ = PDM x ZθJB x RθJB + TB
t p P
T
DM
Junction-to-Board
0.01
0.001
0.1
1
tp - Rectangular Pulse Duration [s]
Z θC,
Norm
alize
d The
rmal
Impe
danc
e
Junction-to-Case
Duty Factors:0.5
0.10.05
0.02
0.01
Single Pulse
0.2
Notes:Duty Factor = tp/TPeak TJ = PDM x ZθJC x RθJC + TC
t p P
T
DM
10-5 10-4 10-3 10-2 10-1 1 10
Norm
alize
d Th
resh
old V
olta
ge
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.60 25 50 75 100 125 150
Figure 10: Normalized Threshold Voltage vs. Temperature
ID = 9 mA
TJ – Junction Temperature (°C)
eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5
DIE MARKINGS
Figure 12: Safe Operating Area
0.1
1
10
100
1000
0.1 1 10 100 1000
I D- D
rain
Curre
nt (A
)
VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Pulse Width1 ms100 μs10 μs
Limited by RDS(on)
2053
YYYY
ZZZZ
TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel
7” reel
a
d e f g
c
b
EPC2053 (note 1) Dimension (mm) target min max
a 8.00 7.90 8.30 b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6
Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Dieorientationdot
Gatesolder bar isunder thiscorner
Die is placed into pocketsolder bar side down(face side down)
Loaded Tape Feed Direction
2053
YYYY
ZZZZ
Part Number
Laser Markings
Part #Marking Line 1
Lot_Date CodeMarking line 2
Lot_Date CodeMarking Line 3
EPC2053 2053 YYYY ZZZZ
Pin 1 indicator
eGaN® FET DATASHEET EPC2053
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6
B
A
e
d
c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Seating Plane
685
+/- 1
5
200+
/- 2
0
885
Information subject to change without notice.
Revised March 19, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED LAND PATTERN (units in µm)
Pad 1 is Gate;Pads 2, 3, 4, 9, 10, 11, 12, 17, 18, 19, 20, 25, 26, 27, 28 are Source; Pads 5, 6, 7, 8, 13, 14, 15, 16, 21, 22, 23, 24 are Drain.
Pad 1 is Gate;Pads 2, 3, 4, 9, 10, 11, 12, 17, 18, 19, 20, 25, 26, 27, 28 are Source; Pads 5, 6, 7, 8, 13, 14, 15, 16, 21, 22, 23, 24 are Drain.
DIE OUTLINESolder Bump View
Side View
DIMMICROMETERS
MIN Nominal MAX
A 3470 3500 3530B 1920 1950 1980c 450d 500e 238 264 290
DIM MICROMETERS
A 3500B 1950c 450d 500e 230
DIM MICROMETERS
A 3500B 1950c 450d 500f 300g 250
RECOMMENDED STENCIL DRAWING (measurements in µm)
Recommended stencil should be 4 mil (100 µm)thick, must be laser cut, opening per drawing.The corner has a radius of R60.Intended for use with SAC305 Type 4 solder,reference 88.5% metals content.
Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
B
A
e
d
c
3 7 11 15 19 23 27
4 8 12 16 20 24 28
1 5 9 13 17 21 25
2 6 10 14 18 22 26
B
A
f
d
c
g
3 7 11 15 19 23 27
4 8 12 16 20 24 28
1 5 9 13 17 21 25
2 6 10 14 18 22 26