eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 1

EPC2019

EPC2019 – Enhancement Mode Power Transistor

VDSS , 200 VRDS(on) , 50 mWID , 8.5 A

Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2019 eGaN® FETs are supplied only in

passivated die form with solder bars

Applications• High Speed DC-DC conversion• Class-D Audio• High Frequency Hard-Switching and Soft-Switching Circuits

Benefits• Ultra High Efficiency• Ultra Low RDS(on)

• Ultra low QG

• Ultra small footprint

EFFICIENT POWER CONVERSION

Maximum RatingsVDS Drain-to-Source Voltage (Continuous) 200 V

ID

Continuous (TA = 25°C, RθJA = 18 °C/W) 8.5A

Pulsed (25°C, TPulse = 300 µs) 42

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature -40 to 150°C

TSTG Storage Temperature -40 to 150

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Static Characteristics (TJ= 25˚C unless otherwise stated)

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 200 V

IDSS Drain Source Leakage VDS = 160 V, VGS = 0 V 20 100 µA

µAIGSS

Gate-to-Source Forward Leakage VGS = 5 V 0.8 mA

Gate-to-Source Reverse Leakage VGS = -4 V 20 100

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1.5 mA 0.8 1.4 2.5

2.5

V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 7 A 36 50 mΩVSD Source-Drain Forward Voltage VIS = 0.5 A, VGS = 0 V 1.8

Thermal Characteristics

RθJC Thermal Resistance, Junction to Case 2.7 °C/W

RθJB Thermal Resistance, Junction to Board 7.5 °C/W

RθJA Thermal Resistance, Junction to Ambient (Note 1) 72 °C/W

TYP UNIT

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate shorted to source.

G

D

SHAL

www.epc-co.com/epc/Products/eGaNFETs/EPC2019.aspx

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 2

EPC2019

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

CISS Input Capacitance 200

pFCOSS Output Capacitance 110

CRSS Reverse Transfer Capacitance 0.7

RG Gate Resistance 0.4 Ω

nCQGD Gate-to-Drain Charge

QG(TH) Gate Charge at Threshold

0.35

0.4

QGS Gate-to-Source Charge 0.6

QOSS Output Charge 18

QRR Source-Drain Recovery Charge 0

270

150

1

QG Total Gate Charge 1.8 2.5

0.6

23

All measurements were done with substrate shorted to source.

VDS = 100 V, VGS = 0 V

VDS = 100 V, VGS = 5 V, ID = 7 A

VDS = 100 V, ID = 7 A

VDS = 100 V, V = 0 VGS

40

35

30

25

20

15

10

5

00 1 2 3 4 5 6

Figure 1: Typical Output Characteristics at 25°C

I D –

Drai

n Cu

rrent

(A)

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

120

100

80

60

40

20

0

Figure 3: RDS(on) vs. VGS for Various Drain Currents

ID = 4 AID = 8 AID = 12 AID = 24 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I D –

Drai

n Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V)

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 6 V

40

35

30

25

20

15

10

5

01.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

120

100

80

60

40

20

0

Figure 4: RDS(on) vs. VGS for Various Temperatures

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

ID = 7 A

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 3

EPC2019

All measurements were done with substrate shortened to source.

Capa

citan

ce (p

F)

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

1000

100

10

1

0.10 50 100 150 200

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 7: Reverse Drain-Source Characteristics

0

2

4

6

8

10

12

14

16

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 .0 4.5 5.0

25˚C125˚C

Figure 9: Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge (V

)

1.4

1.3

1.2

1.0

1.1

0.9

0.8

0.7

0.60 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 1.5 mA

Capa

citan

ce (p

F)

Figure 5a: Capacitance (Linear Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

400

350

300

250

200

150

100

50

00 50 100 150 200

5

4

3

2

1

00 0.5 1.0 1.5 2.0

Figure 6: Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (nC)

ID = 7 AVDS = 100 V

Figure 8: Normalized On-State Resistance vs. Temperature

ID = 7 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

TJ – Junction Temperature (°C)

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 4

EPC2019

Figure 11: Transient Thermal Response Curves

Junction-to-Board

tp, Rectangular Pulse Duration, seconds

Duty Cycle:

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

PDM

t1

t2

0.5

0.1

0.05

0.02

0.01

Single PulseZ θJB

, Nor

mal

ized T

herm

al Im

peda

nce

10-410-5 10-3 10-2 10-1 1 10+1

1

0.1

0.01

0.001

Junction-to-Case

tp, Rectangular Pulse Duration, seconds

Duty Cycle:

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

PDM

t1

t2

0.50.20.10.050.020.01

Single Pulse

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

10-510-6 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

0.0001

I G –

Gate

Curre

nt (m

A)

VGS – Gate-to-Source Voltage (V)

Figure 10: Gate Leakage Current

25˚C125˚C

0 0

1

2

3

4

5

6

1 2 3 4 5 6

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 5

EPC2019

2019

YYYY

ZZZZ Die orientation dot

Gate Pad bump is under this corner

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking line 2

Lot_Date CodeMarking Line 3

EPC2019 2019 YYYY ZZZZ

DIE MARKINGS

TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel

7” reel

a

d e f g

c

b

EPC2019 (note 1) Dimension (mm) target min max

a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bar isunder thiscorner

Die is placed into pocketsolder bar side down(face side down)

Loaded Tape Feed Direction

Figure 12: Safe Operating Area

0.1

1

10

100

0.1 1 10 100 1000

I D –

Dra

in Cu

rrent

(A)

VDS - Drain-Source Voltage (V)

Limited by RDS(on)

TJ = Max Rated, TC = +25°C, Single Pulse

Pulse Width 100 ms 10 ms 1 ms 100 µs 10 µs

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 6

EPC2019

DIE OUTLINESolder Bar View

Recommended Land Pattern (Units in μm)

Side View

1

2 6

7

43 5

A

e g g

B c d

X2 X4

f X3

k

h

815 M

ax

100 ±

20

SEATING PLANE

(685

)

DIM MIN Nominal MAX

A 2736 2766 2796B 920 950 980c 697 700 703d 247 250 253e 168 183 198f 245 250 255g 600 600 600h 450 450 450i 235 250 265

MICROMETERS

Pad no.1 is Gate

Pad no. 3, 5 are Drain

Pad no. 2, 4, 6 are Source

Pad no. 7 is Substrate

Pad no. 1 is Gate

Pad no. 3, 5 are Drain

Pad no. 2, 4, 6 are Source

Pad no. 7 is Substrate

230

230 X3

230 X4

X4

680

2766

950

600 X2

600 X4

450

X2

2

1 7

6

43 5

The land pattern shown is solder mask defined. Copper is larger than the solder mask opening. The solder mask is 10um smaller per side than the bump.

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 7

EPC2019

RECOMMENDED STENCIL (Units in µm)

Information subject to change without notice.

revised September, 2015

For assembly recommendations please visit http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012

Pad no.1 is Gate

Pad no. 3, 5 are Drain

Pad no. 2, 4, 6 are Source

Pad no. 7 is Substrate

The solder stencil is 10µm smaller per side than the bump. The corner has a radius of R60

Recommended stencil should be 4mil (100µm) thick, must be laser cut, openings per drawing.

230

230 X3

230 X4

X4

680

2766

950

600 X2

600 X4

450

X2

2

1 7

6

43 5