eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 1

EPC2001C

Gallium nitride is grown on silicon wafers and processed using standard CMOS equipment leverag-ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-tron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

EPC2001C eGaN® FETs are supplied only in passivated die form with solder bars

Applications• HighSpeedDC-DCconversion• Class-DAudio• HighFrequencyHard-SwitchingandSoft-SwitchingCircuits

Benefits• UltraHighEfficiency• UltraLowRDS(on)• UltralowQG

• Ultrasmallfootprint

EFFICIENT POWER CONVERSION

HAL

EPC2001C – Enhancement Mode Power Transistor

VDSS , 100 VRDS(on) , 7 mWID , 36 A

Maximum Ratings

VDSDrain-to-Source Voltage (up to 10,000 5ms pulses at 150°C) 120 V

Drain-to-Source Voltage (Continuous) 100 V

ID

Continuous (TA = 25˚C, RθJA = 7.3) 36A

Pulsed (25˚C, Tpulse = 300 µs) 150

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature -40 to 150˚C

TSTG Storage Temperature -40 to 150

Thermal Characteristics

RθJC Thermal Resistance, Junction to Case 1 ˚C/W

RθJB Thermal Resistance, Junction to Board 2 ˚C/W

RθJA Thermal Resistance, Junction to Ambient (Note 1) 54 ˚C/W

TYP

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Static Characteristics (TJ= 25˚C unless otherwise stated)

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 µA 100 V

IDSS Drain Source Leakage VGS = 0 V, V DS = 80 V 100 250 µA

IGSS

Gate-Source Forward Leakage VGS = 5 V 1 5mA

Gate-Source Reverse Leakage VGS = -4 V 0.1 0.25

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 5 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 5.6 7 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V V1.7

All measurements were done with substrate shorted to source.

NEW PRODUCT

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 2

EPC2001CI D

– Dr

ain

Curre

nt (A

)

VDS – Drain-to-Source Voltage (V)

150

120

90

60

30

0 1 1.5 2 2.5 3

VGS

GS

GS

GS

= 5 VV = 4 VV = 3 VV = 2 V

I D –

Drai

n Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V)

150

120

90

60

30

00.5 1 1.5 2 2.5 3 3.5 4 4.5 5

R DS(

on) –

Dra

in t

o Sou

rce R

esist

ance

(mΩ

)

R DS(

on) –

Dra

in t

o Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V)

20

25

15

10

5

02.5 2 3 3.5 4 4.5 5

VGS – Gate-to-Source Voltage (V)

25

15

20

10

5

02.5 2 3 3.5 4 4.5 5

ID = 25 A

25˚C125˚C

VDS = 3 V

25˚C125˚C

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

Figure 3: RDS(on) vs. VGS for Various Currents Figure 4: RDS(on) vs. VGS for Various Temperatures

0 0.5

ID = 10 AID = 20 AID = 40 AID = 80 A

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

CISS Input Capacitance

VGS = 0 V, V DS = 50 V

770

pFCOSS Output Capacitance 430

CRSS Reverse Transfer Capacitance 10

RG Gate Resistance

VDS = 50 V, VGS = 5 V, ID = 25 A

VGS = 0 V, V = 50 VDS

0.3 Ω

nCQGD Gate-to-Drain Charge

QG(TH) Gate Charge at Threshold

1.2

1.6

QGS Gate-to-Source Charge 2.4

QOSS Output Charge 31

QRR Source-Drain Recovery Charge 0

900

650

15

QG Total Gate Charge 7.5 9

2

45

All measurements were done with substrate shorted to source.

VDS = 50 V, ID = 25 A

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 3

EPC2001C

All measurements were done with substrate shortened to source.

Norm

alize

d On-

Stat

e Res

istan

ce –

RDS

(on)

TJ – Junction Temperature ( ˚C )

1.8

2

1.6

1.4

1.2

1

0.8

0.60 25 50 75 100 125 150

ID = 25 AVGS = 5 V

Figure 8: Normalized On Resistance vs. Temperature

Norm

alize

d Th

resh

old V

olta

ge

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

0.60 25 50 75 100 125 150

ID = 5 mA

Figure 9: Normalized Threshold Voltage vs. Temperature

TJ – Junction Temperature ( ˚C )

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

I SD –

Sour

ce to

Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

12

24

36

48

60

72

25˚C125˚C

Figure 7: Reverse Drain-Source Characteristics

Capa

citan

ce (n

F)

VDS – Drain-to-Source Voltage (V)

1.2

1

0.8

0.6

0.4

0.2

00 20 40 60 80 100

Figure 5a: Capacitance (Linear Scale)

Capa

citan

ce (n

F)

VDS – Drain-to-Source Voltage (V)

0.01

0.1

1

0.0010 20 40 60 80 100

Figure 5b: Capacitance (Log Scale)V G

S – G

ate t

o Sou

rce

Volta

ge (V

)

QG – Gate Charge (nC)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

00 1 2 3 4 6 5 7 8

ID = 25 AVDS = 50 V

Figure 6: Gate Charge

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 4

EPC2001C

Figure 11: Transient Thermal Response Curves

0.001

0.01

0.1

1

10-5 10-4 10-3 10-2 10-1 1 10

Junction-to-Board

tp - Rectangular Pulse Duration [s]

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce Duty Factors:

0.5

0.10.05

0.020.01

Single Pulse

Notes:Duty Factor = tp/TPeak TJ = PDM x ZθJB x RθJB + TB

t p P

T

DM

0.0001

0.001

0.01

0.1

1Junction-to-Case

Duty Factors:0.5

0.10.050.020.01

Single Pulse

tp - Rectangular Pulse Duration [s]

Z θC,

Norm

alize

d The

rmal

Impe

danc

e

0.2

Notes:Duty Factor = tp/TPeak TJ = PDM x ZθJC x RθJC + TC

t p P

T

DM

10-5 10-4 10-3 10-2 10-1 1 10

I G –

Gate

Curre

nt (m

A)

VGS – Gate-to-Source Voltage (V)

25

20

15

10

5

00 1 2 3 4 5 6

25˚C125˚C

Figure 10: Gate Current

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 5

EPC2001C

TAPE AND REEL CONFIGURATION4mm pitch, 12mm wide tape on 7” reel

a

d e f g

c

b

EPC2001C (note 1) Dimension (mm) target min max

a 12.0 11.7 12.3 b 1.75 1.65 1.85

c (note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note 1: MSL1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,

not the pocket hole.

Dieorientation

dot

Gatesolder bar isunder this

corner

Die is placed into pocketsolder bar side down

(face side down)

7” reel

Loaded Tape Feed Direction

2001

YYYY

ZZZZ Die orientation dot

Gate Pad solder bar is under this corner

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking line 2

Lot_Date CodeMarking Line 3

EPC2001C 2001 YYYY ZZZZ

DIE MARKINGS

Figure 12: Safe Operating Area

0.1

1

10

100

0.1 1 10 100

I D- D

rain

Curre

nt (A

)

VDS - Drain-Source Voltage (V)

TJ = Max Rated, TC = +25°C, Single Pulse

Pulse Width100 ms10 ms1 ms100 us

limited by RDS(on)

eGaN® FET DATASHEET

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2014 | | PAGE 6

EPC2001C

1362

560

180 180X9

X2

RECOMMENDEDLAND PATTERN (units in µm)

Pad no. 1 is Gate;

Padsno.3,5,7,9,11areDrain;

Padsno.4,6,8,10areSource;

Pad no. 2 is Substrate.

Information subject to change without notice.

Revised October 2014

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.

U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398

The land pattern is solder mask defined.

815

Max

100

+/- 2

0

SEATING PLANE

(685

) B

A

d X2

c

e g

3 4 5 7 6 9 8 10 11

g X8

f f X9

2

1

DIE OUTLINESolder Bar View

Side View

DIM   MICROMETERS  MIN   Nominal   MAX  

A   4075   4105   4135  B   1602   1632   1662  c   1379   1382   1385  d   577   580   583  e   235   250   265  f   195   200   205  g   400   400   400