Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

ECEN620: Network TheoryBroadband Circuit Design

Fall 2014

Lecture 5: PLL Units & Noise Transfer Functions

Announcements, Agenda, & References

• HW1 is due Wednesday 9/24

• PLL Units• PLL Noise Transfer Functions

• Chapter 2, 3, 5, & 12 of Phaselock Techniques,F. Gardner, John Wiley & Sons, 2005.

• Chapter 1-3.4 of “Low-Power Low-Jitter On-Chip Clock Generation,” M. Mansuri, Ph.D. thesis, UCLA, 2003.

2

PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)

3

Phase Detector

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output, thus to characterize phase detector gain, extract average output voltage

• The KPD factor can change depending on the specific phase detector circuit

V/rad are units :filter loop less-dimension w/ PLL

PDK4

Dimension-Less Loop Filter

• Lowpass filter extracts average of phase detector signal

• No units for the dimension-less loop filter

( ) ( )

CRCR

sssF

2211

21

2

11

==

+++

=

ττ

τττ

Example: Passive Lag-Lead Loop Filter[Allen]

5

Voltage-Controlled Oscillator

• Time-domain phase relationship

VDDVDD/20

ω0 1KVCO

( ) ( ) ( )tvKtt cVCOoutout +=∆+= 00 ωωωω

( ) ( ) ( )∫ ∫=∆= dtdt tvKtt cVCOoutout ωφLaplace Domain Model

φout(t)( )

Vsrad102

VMHz12

Vsrad are units

6

⋅×=

⋅

ππ

VCOK

6

Loop Divider

• Time-domain model

( ) ( )tN

t outfb ωω 1=

( ) ( ) ( )∫ == tN

tN

t outoutfb φωφ 1dt1

[Perrott]

φout(t) φfb(t)

• The loop divider is dimension-less in the PLLlinear model

7

PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)

less-unit isDivider LoopVs

rad are units

less-unit isFilter LoopV/rad are units

⋅VCO

PD

K

K

8

[Mansuri]

PLL Units w/ Impedance Filter (Charge-Pump PLL)

=π2CP

PDDIKK

9

Phase Frequency Detector (PFD)• Phase Frequency Detector allows for wide

frequency locking range, potentially entire VCO tuning range

• 3-stage operation with UP and DOWN outputs• Net difference in pulse width represents phase error• UP longer = Positive ∆φ• DN longer = Negative ∆φ

• Edge-triggered results in duty cycle insensitivity• The un-averaged PFD gain (ratio of net output pulse time width with

input phase error time) is typically “1” and dimension-less

10

Averaged PFD Transfer Characteristic

• Constant slope and polarity asymmetry about zero phase allows for wide frequency range operation

• The averaged PFD gain is typically “1/(2*pi)” with units of rad-1

UP=1 & DN=-1

[Perrott]

11

Charge Pump

• Converts PFD output signals to charge

• Charge is proportional to PFD pulse widths

( )

used isdetector phasedifferent a ifcan vary gain Thisrad

Amps 2

Gain Pump-Charge & PFD Total

radAmps

2 Gain Pump-Charge Averaged

Amps Gain Pump-Charge Averaged-Un

=

=

=

π

π

CP

CP

CP

I

II

12

Loop Filter

• Lowpass filter extracts average of phase detector error pulses

• The units of the filter are ohms

I

I

VCO ControlVoltage

C1

R

C2

Charging

Discharging

VDD

VSSF(s)

( )sRC

sRsF

+

= 1

1

( )

++

+

=

21

21

12

11

CRCCCss

RCs

CsF

w/o C2

w/ C2

13

[Mansuri]

PLL Units w/ Impedance Filter (Charge-Pump PLL)

=π2CP

PDDIKK

less-unit isdivider Loop

Vsrad are units , of units hasFilter Loop

radA of units hasgain combined Pump-Charge &Detector Phase Total

averaged if radA averaged,-un ifA are unitsGain Pump Charge

averaged if rad of units averaged,-un if less-unit is 1-

⋅Ω VCO

PD

K

KOnly Average

Once

14

PLL Noise Transfer Function

[Mansuri]

15

Input Noise Transfer Function

( ) 222 2

221

nn

nn

n

outn ss

sN

RCKKss

RCsNK

sHIN

IN ωζωζωζω

φφ

++

+=

++

+

==

( )

++

+

=

==

RCKKsss

RCsNKK

sK

vsT

oo

n

out

n

outn

ININ

IN2

1

φφφ

sKo

Input Phase Noise:

Voltage Noise on Input Clock Source:

[Mansuri]

)1 (assumes 2

:factorgain loop aw/ == PDVCOCP KN

RKIKπ

16

Input Noise Transfer Function

( ) 222 2

221

nn

nn

n

outn ss

sN

RCKKss

RCsNK

sHIN

IN ωζωζωζω

φφ

++

+=

++

+

==

( )

++

+

=

==

RCKKsss

RCsNKK

sK

vsT

oo

n

out

n

outn

ININ

IN2

1

φφφ

Input Phase Noise:

Voltage Noise on Input Clock Source:

( )

( )VCO0

VCOn

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10

10*2 ,1 ,1*2

Parameters Simulation

ωωπ

ππµ

πωζπω

===

Ω==

===

===

bufdelay

VCOPD

VpsK

VMHzK

kRpFC

VGHzKAK

GHzMHz

17

VCO Noise Transfer Function

( ) 22

2

2

2

2 nnn

outn ss

s

RCKKss

ssHVCO

VCO ωζωφφ

++=

++==

( )

RCKKss

sKs

Kv

sT VCOVCO

n

out

n

outn

VCOVCO

VCO

++=

==

2φφφ

VCO Phase Noise:

Voltage Noise on VCO Inputs:

KVCO is different if the input is at the Vcntrl input (KVCO) or supply (KVdd)

[Mansuri]

18

VCO Noise Transfer Function

( ) 22

2

2

2

2 nnn

outn ss

s

RCKKss

ssHVCO

VCO ωζωφφ

++=

++==

( )

RCKKss

sKs

Kv

sT VCOVCO

n

out

n

outn

VCOVCO

VCO

++=

==

2φφφ

VCO Phase Noise:

Voltage Noise on VCO Inputs:

( )

( )VCO0

VCOn

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10

10*2 ,1 ,1*2

Parameters Simulation

ωωπ

ππµ

πωζπω

===

Ω==

===

===

bufdelay

VCOPD

VpsK

VMHzK

kRpFC

VGHzKAK

GHzMHz

19

Clock Buffer Noise Transfer Function

( ) 22

2

2

2

2 nnn

outn ss

s

RCKKss

ssHbuf

buf ωζωφφ

++=

++==

( )

RCKKss

sK

RCKKss

ss

Ks

Kv

sT VCOdelay

buf

VCOdelay

buf

VCOdelay

n

out

n

outn

bufbuf

buf

++≈

++

+=

+

==

2

2

2

2

11

ω

ω

ω

ω

ωφφφ

Output Phase Noise:

Voltage Noise on Buffer Inputs:

Kdelay units = (s/V)

[Mansuri]

1+buf

VCOdelays

K

ω

ω

20

Clock Buffer Noise Transfer Function

( ) 22

2

2

2

2 nnn

outn ss

s

RCKKss

ssHbuf

buf ωζωφφ

++=

++==

( )

RCKKss

sK

RCKKss

ss

Ks

Kv

sT VCOdelay

buf

VCOdelay

buf

VCOdelay

n

out

n

outn

bufbuf

buf

++≈

++

+=

+

==

2

2

2

2

11

ω

ω

ω

ω

ωφφφ

Output Phase Noise:

Voltage Noise on Buffer Inputs:

( )

( )VCO0

VCOn

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10

10*2 ,1 ,1*2

Parameters Simulation

ωωπ

ππµ

πωζπω

===

Ω==

===

===

bufdelay

VCOPD

VpsK

VMHzK

kRpFC

VGHzKAK

GHzMHz

21

PLL Noise Transfer Function Take-Away Points

• The way a PLL shapes phase noise depends on where the noise is introduced in the loop

• Optimizing the loop bandwidth for one noise source may enhance other noise sources

• Generally, the PLL low-pass shapes input phase noise, band-pass shapes VCO input voltage noise, and high-pass shapes VCO/clock buffer output phase noise

22

Next Time

• PLL System Analysis• Transient Response

23