Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

ECEN620: Network TheoryBroadband Circuit Design

Fall 2019

Lecture 7: Voltage-Controlled Oscillators

Announcements

2

• Exam 1 Tuesday Oct 15• One double-sided 8.5x11 notes page allowed• Bring your calculator• Covers through Lecture 7

Agenda

• VCO Fundamentals• VCO Examples• VCO Phase Noise

• Phase Noise Definition and Impact• Ideal Oscillator Phase Noise• Leeson Model• Hajimiri Model• Phasor-Based Phase Noise Analysis

• VCO Jitter

3

Charge-Pump PLL Circuits

• Phase Detector

• Charge-Pump

• Loop Filter

• VCO

• Divider

4

Voltage-Controlled Oscillator

• Time-domain phase relationship

5

VDDVDD/20

0 1KVCO

tvKtt cVCOoutout 00

dtdt tvKtt cVCOoutout Laplace Domain Model

out(t)

Voltage-Controlled Oscillators (VCO)

• Ring Oscillator• Easy to integrate• Wide tuning range (5x)• Higher phase noise

• LC Oscillator• Large area• Narrow tuning range (20-30%)• Lower phase noise

6

Barkhausen’s Oscillation Criteria

• Sustained oscillation occurs if

• 2 conditions:• Gain = 1 at oscillation frequency 0

• Total phase shift around loop is n360 at oscillation frequency 0

7

jHjH

1Closed-loop transfer function:

1jH

n

[Sanchez]

Agenda

• VCO Fundamentals• VCO Examples• VCO Phase Noise

• Phase Noise Definition and Impact• Ideal Oscillator Phase Noise• Leeson Model• Hajimiri Model• Phasor-Based Phase Noise Analysis

• VCO Jitter

8

Ring Oscillator Example

9

[Sanchez]

Ring Oscillator Example

10

• 4-stage oscillator – work this one out yourself• A0 = sqrt(2)• Phase shift = 45°

• Easier to make a larger-stage oscillator oscillate, as it requires less gain and phase shift per stage, but it will oscillate at a lower frequency

LC Oscillator Example

221

22211

221

22

12

11

1

1

1

CRCL

LRjsZ

sCRsCLsLRsZ

S

Seq

S

Seq

LC tank impedance

• Oscillation phase shift condition satisfied at the frequency when the LC (and R) tank load displays a purely real impedance, i.e. 0 phase shift

LC Oscillator Example

• Transforming the series loss resistor of the inductor to an equivalent parallel resistance

12

SPP

SP R

LRCCLRLL

221

1221

2

1 ,,1

PPCL1

1

RP

[Razavi]

LC Oscillator Example

13

12 PmRg

PPCL1

1

Loop Gain

• Phase condition satisfied at

• Gain condition satisfied when

[Razavi]

• Can also view this circuit as a parallel combination of a tank with loss resistance 2RP and negative resistance of 2/gm

• Oscillation is satisfied when

Pm

Rg

1

• Noise in the system will initiate oscillation, with the signals eventually exhibiting rail-to-rail swings

• While the small-signal transistor parameters (gm, go, Cg, etc…) can be used to predict the initial oscillations during small-signal start-up, these parameters can vary dramatically during large-signal operation

CMOS Inverter Ring Oscillator

14

[Razavi]

• For this large-signal oscillator, the frequency is set by the stage delay, TD

• TD is a function of the nonlinear current drive and capacitances of each stage

• As an “edge” has to propagate twice around the loop

CMOS Inverter Ring Oscillator

15

[Razavi]

number stage oscillator theis N where2

1or ,6

1

DDosc NTTf

Supply-Tuned Ring Oscillator

16

thc

stageDVCO VV

nCnTT

22

stagec

VCOVCO nCV

fK2

[Sidiropoulos VLSI 2000]

Current-Starved Ring Oscillator

17

[Sanchez]

Capacitive-Tuned Ring Oscillator

18

Symmetric Load Ring Oscillator

19

[Maneatis JSSC 1996 & 2003]

• Symmetric load provides frequency tuning at excellent supply noise rejection

• See Maneatis papers for self-biased techniques to obtain constant damping factor and loop bandwidth (% of ref clk)

2ID

Pseudo-Differential Ring Oscillators

20

[Frans JSSC 2015]

• Often supply-tuned with a regulator• Band select is possible with adjustable capacitors and main path

inverter strength• Due to even stages, there is a potential for the oscillator to be stuck in

a non-differential mode• Adjustable ratio between cross-coupled and main inverters, initially

large, ensures startup in differential mode. This can be reduced during normal operation.

LC Oscillator

• A variable capacitor (varactor) is often used to adjust oscillation frequency

• Total capacitance includes both tuning capacitance and fixed capacitances which reduce the tuning range

21

fixedtunePPPosc CCLCL

11

Varactors

• pn junction varactor• Avoid forward bias region to prevent oscillator nonlinearity

22

• MOS varactor• Accumulation-mode devices have better Q than inversion-mode

[Perrott]

n-well[Razavi]

Agenda

• VCO Fundamentals• VCO Examples• VCO Phase Noise

• Phase Noise Definition and Impact• Ideal Oscillator Phase Noise• Leeson Model• Hajimiri Model• Phasor-Based Phase Noise Analysis

• VCO Jitter

23

Oscillator Noise

24

Jitter

[McNeill]

Phase Noise Definition

• An ideal oscillator has an impulse shape in the frequency domain• A real oscillator has phase noise “skirts” centered at the carrier frequency• Phase noise is quantified as the normalized noise power in a 1Hz

bandwidth at a frequency offset from the carrier

25

dBc/Hz P

1Hz ,Plog10carrier

sideband

oL

Phase Noise Impact in RF Communication

• At the RX, a large interferer can degrade the SNR of the wanted signal due to “reciprocal mixing” caused by the LO phase noise

• Having large phase noise at the TX can degrade the performance of a nearby RX

26

RX Reciprocal Mixing Strong Noisy TX Interfering with RX

Jitter Impact in HS Links

27

• RX sample clock jitter reduces the timing margin of the system for a given bit-error-rate

• TX jitter also reduces timing margin, and can be amplified by low-pass channels

Ideal Oscillator Phase Noise

28

2tank

22

2

is voltagenoise squared-mean theofdensity spectral The

4

noisethermalintroducewillresistance tank The

Zfi

fv

RkT

fi

nn

n

Tank Impedance Near Resonance

29

2

2tank

tank

22tank

2tank

2

2

1 Tank

12221

resonance toclose sfrequencieConsider

1 :Frequency Resonance

11

QRZ

QRjZ

QR

CCRQ

Cj

LCLj

LCLCLCLjZ

LC

LCLjLj

CjZ

o

o

oo

o

oo

o

oo

o

o

o

Ideal Oscillator Phase Noise

30

carrier thefromaway slope 20dB/dec- adisplay willnoise thermal todue noise Phase

dBc/Hz 2

2log102

421

log1021

log10

phase. and amplitudebetween 21evenly

split ispower noise thisTherefore, equal. arepower noise-phase and amplitudem,equilibriuin that,states 2000] JSSC [Lee Theoremion Equipartit The

24

24

22

22

2

222

tank

22

QPkT

Qv

kTR

vfv

L

QkTR

QR

RkTZ

fi

fv

o

sig

o

sigsig

n

oonn

• Phase noise improves as both the carrier power and Q increase

Other Phase Noise Sources

• Tank thermal noise is only one piece of the phase noise puzzle

• Oscillator transistors introduce their own thermal noise and also flicker (1/f) noise

31

[Perrott]

Leeson Phase Noise Model

32

• Leeson’s model modifies the previously derived expression to account for the high frequency noise floor and 1/f noise upconversion

• A empirical fitting parameter F is introduced to account for increased thermal noise

• Model predicts that the (1/)3

region boundary is equal to the 1/f corner of device noise and the oscillator noise flattens at half the resonator bandwidth

dBc/Hz 12

12log1031

2

fo

sig QPFkTL

Noise Floor

1/f Noise

33 ELEN620-IC Design of Broadband Communication circuit

A 3.5GHz LC tank VCO Phase Noise

MeasurePhasenoise

-30dB/decade-20dB/decade

-105dBc

34 ELEN620-IC Design of Broadband Communication circuit

RBW=10K

PN=-85dBm-(-20dBm)-10log10(10e3)

=-105dBc

VCO Output Spectrum Example

-85dBm

-20dBm

dBc---in dB with respect to carrier

Make sure to account for the spectrum analyzer resolution bandwidth

Leeson Model Issues

35

• The empirical fitting parameter F is not known in advance and can vary with different process technologies and oscillator topologies

• The actual transition frequencies predicted by the Leeson model does not always match measured data

YCLOAMSC-TAMU 36

Harjimiri’s Model (T. H. Lee) Injection at Peak (amplitude noise only)

Injection at Zero Crossing (maximum phase noise)

37 ELEN620-IC Design of Broadband Communication circuit

A time-Varying Phase Noise model: Hajimiri-Lee model

Impulse applied to the tank to measure its sensitivity function

The impulse response for the phase variation can be represented as

fin

2

is the impulse sensitivity function ISFqmax, the maximum charge displacement across the capacitor, is a normalizing factor

Impulse Sensitivity Function (ISF) Model

• The phase variation due to injected noise can be modeled as

38

• The function () is a time-varying proportionality factor called the “impulse sensitivity function”• Encodes information about the sensitivity of the oscillator

to an impulse injected at phase (0 to 2)• Phase shift is assumed linear to charge injection• ISF has the same oscillation period as the oscillator

• The phase impulse response can be written as

39 ELEN620-IC Design of Broadband Communication circuit

How to obtain the Impulse sensitivity function for a LC oscillator

() can be obtained using CadenceConsider the effect on phase noise of each noise source

YCLOAMSC-TAMU 40

Typical ISF Example The ISF can be estimated analytically or calculated from simulation. The ISF reaches peak during zero crossing and zero at peak for typical LC and ring oscillators.

Phase Noise Computation

41

diq

dith

tuq

th

t

o

o

max

max

1,t

function impulse noise phase th thecurrent wi noisearbitrary any

theof integral on)(convolutiion superposit by the computed becan then noise phase The

,

functionimpulsenoisephase obtain thetousedisfunction y sensitivit impulse The

ISF Decomposition w/ Fourier Series

42

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Fourier ISF theonce computed be tosource noisearbitrary an from phase excess theallows This

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1

0

max

1

0

no

t

n

t

nnn

nnono

dnicdicq

nc

ncc

Phase Noise Frequency Conversion

43

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4log10

powerth carrier wi about the symmetric sidebands ightedequally we twobe will there,cos

waveformsinusoidal a Assuming .at sidebands equal twoshow willspectrumfrequency resulting The

2sin

other than

termsall fromon contributi negligible a be will thereintegral,n computatio noise phase theperformingWhen

cos

frequencyn oscillatio theof multipleinteger

an near isfrequency osecurrent whnoisesinusoidalahave we wherecase simple aconsider First

2

2

max

max

ω

ωqcIP

tttv

ωqωtcItφ

mn

tmIti

m

mmSBC

oout

mm

om

low-frequency noise noise near o

noise near 2o

noise near 3o

Phase Noise Due to White & 1/f Sources

44

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carrier. near the stays and 1 and by weightediscarrier near the noise White

carrier. near the noise 1 becomes noise 1 so ,t coefficienby weightedd,upconverte gets dcnear Noise

.1by weightedare and itself

carrier near the fold allfrequency carrier theof multiplesinteger near components noise Here

4log10

in resultssourcenoisewhiteaofcasegeneral the toanalysis previous theExtending

2

21

30

2

22max

0

22

fc

fc

ffc

ω

ωq

cfi

P

m

mm

n

SBC

How to Minimize Phase Noise?

45

s.frequencie allat noise phase thereduce will reducing Thus,

2log10

as expressed becan region 1 in the spectrum The

21

theoremsParseval' Usingminimized. be should tscoefficien ISF thenoise, phase minimize order toIn

22max

22

2

2

0

22

0

2

rms

rmsn

rmsm

m

n

ωqfi

L

f

dxxc

c

1/f Corner Frequency

46

noise. 1in reductions dramaticfor potential theis e then thersymmetry, time-fall and -risethrough

minimized is If corner. noisecuit device/cir 1 thelower thangenerally is This

4

isfrequency corner 1 theThus,

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slide previous theFrom

frequencycorner 1 theis where

content 1 includes which noisecurrent Consider

2

12

20

11

3

122

max

20

2

1

1221,

3

f

f

c

f

ωq

cfi

L

f

ii

f

dc

rms

dcf

rmsff

f

n

f

fnfn

Cyclostationary Noise Treatment

47

xxx

xi

ttiti

n

nn

NMF

0

00

ISF effectivean formulatecan we this, Usingunity. of peak value aith function w unitless periodic a is and source, noise

onarycyclostati theof that toequal is peak value whosesource noise whitestationary a is Here

function. periodic a and noise whitestationary ofproduct theasit gby treatin thishandleeasily can model LTV The

cycle.oscillatoran over ly dramaticalchangecan noise,thusandcurrent,drain Transistor

Key Oscillator Design Points from Hajimiri Model

48

• As the LTI model predicts, oscillator signal power and Q should be maximized

• Ideally, the energy returned to the tank should be delivered all at once when the ISF is minimum

• Oscillators with symmetry properties that have small dc will provide minimum 1/f noise upconversion

Reducing LC-VCO Noise in FinFET Processes

49

• NMOS only current-limited LC-VCO avoids the high flicker noise present in PMOS transistors

• Stacked devices further reduced flicker noise

• Regulator noise reduced with RC filtering

• Low current multiplication factor to minimize tail current noise

• MOM cap switches designed to improve tank Q [Turker ISSCC 2018]

LC-VCO Capacitor Switch

50

• When sel=0, high impedance stacked transistors pull nodes A & B higher to minimize Q degradation due to M1 leakage [Turker ISSCC 2018]

Sel=1

Sel=0

Filtering LC-VCO Regulator Flicker Noise

51

• RC filter at reference input• Regulator designed with transistor stacking, double gate

contacts, and large width & lengths• Programmable sub-threshold FET resistor to realize kHz

range filter

[Turker ISSCC 2018]

(A & B)

Carrier frequency = 16GHzA B C

(C) Further improves noise by ~3.5dB

Sub-threshold FET R~= 1M-ohm to 50M-ohm

Low-Noise Charge Pump

52

• Low mirroring ratio between input diode-connected transistor and charge pump current source

• Large replica bias transistors to set PMOS current• Extra filtering in PMOS bias• Stacked transistors utilized

[Turker ISSCC 2018]

CMOS Circuit Noise Reduction

53

• Important to maintain fast edge rates (<10ps) in CMOS circuits to reduce flicker noise impact

[Turker ISSCC 2018]

Phasor-Based Phase Noise Analysis

54

• Models noise at 2 sideband frequencies with modulation terms

• The 1 and 2 terms sum co-linear with the carrier phasor and produce amplitude modulation (AM)

• The 1 and 2 terms sum orthogonal with the carrier phasor and produce phase modulation (PM)

Phasor-Based LC Oscillator Analysis

55

• This phasor-based approach can be used to find closed-form expressions for LC oscillator phase noise that provide design insight

• In particular, an accurate expression for the Leesonmodel F parameter is obtained

dBc/Hz 2

2log102

QP

FkTL o

sig

LC Oscillator F Parameter

56

• 1st Term = Tank Resistance Noise• 2nd Term = Cross-Coupled Pair Noise• 3rd Term = Tail Current Source Noise

dBc/Hz 2

2log102

QP

FkTL o

sig

• The above expression gives us insight on how to optimize the oscillator to reduce phase noise

• The tail current source is often a significant contributor to total noise

Tail Current Noise

57

• The switching differential pair can be modeled as a mixer for current source noise

• Other than low-frequency noise, only the second-order harmonic is converted close to the carrier• The other frequencies are filtered by the LC tank

• Introducing a tail-current filter to attenuate this second-order harmonic can improve phase noise performance

[Hegazi JSSC 2001] Output PSD

Tail Current Filter

58

• Large capacitor in parallel with current source shorts high-frequency noise to ground

• Series inductor resonating with differential transistors’ source capacitors at 20 provides a high impedance and reduces tank loading

• Provides near 7dB phase noise improvement

[Hegazi JSSC 2001]

Tail Current Top Bias

Agenda

• VCO Fundamentals• VCO Examples• VCO Phase Noise

• Phase Noise Definition and Impact• Ideal Oscillator Phase Noise• Leeson Model• Hajimiri Model• Phasor-Based Phase Noise Analysis

• VCO Jitter

59

Open-Loop VCO Jitter

• Measure distribution of clock threshold crossings• Plot as a function of delay T

60

[McNeill]

T

Open-Loop VCO Jitter

• Jitter is proportional to sqrt(T)• is VCO time domain figure of merit

61

TTOLT

[McNeill]

VCO in Closed-Loop PLL Jitter

62

• PLL limits for delays longer than loop bandwidth L

LL f 21

[McNeill]

Ref Clk-Referenced vs Self-Referenced

63

[McNeill]

Ref Clock for Frequency Synthesis PLL

• Generally, we care about the jitter w.r.t. the ref. clock (x)• However, may be easier to measure w.r.t. delayed version of output clk

• Due to noise on both edges, this will be increased by a sqrt(2) factor relative to the reference clock-referred jitter

CDR Example

Converting Phase Noise to Jitter

64

• Actual integration range depends on application bandwidth• fmin set by asumed CDR tracking bandwidth• fmax set by Nyquist frequency (f0/2)

• Most exact approach

2 22

0

4 sinToS f f T df

• RMS jitter for T accumulation

• As T goes to ∞ 22 2

0

2 20To oR S f df

[Mansuri]

02 22

20

2

2

where is the system jitter transfer function

f

T syso

sys

S f H f df

H f

Next Time

• Divider Circuits

65