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Sam Palermo Analog & Mixed-Signal Center
Texas A&M University
ECEN620: Network Theory Broadband Circuit Design
Fall 2012
Lecture 9: PLL Acquisition
Announcements, Agenda, & References
• Exam 1 is on Wed. Oct 3 • One double-sided 8.5x11 notes page allowed • Bring your calculator
• PLL Acquisition
• Chapter 5 & 8 of Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005.
• Chapter 4 of Phase-Locked Loops for Wireless Communications, D. Stephens, Kluwer, 2002. 2
PLL Frequency Step Response: Linear vs Behavioral Model
3
θref(s)=Frequency Step Input: ∆ωs2 = ∆510 Mrad/sec
32s2
No Cycle Slips Observedwith Linear Model
Cycle Slips
• Due to non-linearities in loop components (primarily the PD), a real PLL’s response can vary significantly from the linear model
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
4
( )
( )
( )
orefref
o
ePD
cVCOo
t
K
tvK
KsF
ωωωω
ω
φ
ω
−=∆
+
==
and is phaseinput
thesuch that , fromdifferent frequency aat is signalinput theAssume
sin :OutputDetector Phase Sinusoidal
:Frequency ousInstantane VCO
1
PD sinusoidal a with PLLorder -first simple a Assuming
1
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
5
( ) ( ) ( ) ( )( ) ( )
( ) ( )( ) ( )
( ) ( )( ) PDVCOee
out
t
oePDVCOorefoutrefe
out
t
oePDVCOoout
t
ocVCOoout
KKKtKdt
t
dKKt
dKKtdvKtt
=−∆=
−−−=−=
++=++=
∫
∫∫
wheresind
equation aldifferentinonlinear following theyields time w.r.t. thisatingDifferenti
0sin
iserror phase PLL The
0sin0
is phaseoutput PLL The
φωφ
φττφωωφφφ
φττφωφττωφ
6
First-Order PLL Hold Range (Sinusoidal PD)
( ) ( )( )
( )
K
K
Kdt
t
e
ee
≤∆
∆=
=−∆=
ω
ωφ
τφωφ
todconstraine isfrequency lock the,1 exceedcannot sine Since
sin
0sind
locked, is PLL theIf
( )rad/sec :Range Hold KH <∆ω
7
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
( )ee
KKφωφ sin
Kby equation aldifferenti PLLorder -first thegNormalizin
−∆
=•
unstable are nulls slope-positive while
points,lock stable are nulls slope-Negative
0 wherenulls 2 are thereplot, plane-phase In the =dt
d eφ
• Every cycle (2π interval) contains a stable null, thus φe cannot change by more than one cycle before locking
• There is no cycle slipping in the locking process • A cycle slip occurs when the phase error changes by more
than 2π without locking
8
First-Order PLL Phaselock Acquisition Time (Sinusoidal PD)
( ) ( )( ) ( )
( ) ( )
( ) ( )
( )
tlysignifican increasecan andion approximatlinear thisfrom
deviate willresponse thelarge, is 0 if However,
0
response step phase modellinear theissolution eapproximat the
,sinsuch that small, is 0 and zero is If
0sin
solveformally toneed we time,acquistionphaselock thefind order toIn
e
Ktoute
eee
out
t
oePDVCOe
et
dKKtt
φ
φφ
φφφω
φττφωφ
−−=
≈∆
−−∆= ∫
• If the frequency offset exceeds the PLL hold range, the phase error will oscillate asymmetrically as the PLL undergoes cycle slips
9
First-Order PLL Lock Failure (Sinusoidal PD)
First-Order PLL VCO Control Voltage
( )rad/sec :Range Hold KH <∆ω
Second-Order Type-2 PLL Phaselock Acquisition (Sinusoidal PD)
10
( )
( ) ( ) ( ) ( )( ) ( )( )
( ) ( ) ( ) ( )( ) ( )( ) ( )0sin1sin0
is phaseoutput PLL The
sin1sin1
as expressed becan domain - timein the responsefilter The
11
PD sinusoidal a with PLL 2-order type-second a Assuming
0 010 1
2
011
2
011
2
11
2
1
2
out
t t
e
t
ePDVCOoout
t
ocVCOoout
t
ePDePD
t
eec
dddKKtdvKtt
dKKdvtvtv
ssssF
φτττφτ
ττφττωφττωφ
ττφτ
τφττττ
τττ
τττ
ττ
+
++=++=
+=+=
+=+
=
∫ ∫∫∫
∫∫
Second-Order Type-2 PLL Phaselock Acquisition (Sinusoidal PD)
11
( ) ( )( ) ( )( ) ( )
( ) ( )
+−=
−
+−−=−=
•••
∫ ∫∫
eeePDVCOe
out
t t
e
t
ePDVCOorefoutrefe
KK
dddKKt
φτ
φφττφ
φτττφτ
ττφττωωφφφ
sin1cos
equation aldifferentinonlinear following theyields time w.r.t. twice thisatingDifferenti
0sin1sin
iserror phase PLL The
11
2
0 010 1
2
Second-Order Type-2 PLL Phaselock Acquisition (Sinusoidal PD)
12
( ) ( ) 0sincos2
following theyieldsequation aldifferentinonlinear theinto thisngSubstituti
4 ,
arefactor damping andfrequency natural thePLL, 2-TypeOrder -Second For this
2
1
22
1
2
=++
==
•••
eneene
VCOPDVCOPDn
KKKK
φωφφζωφ
ττζ
τω
• No closed form solution exists, and numerical techniques are required to solve
Second-Order Type-2 PLL Phaselock Acquisition (Sinusoidal PD)
13
( ) ( ) 0sincos2 2 =++•••
eneene φωφφζωφ
Acquisition with a phase error
time vs and •
ee φφee φφ vs :Plot Plane Phase
•
Second-Order PLL Phase Plane Plots (Sinusoidal PD)
14
( ) ( ) 0sincos2 2 =++•••
eneene φωφφζωφ
• An unstable singularity is called a Saddle Point
• A trajectory that terminates on a saddle point is called a “Separatrix”
• If a trajectory lies between the 2 separatrices, it will lock without cycle slipping
• If a trajectory lies outside the 2 separatrices, it will cycle slippling one or more times before locking (if at all)
Second-Order PLL Pull-Out Range and Lock Time (Sinusoidal PD)
15
( )
( )
( )
( )
(Hz) 41
2
,11 Assuming
(Hz)
bandwidth noise PLL theis Here,
10% than lesserror phasefor
2.44
as edapproximat becan timeacquistion PLL therange,out -pull than theless is stepfrequency a If
1.4 and 0.5between for
18.1
11
2
1
2
0
2
3
2
+=
+=+
=
=
∆+=+=
+≈∆
∫∞
ζζω
τττ
ττ
ω
ζ
ζωω
nL
L
L
Lnfreqphaseacq
nPO
B
ssssF
dffHB
B
Bfttt
• The Pull-Out Range is the maximum frequency step that can occur before the loop locks without cycle slipping
Second-Order PLL Locking Outside of the Pull-Out Range (Sinusoidal PD)
16
• Multiple cycle slips are observed before the loop locks
Next Time
• Phase Detector Circuits
17