DEVELOPMENT OF CLOSED-LOOP INTERFACE CIRCUITS FOR CAPACITIVETRANSDUCERS WITH APPLICATION TO A MEMS CAPACITIVE MICROPHONE

By

KARTHIK KADIRVEL

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOLOF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2007

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c© 2007 Karthik Kadirvel

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To my parents, sister and Sona

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ACKNOWLEDGMENTS

I would like to thank my advisor and mentor Dr. Toshikazu Nishida for his constant

motivation and encouragement to bring out the best in me. This research would not have

been possible without his logical approach to problem solving and emphasis on fundamental

principles. Dr. Mark Sheplak and Dr. Robert Fox provided indispensable help on MEMS

processing and circuit design respectively at various points during this research . The many

discussions with Dr. Louis N. Cattafesta on control theory provided valuable information at

crucial junctures of this research.

I would like to thank my project colleagues David Martin for providing me with a MEMS

microphone to use as a test vehicle for the circuit development, Jian Liu for the help in modeling

using Matlab and Joel Fuster for the various board level circuit design ideas.

I would like to thank all my friends at the Interdisciplinary Microsystems Group for their

friendship and support during the course of my graduate program. Special mention goes to

Robert Taylor, Erin Patrick, and Stephen Horowitz for all their help.

Mr. T.K Sundaram, my high school mathematics and physics instructor, deserves special

mention here. I would like to extend my heartfelt thanks and gratitude for providing me with the

strong foundation on which all my achievements stand.

The help provided by Al Ogden, Ivan Kravachenko and Bill Lewis of the UF Nano

fabrication facilities and Ken Reed of TMR Engineering is gratefully acknowledged.

Finally, and most important I would like to thank my family and my wife for believing in

all my goals and aspirations and, for their love, encouragement, and constant support in all my

endeavors.

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TABLE OF CONTENTS

page

ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CHAPTER

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.2 Research Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.3 Dissertation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2 CAPACITANCE TRANSDUCERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.2 Canonical Capacitive Transducers . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.1 Single Backplate Capacitive Transducers . . . . . . . . . . . . . . . . . . 242.2.2 Canonical Dual Backplate Capacitive Transducer . . . . . . . . . . . . . 33

2.3 Structure of Microphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.4 Lumped Element Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3 INTERFACE CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.2 Performance Metrics of Capacitive Transducers . . . . . . . . . . . . . . . . . . 463.3 Analog Open Loop Sense Techniques . . . . . . . . . . . . . . . . . . . . . . . 51

3.3.1 Sensing Using A Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . 523.3.2 Sensing Using A Charge Amplifier . . . . . . . . . . . . . . . . . . . . . 653.3.3 Sensing Using Synchronous Modulation/Demodulation . . . . . . . . . . 72

3.4 Digital Open Loop Sense Techniques . . . . . . . . . . . . . . . . . . . . . . . . 803.5 Closed-Loop Sense Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.5.1 Sensing Using Closed-Loop Analog Interface Circuit . . . . . . . . . . . 863.5.2 Sensing Using Digital closed-loop Interface Technique . . . . . . . . . . 91

3.6 Scaling Analysis of ∆Σ Interface Techniques . . . . . . . . . . . . . . . . . . . 933.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4 DESIGN OF ANALOG INTERFACE CIRCUIT . . . . . . . . . . . . . . . . . . . . 97

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.2.1 Simulink Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984.2.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.3 Design of Analog Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 1034.3.1 Design of Amplifier for Top and Bottom Plate Voltage Generation . . . . 1034.3.2 Input Buffer Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . 105

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4.3.3 Demodulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064.3.4 Compensator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.4 Integration of Interface Circuit Components on a PCB . . . . . . . . . . . . . . . 1084.5 Noise model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094.6 Limitations of the Current Implementation of the Interface Circuit . . . . . . . . 1124.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5 DESIGN OF DIGITAL CLOSED LOOP INTERFACE CIRCUIT . . . . . . . . . . . 113

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.2 Design of ∆Σ Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.3 Component Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.3.1 Switched Capacitor Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 1165.3.2 Compensator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205.3.3 Comparator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.3.4 Bias Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.4 System Level Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245.5 System Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275.6 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6 EXPERIMENTAL SETUP AND RESULTS . . . . . . . . . . . . . . . . . . . . . . . 131

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316.2 Acoustic Pressure Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.2.1 Design of Acoustic Pressure Coupler . . . . . . . . . . . . . . . . . . . . 1326.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.3.1 Characterization of Pressure Coupler . . . . . . . . . . . . . . . . . . . . 1336.3.2 Open Loop Frequency Response of Microphone with dc Bias . . . . . . . 1366.3.3 Open Loop Frequency Response of Microphone with dc+ac Bias . . . . . 1376.3.4 Linearity of Open Loop Microphone . . . . . . . . . . . . . . . . . . . . 1396.3.5 Noise Floor of Open Loop Microphone . . . . . . . . . . . . . . . . . . . 1406.3.6 Compensator Characterization . . . . . . . . . . . . . . . . . . . . . . . 1416.3.7 Closed Loop Frequency Response . . . . . . . . . . . . . . . . . . . . . 1426.3.8 Closed Loop Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446.3.9 Closed Loop Noise Floor . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7 CONCLUSION AND FUTURE WORK . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.2.1 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 151

A PERFORMANCE METRICS FORMULATION . . . . . . . . . . . . . . . . . . . . . 152

A.1 Derivation of Sensitivity for a Voltage Follower . . . . . . . . . . . . . . . . . . 152A.2 Noise Analysis for a Capacitive Microphone with a Voltage Follower . . . . . . . 154A.3 Derivation of Sensitivity for a Charge Amplifier . . . . . . . . . . . . . . . . . . 156

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A.4 Noise Analysis for a Capacitive Microphone with a Charge Amplifier . . . . . . 157A.5 Sensitivity for Synchronous Modulation and Demodulation Interface Circuit . . 158

B FORMULATION USED IN SWITCHED CAPACITOR CIRCUITS . . . . . . . . . . 162

B.1 Bandwidth Considerations for Amplifiers in Switched Capacitor Amplifiers . . . 162B.2 Analysis of Noise in a Switched Capacitor Amplifier . . . . . . . . . . . . . . . 162

B.2.1 Switch Resistance Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 163B.2.2 Wideband Amplifier Noise . . . . . . . . . . . . . . . . . . . . . . . . . 163

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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LIST OF TABLES

Table page

1-1 Comparison of audio and aeroacoustic microphone specifications . . . . . . . . . . . . 21

2-1 Dimensions of aeroacoustic and audio microphone[64]. . . . . . . . . . . . . . . . . . 40

2-2 Material properties of microphone structure. . . . . . . . . . . . . . . . . . . . . . . . 40

2-3 Theoretical formulation for lumped element model parameters. . . . . . . . . . . . . . 43

2-4 Lumped element model parameters of aeroacoustic and audio microphone. . . . . . . . 43

2-5 Second order system parameters of microphones. . . . . . . . . . . . . . . . . . . . . 44

3-1 Parasitic capacitance for various packaging technologies. . . . . . . . . . . . . . . . . 54

3-2 Specification of Voltage Amplifiers for Bruel and Kjaer Microphones. . . . . . . . . . 61

3-3 Review of interface circuits used in MEMS microphones published in literature. . . . . 63

3-4 Specification of a representative sample of operational amplifiers recommended bymanufacturers for use as voltage followers for capacitive transducers. . . . . . . . . . . 65

3-5 Review of charge amplifier interface circuits used in capacitive microphones. . . . . . 72

3-6 Specification of a representative sample of general purpose operational amplifiersrecommended by the manufacturer for use as charge amplifiers using a feedback resistorand capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3-7 Summary of previous synchronous modulation/demodulation based open loop capacitivetransducer interface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3-8 Summary of previous synchronous modulation/demodulation based closed-loop capacitivetransducer interface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3-9 Frequency requirements of ∆Σ interface circuits with increasing resonant frequency. . 94

3-10 Feedback voltage requirements of ∆Σ interface circuits with increasing dynamic range. 94

3-11 Summary of previous ∆Σ based closed-loop capacitive transducer interface circuit. . . 95

4-1 Feedback voltage requirements of aeroacoustic and audio microphone for force balancingmaximum input pressure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4-2 Element values for resistors and capacitors used in compensator. . . . . . . . . . . . . 107

4-3 Magnitude of parameters used in noise analysis . . . . . . . . . . . . . . . . . . . . . 110

5-1 Clock signals used in the various components of the ∆Σ modulator. . . . . . . . . . . 125

5-2 Function performed during each time interval. . . . . . . . . . . . . . . . . . . . . . . 127

5-3 Parameters used in closed loop simulation. . . . . . . . . . . . . . . . . . . . . . . . . 128

5-4 Frequency requirements of ∆Σ interface circuits with increasing resonant frequency. . 129

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5-5 Feedback voltage requirements of ∆Σ interface circuits with increasing dynamic range. 129

6-1 Comparison of simulated and experimental sensitivity. . . . . . . . . . . . . . . . . . 139

6-2 Characterization results of microphone in open and closed loop mode of operation. . . 148

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LIST OF FIGURES

Figure page

1-1 Microphone classification based on sensor structure. . . . . . . . . . . . . . . . . . . . 19

1-2 Common condenser microphone structures. . . . . . . . . . . . . . . . . . . . . . . . 20

1-3 Microphone classification based on sense technique. . . . . . . . . . . . . . . . . . . . 21

2-1 Overview of Chapter 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2-2 Schematic of a single backplate capacitive transducer. . . . . . . . . . . . . . . . . . . 24

2-3 Schematic of a single backplate capacitive transducer connected to a voltage buffer. . . 26

2-4 Schematic of a single backplate capacitive transducer connected to a charge amplifier. . 28

2-5 Schematic of a single backplate capacitive transducer showing electrostatic force andrestoring force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2-6 Schematic of a differential capacitive transducer. . . . . . . . . . . . . . . . . . . . . . 33

2-7 Schematic of a dual backplate capacitive transducer connected to a voltage amplifier. . 36

2-8 Schematic of a dual backplate capacitive transducer connected to a charge amplifier. . . 36

2-9 Schematic of a dual backplate capacitive transducer showing forces on the movableplate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2-10 Cross section view of dual backplate microphone [64]. . . . . . . . . . . . . . . . . . 40

2-11 Low frequency LEM of dual backplate microphone. . . . . . . . . . . . . . . . . . . . 43

2-12 Theoretical normalized frequency response of audio microphone. . . . . . . . . . . . . 44

2-13 Theoretical normalized frequency response of aeroacoustic microphone. . . . . . . . . 45

3-1 Overview of Chapter 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3-2 Characteristic frequency response of a capacitive transducer. . . . . . . . . . . . . . . 48

3-3 Characteristic ideal and actual response of a capacitive transducer. . . . . . . . . . . . 48

3-4 Characteristic noise floor of a capacitive transducer using a voltage amplifier interfacecircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3-5 Noise model of resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3-6 Noise model of opamp showing voltage and current noise source. . . . . . . . . . . . . 51

3-7 Plot of noise PSD of amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3-8 Organization of each interface circuit discussed in Chapter 3. . . . . . . . . . . . . . . 53

3-9 Schematic of a dual backplate microphone connected to voltage buffer. . . . . . . . . . 53

3-10 Noise model of dual backplate microphone connected to voltage buffer. . . . . . . . . 55

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3-11 Variation of sensitivity as a function of total parasitic capacitance for various sensecapacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3-12 Power spectral density of individual noise contributors and total output noise in a voltageamplifier based interface circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3-13 Plot of output noise for voltage amplifier with a fixed bias resistor (10MΩ) . . . . . . 59

3-14 Plot of output noise for voltage amplifier with a fixed parasitic capacitance of (10pF ). . 60

3-15 Schematic of dual backplate microphone connected to a charge amplifier. . . . . . . . 66

3-16 Noise model of dual backplate microphone connected to charge amplifier. . . . . . . . 66

3-17 Power spectral density of individual noise contributors and total output noise in a chargeamplifier based interface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3-18 Plot of output noise for charge amplifier with a fixed bias resistor (10MΩ) . . . . . . . 70

3-19 Plot of output noise for charge amplifier with a fixed parasitic capacitance of (10pF ). . 71

3-20 Schematic of capacitive microphone with a synchronous modulation and demodulationtechnique using a voltage amplifier based circuit. . . . . . . . . . . . . . . . . . . . . 73

3-21 Schematic of a capacitive microphone with a synchronous modulation and demodulationtechnique using a charge amplifier based circuit. . . . . . . . . . . . . . . . . . . . . . 73

3-22 Plot of spectrum at various nodes of Figure 3-21 . . . . . . . . . . . . . . . . . . . . . 74

3-23 Noise model of synchronous modulator and demodulator using voltage amplifier. . . . 77

3-24 Noise model of synchronous modulator and demodulator using charge amplifier. . . . . 77

3-25 Switched capacitor implementation of correlated double sampling. . . . . . . . . . . . 81

3-26 Equivalent circuit of switched capacitor amplifier during amplify and reset phase. . . . 82

3-27 Noise model of switched capacitor amplifier during amplify phase. . . . . . . . . . . . 82

3-28 Schematic of analog closed-loop force feedback scheme. . . . . . . . . . . . . . . . . 87

3-29 Schematic of first order ∆Σ modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3-30 Schematic of second order mechanical ∆Σ modulator. . . . . . . . . . . . . . . . . . 92

4-1 Overview of Chapter 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4-2 Block diagram of analog closed-loop system showing microphone and interface circuit. 98

4-3 Bode plot of compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4-4 Bode plot of loop gain with and without compensator. . . . . . . . . . . . . . . . . . . 102

4-5 Simulink model of analog closed-loop control system. . . . . . . . . . . . . . . . . . . 102

4-6 Subsystems used in Simulink model. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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4-7 Diaphragm displacement with and without feedback. . . . . . . . . . . . . . . . . . . 104

4-8 Diaphragm displacement with and without feedback. . . . . . . . . . . . . . . . . . . 104

4-9 Schematic of summing amplifier that generates top and bottom plate voltages. . . . . . 105

4-10 Schematic of voltage amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4-11 Schematic of analog multiplier (AD835) showing relevant pins. . . . . . . . . . . . . . 106

4-12 Schematic of two stage compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4-13 Annotated photograph of PCB1 showing buffer amplifier, breakout headers and opticalport. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4-14 Annotated photograph of PCB2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4-15 Schematic of forward path of the closed loop system . . . . . . . . . . . . . . . . . . 109

4-16 Plot of theoretical noise floor of the open loop system and forward path system . . . . 111

5-1 Overview of Chapter 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5-2 Flow chart for design of ∆Σ modulator component parameters from system levelspecification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5-3 Schematic of second order mechanical ∆Σ modulator. . . . . . . . . . . . . . . . . . 115

5-4 Transistor level schematic of amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5-5 Schematic of amplifier during amplify phase. . . . . . . . . . . . . . . . . . . . . . . 118

5-6 Transistor level schematic of compensator. . . . . . . . . . . . . . . . . . . . . . . . . 121

5-7 Compensator schematic during the two phases of operation. . . . . . . . . . . . . . . . 122

5-8 Transistor level schematic of comparator . . . . . . . . . . . . . . . . . . . . . . . . . 123

5-9 Schematic of bias network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5-10 Flowchart showing the sequence of operation of the overall ∆Σ modulation basedinterface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5-11 Schematic of ∆Σ modulator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5-12 System level timing diagram over one complete cycle. . . . . . . . . . . . . . . . . . . 127

5-13 Simulink Model of the ∆Σ modulator based interface circuit. . . . . . . . . . . . . . . 128

5-14 Power spectral density of output ∆Σ modulated bitstream. . . . . . . . . . . . . . . . 129

6-1 Overview of Chapter 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6-2 Photograph of acoustic pressure coupler. . . . . . . . . . . . . . . . . . . . . . . . . . 132

6-3 Plot of input pressure signal as a function of frequency. . . . . . . . . . . . . . . . . . 134

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6-4 Comparison of frequency response of pressure coupler with air as medium and withhelium as medium. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6-5 Block diagram describing characterization procedure used. . . . . . . . . . . . . . . . 135

6-6 Frequency response with dc bias (5V ) with air medium. . . . . . . . . . . . . . . . . . 136

6-7 Frequency response with dc bias (5V ) with helium medium. . . . . . . . . . . . . . . 137

6-8 Schematic of capacitive microphone with a synchronous modulation and demodulationtechnique using a voltage amplifier based circuit. . . . . . . . . . . . . . . . . . . . . 137

6-9 Open loop frequency response measured at the output of low pass filter. . . . . . . . . 138

6-10 Open loop frequency response normalized to the peak ac voltage measured at the outputof low pass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6-11 Open loop linearity of the open loop system. . . . . . . . . . . . . . . . . . . . . . . 139

6-12 Linearity of the open loop system normalized to peak ac bias voltage measured at theoutput of the demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6-13 Noise floor of microphone for two different ac bias voltages measured at the outputof the demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6-14 Theoretical and experimental frequency response of compensator. . . . . . . . . . . . 142

6-15 Block diagram of analog closed-loop system showing microphone and interface circuit. 142

6-16 Closed loop frequency response measured at the output of demodulator . . . . . . . . 143

6-17 Closed loop frequency response measured at the output of demodulator with ac biasof 6Vpp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6-18 Closed loop frequency response measured at the output of demodulator with ac biasof 9Vpp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6-19 Closed loop frequency response measured at the output of compensator. . . . . . . . . 146

6-20 Linear range of system in closed loop configuration as measured at the output of thecompensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6-21 Linearity of the closed loop system normalized to peak ac bias voltage measured atthe output of the compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6-22 Closed loop noise floor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

A-1 Noise model of dual backplate microphone connected to voltage buffer. . . . . . . . . 152

A-2 Noise model of dual backplate microphone connected to voltage buffer. . . . . . . . . 155

A-3 Noise model of dual backplate microphone connected to charge amplifier. . . . . . . . 157

B-1 Noise model of switched capacitor amplifier during amplify phase. . . . . . . . . . . . 162

13

Abstract of Dissertation Presented to the Graduate Schoolof the University of Florida in Partial Fulfillment of theRequirements for the Degree of Doctor of Philosophy

DEVELOPMENT OF CLOSED-LOOP INTERFACE CIRCUITS FOR CAPACITIVETRANSDUCERS WITH APPLICATION TO A MEMS CAPACITIVE MICROPHONE

By

Karthik Kadirvel

December 2007

Chair: Toshikazu NishidaMajor: Electrical and Computer Engineering

There has been a trend towards miniaturization and batch fabrication of sensors inspired

by a similar trend in the electronics industry using novel fabrication techniques used in micro

electromechanical system (MEMS) fabrication. Capacitive microphones, whose common

applications include aeroacoustic measurement and cell phones, is one such sensor whose

dimensions are being aggressively scaled down. In measurement microphones, miniaturization

will facilitate improved measurement precision, and in cell phones, miniaturization will reduce

printer circuit board space and complexity. Both applications will benefit from the potential cost

reduction brought by the batch fabrication of sensors.

As sensor geometry is scaled down, improved circuit techniques are required to measure the

sensor output. This is because at small geometries sensor capacitance is comparable to unwanted

parasitic capacitance which reduces the transducer sensitivity. Also, at reduced sensor geometry,

the voltage required to bias the microphone could cause the microphone plates to pull in. The

goal of this work is to design and characterize interface circuits that are suitable for miniature

capacitive transducers. To achieve this goal, the performance of existing open and closed-loop

interface circuits are investigated. Scaling of the performance metrics of the microphone and

interface circuit as sensor geometry decreases is also investigated.

A proof of concept closed-loop analog controller for a MEMS capacitive microphone

is designed. A test apparatus is developed to characterize the system over the audio range

by operating the microphone in a helium medium which increases the bandwidth of the test

apparatus. Characterization of the microphone in open and closed loop mode of operation is

14

presented. Results show that stable closed loop operation of the microphone is feasible with

increased sensitivity and the potential to address pull-in issues.

15

CHAPTER 1INTRODUCTION

There has a been a major trend towards miniaturization and batch fabrication of transducers

inspired by a similar trend in the electronics industry. With the advent of micromachining [1]

techniques used in microelectromechanical system, (MEMS) manufacturing, fabrication of

transducers with very small sizes have been made possible. Micromachining also facilitates the

batch fabrication of devices which possess nearly matched structural and electrical properties.

Batch fabrication of devices also can reduce the cost of manufacturing if the volume is large

enough.

One key transducer leading the way in this trend are capacitive transducers. Capacitive

transducers are devices that respond to physical phenomenon via a change in capacitance

that is measured using various interface circuits. Commercially successful applications that

utilize capacitive transducers include accelerometers used in air bag deployment system for

cars and laptop hard drives by Analog Devices [2], projection technology for large screen TVs

using Texas Instruments Digital Light Processing (DLP) processors [3], pressure sensors by

Freescale Semiconductors [4], and audio microphones for cell phones by Knowles Acoustics

[5]. Other capacitive transducers published in the literature include accelerometers [2],[6] –[11],

micro-mirrors [12], microphones [13] – [21], pressure sensors [22] – [25], oscillators [26] –

[31], and gyroscopes [32] – [35]. In all these applications, the capacitance change of the sensor

is converted into a usable voltage using interface circuits [36] such as the voltage buffer [37] –

[40], charge amplifier [41], ac bridge [6], force balancing circuits [6, 8, 42], and oscillator based

circuits[43] – [45].

The miniaturization of capacitive transducers results in new challenges for the design of the

interface circuits. Some of the issues that are exacerbated at small sensor geometries that make

the design of interface circuits more challenging include a parasitic capacitance comparable to

the sensor capacitance, reduced sensitivity, and pull in [46]. All of these factors can degrade the

performance of micromachined capacitive transducers. As we scale down aggressively from

micro scale devices in MEMS systems to nano scale devices, an understanding of the tradeoffs of

interface circuits is important to obtain the full performance benefits of the miniature capacitive

transducer.

16

The overall topic of my work is the study of interface circuits for a specific class of

capacitive transducers namely capacitive microphones. Traditionally, capacitive microphone

interface circuitry consisted primarily of voltage amplifiers . For example, commonly used

instrumentation grade capacitive microphones for aeroacoustic applications, the Bruel and

KjærType 4134 and Type 4138 series of microphones [38], use a voltage buffer amplifier as the

interface circuit. Capacitive microphones used over the audio bandwidth (20Hz − 20kHz) such

as the Bruel and KjærType 4135 microphone also use a voltage buffer as the interface circuit.

Commercial MEMS microphones that use voltage buffers include the SiSonic microphones [5]

manufactured by Knowles acoustics and DigiSiMic microphones [47] by Sonion Technologies.

Though voltage amplifier interface circuits are commonly used, there exist other interface

techniques that may possess advantages for high performance capacitive transducers in certain

applications. For example, since capacitive accelerometers are similar in operating principle and

structure as compared to capacitive microphones circuits used for accelerometers may be adapted

for use in capacitive microphones. A closed-loop interface interface circuit technique used in

some accelerometers, [2], may provide benefits such as improved pull-in performance, higher

sensitivity, and direct digital output. This provides the motivation for investigating the potential

advantages and disadvantages for closed-loop interface circuits for capacitive microphones.

To achieve these goals, a thorough understanding of the theoretical performance of existing

capacitive interface techniques is required. Although previous work [48], [49], review interface

techniques such as voltage buffer, charge amplifier, synchronous modulation and demodulation,

they do not provide detailed theoretical formulations to compare the various techniques. In

addition, closed loop interface circuits are not discussed in detail.

The goal of my work is to design and evaluate capacitive interface circuits with an emphasis

on closed-loop interface circuits for MEMS capacitive microphones. To achieve this goal, the

performance of existing open and closed-loop interface circuits are investigated. Theoretical

formulations for the performance metrics of the interface circuits are derived and compiled

into a common framework for comparison. Using the information obtained, a proof of concept

closed-loop analog controller for a MEMS capacitive microphone is designed.

17

1.1 Background

This section begins a brief introduction to the operating principle of a capacitive microphone.

Various commonly used microphone structures are then described. A preliminary overview and

a brief literature review of the microphone interface circuits is presented in this section. This

section concludes with a flow chart showing the various interface circuits which forms the

framework for Chapter 2. A detailed literature review along with theoretical formulations for

each of the interface circuits is presented in Chapter 2.

A microphone is a transducer that converts input acoustical energy into corresponding

electrical energy. Capacitive microphones consist of a flexible diaphragm that is exposed to

the pressure fluctuations of the acoustic field of interest and one or more fixed backplates. The

pressure induced structural deflection of the diaphragm causes a variation in the capacitance

between the vibrating diaphragm and the fixed backplates which is detected and measured.

There are two main ways of measuring the capacitance change. The two approaches are

based on the fundamental equation that relates the charge Q stored on the capacitor plates to the

capacitance C and the voltage V across the plates of the capacitor,

Q = CV. (1–1)

In the fixed charge scheme [14], [50] – [52] the, charge is held constant and the voltage change

associated with the capacitance change is measured. The charge is held constant by using

a dc voltage source to bias the capacitor or by using a special dielectric material (electret)

such as polypropylene, mylar, or silicon dioxide that can hold charge for long periods of time

measured in years. The electret material is bonded either to the movable diaphragm or to the

fixed backplate which is charged with a high potential of hundreds of volts using an external

dc source. The main advantage of electret microphones is that they do not require an external

power supply and are thus useful for portable applications [53]. The fixed voltage that can be

generated by the charge on the electret is much higher than what can be achieved via a battery

which leads to a higher sensitivity. The main disadvantages of micromachined electrets are that

the micromachined electret materials lose their charge over time when exposed to humidity [16].

In the fixed voltage scheme, a fixed voltage is maintained using an external voltage source while

18

the charge transfer associated with the capacitance change is measured. The externally applied

voltage is known as the ’polarization voltage’.

Capacitive microphones can be broadly classified based on the structure and on the detection

mechanism. Figure 1-1 shows a classification tree of the common capacitive microphone

structure. Based on the structure, they can be classified as single back plate and dual backplate

microphones. Various authors have reported single backplate microphones [17, 21], [54] – [60]

and dual back plate microphones [19],[61] – [64] in the literature. A schematic of the common

microphone structures is shown in Figure 1-2.

Most commercial MEMS [5, 47] and non-MEMS [38] microphones use a single backplate

design. In these microphones, a single variable capacitor is formed between the fixed backplate

and the movable plate that is measured by the interface circuit. In dual backplate and dual

diaphragm microphones, two capacitors that vary differentially are formed. Dual backplate and

dual diaphragm microphones have certain advantages such as increased sensitivity as compared

to single backplate microphones, a higher bias voltage which increases the sensitivity, improved

pull in performance, and increased linearity but are more complex to fabricate and have higher

cost. SingleBackplate DualBackplateSingleDiaphragm DualDiaphragmCondenserMicrophone

Figure 1-1. Microphone classification based on sensor structure.

Figure 1-3 shows a classification tree of the various capacitive microphone interface

techniques. Based on the sensing scheme, microphones can be broadly divided into open

loop [41, 59, 65, 66] and closed loop [6] – [8],[10, 60], [67] – [69] categories. Both of these

categories can be further divided into analog and digital techniques based on the presence or

19

Backplate

Pressure Equalization Vent

Backchamber Acoustic Hole

Air Gap

Diaphragm

(a) Schematic of single backplate single diaphragmmicrophone[55].

Bottom Diaphragm

Top Diaphragm

Pressure Equalization Vent

Backchamber Acoustic Hole

Air Gap

Backplate

(b) Schematic of single backplate dual diaphragmmicrophone[55].

Bottom Backplate

Top Backplate

Pressure Equalization Vent

Backchamber Acoustic Hole

Air Gap

Diaphragm

(c) Schematic of dual backplate single diaphragmmicrophone[55].

Figure 1-2. Common condenser microphone structures.

absence of a clock signal, respectively. A detailed literature review, principle of operation, and

performance metrics of each of these circuits is discussed in Section 2.2 to Section 2.5.

1.2 Research Objectives

The goal of this work is to design a closed-loop force feedback interface circuit for a MEMS

capacitive microphone. Capacitive microphones with two different target applications namely,

aeroacoustic applications and audio applications, are the theoretical testbeds for characterizing

these circuits. The target specification for the two microphones are listed in Table 1-1. These

specifications provide typical values for the various parameters. The actual values depend

upon the application. For example, telephony applications require audio microphones with

20

CondenserMicrophoneOpenLoop ClosedLoopSwitchedCapacitor SynchronousMod/DemodAnalog Digital DigitalAnalog SigmaDeltaSynchronousMod/DemodVoltageBuffer ChargeAmplifierFigure 1-3. Microphone classification based on sense technique.

a bandwidth of 300Hz − 3.4kHz while hearing aid microphones have a bandwidth of

20 Hz-20 kHz. Also, in the table, it is assumed that the dynamic range is 100dB. To aid in

Table 1-1. Comparison of audio and aeroacoustic microphone specificationsProperty Audio Microphone Aeroacoustic

MicrophoneMax Pressure 120 dB 160 dB

Bandwidth∗ 20 Hz-20 kHz 45 Hz-160 kHz

Noise Floor 20 dB 60 dB∗100dB dynamicrange is assumed

the design of the overall system, a detailed model of the microphone and the interface circuit has

been developed. Theoretical formulations for the sensitivity, frequency response, and minimum

detectable signal (MDS) of the microphone along with the interface circuit system have been

derived. The theoretical parameters are compared with simulation and experimental results by

characterizing the microphone and interface circuit in a acoustic pressure coupler.

1.3 Dissertation Overview

This dissertation is divided into seven chapters. Chapter 2 is an in-depth study of the

various capacitive transducer interface circuits. For each of the interface circuit techniques, the

literature is reviewed and the principle of operation and performance metrics are explained. Since

the design of the circuit depends on the characteristics of the capacitive transducer, Chapter 2

21

discusses the structure and specifications of two capacitive microphones used as the test vehicles

to theoretically evaluate the performance of the interface circuit. To aid in design and prediction

of the performance specifications, an electrical model of the overall system consisting of the

sensor along with the interface circuit is described. Furthermore, a reduced order lumped element

model of the microphone is described for use in multi-domain simulations.

Chapter 3 discusses various open and closed loop interface circuits for capacitive

transducers with an emphasis on capacitive microphones. Theoretical formulations for the

performance metrics of the interface circuits are developed.

Chapter 4 and Chapter 5 detail the design and simulation of the analog and digital

closed-loop interface circuits respectively. The two interface circuits are compared in terms

of performance specifications, design complexity, ease of implementation, and cost. Chapter 5

concludes by presenting the reason for implementing an analog closed-loop interface circuit over

a digital closed-loop interface circuit.

In Chapter 6, the test apparatus used to characterize the performance of the interface circuit

is explained. Results of the characterization of the test apparatus is presented first followed by the

characterization results of the microphone with the analog open and closed loop interface circuit.

Chapter 7 discusses the results obtained along with the future work.

22

CHAPTER 2CAPACITANCE TRANSDUCERS

2.1 Introduction

In this chapter, canonical capacitive transducers are discussed followed by a discussion

of the microphone under consideration. Lumped element modeling of the sensor to facilitate

multi-domain simulation of the sensor along with the interface circuitry in the following chapter

is also discussed.

This chapter begins with a discussion of a canonical single backplate and dual backplate

capacitive transducer. Theoretic formulation of the voltage, charge, capacitance, and force

relations for the two canonical transducers are derived. Linearization of the formulation is also

presented. A discussion of the performance metrics of capacitive transducers is then presented.

The structural and material properties of the microphone under consideration are discussed

next. A lumped element model (LEM) is then developed for the microphone. Using the LEM, a

reduced second order system is developed which is used to extract the sensor resonant frequency

and damping coefficient. This chapter concludes with MATLAB simulations of the reduced order

models. A graphical overview of this chapter is shown in Figure 2-1.

Lumped elementmodellingStructural andmaterial propertiesof microphoneCanonicalcapacitivetransducersSummaryIntroduction

Audio microphoneAeroacousticmicrophoneSingle backplateDual backplate

Figure 2-1. Overview of Chapter 2.

2.2 Canonical Capacitive Transducers

In this section, the principle of operation of a single backplate and dual backplate capacitive

transducer is presented.

23

2.2.1 Single Backplate Capacitive Transducers

Structure and Principle of Operation. Figure 2-2 shows a simple single backplate

capacitive transducer. It consists of two plates that are at a nominal gap x0 between them. One

plate is fixed and the other plate is free to move in response to an input physical phenomenon.Fixed PlateMovable Plate x0 x'0 xxxFigure 2-2. Schematic of a single backplate capacitive transducer.

The plates are so arranged such that only the distance x between the plates can vary and not the

area of overlap A between the two plates. Under the application of an external pressure signal,

the diaphragm moves from its equilibrium position.

The distance between the plates can be expressed in terms of the nominal gap distance, x0,

and the instantaneous displacement from the nominal position, x′, by the equation

x = x0 − x′. (2–1)

The instantaneous capacitance C, between the plates is given in terms of the permitivity of free

space ε0, relative permitivity εr, area of overalap A, and the distance between the plates x, by

C =ε0εrA

x. (2–2)

For air gap, the relative permitivity is approximately unity. Substituting Equation 2–1 into the

previous equation, we obtain

C =ε0εrA

x0

[1

1− x′x0

]. (2–3)

Defining the nominal capacitance C0 as

C0 =ε0εrA

x0

, (2–4)

24

the instantaneous capacitance C can be rewritten as

C = C0

[1

1− x′x0

], (2–5)

i.e.,

C ∝[

1

1− x′x0

]. (2–6)

From Equation 2–5, it can be observed that there exists a non-linear relationship between the

capacitance and the distance between the plates. For small displacements (x′ << x0), using a

Taylor’s series expansion, Equation 2–5 can be linearized as

C = C0

[1 +

x′

x0

]. (2–7)

If the change in capacitance is denoted by ∆C, then

C = C0 + ∆C. (2–8)

Substituting for C from Equation 2–2 and C0 from Equation 2–4 in Equation 2–8, we obtain

∆C = C0x′

x0

. (2–9)

This shows that for small displacements, the change in capacitance is a linear function of the

change in gap distance. The next equation to consider is the relationship between the voltage V

across the plates of the capacitor and the charge Q stored across the plates of the capacitor which

is given by

V =Q

C. (2–10)

Substituting Equation 2–5 in the previous equation, we obtain

V =Q

C0

[1− x′

x0

]. (2–11)

From Equation 2–11, it can be seen that

V ∝ Qx′. (2–12)

This shows that the voltage across the plates of a capacitor is a product of two time dependent

variables. Hence, the voltage across the plates of the capacitor is a non-linear function of the

25

displacement and charge stored on the plates of the capacitor. Equation 2–12 equation can

be linearized by using either a fixed charge or a fixed voltage to measure the displacement.

These two linearization methods determine the choice of interface circuit. For the fixed charge

technique, a voltage amplifier is used. This is because for the fixed charge technique

V ∝ x′. (2–13)

For the fixed voltage technique, a charge amplifier is used. This is because for the fixed voltage

technique, the output is charge which will be shown to be linear with displacement after

integration by a charge amplifier. A preliminary discussion of the two interface techniques is

presented next. A detailed review of these two techniques along with detailed performance

metrics and a literature review is given in Section 3.3 and Section 3.3.2.

Linearization Using Fixed Charge (Voltage Amplifier Interface Circuit). In this

technique, a fixed charge is stored on the plates of the capacitor. The fixed charge can be

provided by a dc voltage source to bias the capacitor or by using a special material known as

an electret. An electret is a material that can store charge for long periods of time (measured

in years). The charge is applied onto the electret material using a technique called polarization

whereby a large (few 100s of volts) is applied to the electret material. Figure 2-3 shows a single

backplate capacitive transducer linearized using a fixed charge technique by connecting to a dc

voltage source Vdc. Vdc is connected to one end of the capacitive transducer. A bias resistor Rdc

Rdc -+ VoutC+VdcFigure 2-3. Schematic of a single backplate capacitive transducer connected to a voltage buffer.

is connected between the other end of the capacitive transducer and ground and is used to set the

dc operating point. A unity gain voltage amplifier is connected to the common point between the

26

resistor and the capacitor as shown in Figure 2-3. The fixed charge on the transducer is given by

the relation

Qdc = VdcC0. (2–14)

The RC network consisting of Rdc and C sets up a high pass filter with a cut in frequency of

12πRdcC

. For all frequencies above the cut in frequency, the voltage on the plate is free to change

which is buffered by the voltage amplifier and can be measured. Substituting Q with Qdc in

Equation 2–11, the voltage across the plates of the capacitor is given by

V =Qdc

C0

[1− x′

x0

]. (2–15)

The small signal output voltage Vout is given by

Vout = Vdcx′

x0

. (2–16)

From Equation 2–15, it can be seen that

Vout ∝ x′, (2–17)

which is a linear relation between the voltage and the change in gap distance. It should be

noted that in this discussion, the parasitic capacitances are neglected. The effect of parasitic

capacitances are discussed in Chapter 3.

Linearization Using Fixed Voltage (Charge Amplifier Interface Circuit). Figure 2-4

shows a single backplate capacitive transducer connected to a charge amplifier. In this technique,

the fixed voltage is provided by a DC voltage source Vdc which is connected to one end of the

capacitive transducer. The other end is connected to the inverting input of an inverting amplifier.

The inverting terminal of the amplifier is held at virtual ground due to negative feedback. A

feedback capacitor Cint is connected between the output of the amplifier and the inverting input.

This circuit integrates the charge flowing out of the transducer. A bias resistor Rdc is connected

in parallel to the feedback capacitor and is used to set the DC operating point. The RC network

consisting of Rdc and Cint sets up a high pass filter with a cut in frequency of 12πRdcCint

. For all

frequencies above the cut in frequency, the charge flowing from the transducer is integrated by

the feedback capacitor. The relation between the input and output of a charge amplifier above the

27

Cint+-RdcC+Vdc VoutFigure 2-4. Schematic of a single backplate capacitive transducer connected to a charge amplifier.

cut in frequency is given by

Vout = − C

Cint

Vdc (2–18)

Substituting for C from Equation 2–8 and Equation 2–9, Vout can be expressed as

Vout = − C0

Cint

Vdc − C0x′

x0

Vdc (2–19)

From Equation 2–19 it can be seen that

Vout ∝ x′, (2–20)

which is a linear relation between the output voltage and the change in gap distance. The effect

of parasitic capacitance on the output voltage is discussed in Chapter 3.

Force Relations. We now consider the force between the plates of the capacitor. By the

law of conservation of energy, the sum of the incremental change in electrical potential energy

dEe and the incremental change in mechanical potential energy dEm is zero, i.e.

dEe + dEm = 0. (2–21)

The incremental change in mechanical potential energy is given in terms of the force between the

two plates F and the incremental change in gap distance dx′ by

dEm = −Fdx′. (2–22)

28

The negative sign denotes that the force increases as gap distance decreases. Rewriting

Equation 2–22, we obtain

F = −dEe

dx′. (2–23)

Substituting Equation 2–21 in Equation 2–22, we obtain

Fe =dEe

dx′. (2–24)

The electrical potential energy stored across the plates of the capacitor Ee, is dependent on the

biasing technique used. If the capacitor is biased with a fixed voltage Vdc, then the energy stored

is given by the relation

Ee =1

2CV 2

dc. (2–25)

Substituting for C from Equation 2–2 and using Equation 2–25 in Equation 2–24, we obtain an

expression for the magnitude of the electrostatic force acting on the movable plate biased at Vdc

F∣∣∣Vdc

=1

2V 2

dc

εA

(x0 − x′)2 (2–26)

i.e.,

| Felectrostatic |∝ 1

(x0 − x′)2 . (2–27)

From Equation 2–27, it can be seen that the force between the plates of a capacitor is non-linearly

related to the gap. The direction of the electrostatic force is towards the fixed plate. The movable

plate comes closer to the fixed plate, the force will increase and approach infinity as gap distance

decreases. The force relation can be linearized for small displacements (x′ << xo) using a

Taylor series expansion as

~Felectrostatic

∣∣∣Vdc

∼= 1

2V 2

dc

εA

x20

(1 + 2

x′

x0

)(−x). (2–28)

If the plates are biased with a fixed charge, then the energy stored is given by the relation

Ee =Q2

dc

2C. (2–29)

Substituting for C from from Equation 2–2 and substituting Equation 2–29 in Equation 2–24 we

obtain

F∣∣∣Qdc

=Q2

dc

2εA(−x) (2–30)

29

This can be rewritten in terms of Vdc as

~Felectrostatic

∣∣∣Qdc

=1

2V 2

dc

εA

x20

(2–31)

From this equation, it can be seen that the force is independent of the displacement of the

movable plate for the fixed charge technique.

Quasistatic Pull-in. When the plates of a capacitive transducer are biased with a fixed

bias, it is possible for the plates of the transducer to collapse into each other if the potential

between them is large enough [46]. The reason for this is as follows. When a voltage is applied

to the plates, an electrostatic force attracts the movable plate towards the fixed plate. At small

voltages, this is balanced by the restoring force of the diaphragm. As the voltage is increased,

the electrostatic force between the plates keeps increasing. At some critical voltage, known as

the pull-in voltage VPI , the two plates will snap in. The study of the pull-in characteristics if

important to determine the maximum voltage Vdc that can be applied on the transducer plates.

The actual voltage used is much lower than the pull in limit to ensure stable operation of the

transducer. There are two main types of pull in.

1. Quasistatic Pull-in: In this type of pull-in the movable plate is initially at rest. No time

varying external force is applied on the movable plate.

2. Dynamic Pull-in : In this type of pull-in, a time varying external force is acting on the

movable plate and/or a time varying bias voltage [70].

In this discussion, only the quasi static case is considered. The pull-in voltage and the critical gap

at which pull-in occurs is derived next for the constant voltage and constant charge techniques.

Quasistatic Pull-in for Single Backplate Transducer with Fixed Voltage Biasing.

Figure 2-5 shows the fixed plate and movable plate along with the direction of forces. It can

be seen that the force due to electrostatic attraction Felectrostatic and the restoring spring force

Fspring oppose each other. The electrostatic force is always attractive and tries to bring both

plates together. The restoring force always tries to bring the movable plate back to its equilibrium

position. Based on the sign convention shown in the figure an increase in the electrostatic force

causes a decrease in gap distance.

30

Fixed PlateMovable Plate x0 x'0 x xxFelectrostaticFspringFigure 2-5. Schematic of a single backplate capacitive transducer showing electrostatic force and

restoring force.

The restoring force in the diaphragm Fr is given in terms of the mechanical compliance

Cm,d of the diaphragm by

~Fspring = (1/Cm,d) x′(x). (2–32)

Using Equation 2–1 Fspring can be expressed as a function of the gap distance, x as

~Fspring = +1

Cm,d

(x0 − x) (x). (2–33)

The Felectrostatic due to the electrostatic attraction between the plates is given by Equation 2–25

which is repeated below.

~Felectrostatic = −1

2Vdc

2 εA

x2(x). (2–34)

The net force acting on the diaphragm Fnet is thus given by the sum of the restoring spring force

given by Equation2–33 and the electrostatic force given by Equation 2–25

| ~Fnet |= −1

2Vdc

2 ε0A

x2+

1

Cm,d

(x0 − x) = 0. (2–35)

Initially, when the bias voltage is small, the movable plate will be displaced by a small

amount from its equilibrium position. As the voltage increases, the gap distance decreases. At

any given voltage, the stability is determined by applying a small perturbation to the diaphragm

and analyzing the subsequent diaphragm motion. If a small perturbation causes the diaphragm

to start moving towards the fixed back plate the equilibrium is unstable, else the equilibrium is

stable. To determine the critical gap distance and critical voltage at which the system transforms

from stable to unstable, we partially differentiate the net force Fnet with respect to the gap

31

distance x. When the plates are biased with a fixed voltage Vdc, ∂Fnet is given by

∂Fnet =

(− 1

Cm,d

+ε0AVdc

2

x3

)∂x. (2–36)

If the diaphragm is perturbed towards the backplate, i.e., ∂x < 0, then to ensure stable operation

the quantity in parenthesis must be positive so that ∂Fnet is also negative. Thus,

− 1

Cm,d

+εAVdc

2

x3< 0. (2–37)

Denoting the critical gap distance by xPI and the critical voltage by VPI , Equation 2–37 becomes

− 1

Cm,d

+εVPI

2

xPI3

= 0. (2–38)

By substituting Equation 2–38 into Equation 2–36 and evaluating at xPI and VPI , the critical gap

distance is

xPI =2

3x0, (2–39)

and the pull-in voltage is

VPI =

√8x0

3

27Cm,dεA. (2–40)

Quasistatic Pull-in for Single Backplate Transducer with Fixed Charge Biasing. Now

we derive the critical gap distance and pull in voltage for a single backplate capacitive transducer

biased with a fixed charge biasing technique. For this technique, the electrostatic force if given

by Equation 2–31 which is repeated below

~Felectrostatic = −1

2V 2

dc

εA

x20

((x)). (2–41)

It should be noted that the electrostatic force due to a fixed charge does not depend on the

position of the movable plate. The net force is given by

| ~Fnet |= 1

2Vdc

2 εA

x02

+1

Cm,d

(x0 − x) = 0. (2–42)

Differentiating the net force,

∂Fnet = − 1

Cm,d

∂x. (2–43)

32

If the diaphragm is perturbed towards the backplate, i.e. ∂x < 0, there is an opposite restoring

force ensuring that the equilibrium point is always stable. To determine the equilibrium position

xeq, we set Fnet = 0. The equilibrium position is thus given by

xeq = x0 − 1

2Cm,dVdc

2 εA

x02. (2–44)

If too large a voltage is chosen, then xeq < 0 which implies that the two plates are touching each

other. Furthermore if Vdc is too large then the initial deflection of the movable plate will be too

large and the transducer might operate in the non-linear region. To determine the pull-in voltage

we set xeq = 0 and solve for the voltage. This is given by

VPI =

√2x0

3

Cm,dεA. (2–45)

Comparing the pull-in voltage between the constant charge and constant voltage biasing

techniques, it can be seen that the pull-in voltage limit is higher for the constant charge

technique.

2.2.2 Canonical Dual Backplate Capacitive Transducer

Another commonly used structure in capacitive sensors is a a dual backplate structure [71]

as shown in Figure 2-6. The need for a differential structure is motivated by a need to linearizeFixed PlateMovable Plate x0Fixed Plate x0C2=C20 -C1=C10 + x'C1C2 xxFigure 2-6. Schematic of a differential capacitive transducer.

the system using structural modification. Also the differential structure has twice the change

in capacitance of the single backplate structure. The improvement in sensitivity and linearity is

discussed later in this section.

This structure consists of a movable plate sandwiched between two fixed plates. Two

capacitances C1 and C2 are formed, one between the top backplate and the movable plate and

the other between the bottom back plate and the movable plate. Under the application of an input

33

force on the movable plate, one of the capacitances increases while the other one decreases from

the nominal value. Under zero input force, the nominal capacitance of the two capacitors are

denoted by C10 and C20. If the change in capacitance of capacitor C1 is denoted by ∆C1 and the

change in capacitance of capacitor C2 is denoted by ∆C2, then

C1 = C10 + ∆C1 (2–46)

C2 = C20 −∆C2.

It is assumed for the initial discussion that the nominal capacitance and change in capacitance are

matched i.e.

C10 = C20 = C0 (2–47)

and

∆C1 = ∆C2 = ∆C. (2–48)

The effects of capacitance mismatch will be discussed later in this chapter. From the geometry,

C1 and C2 is given by

C1 =ε0A

x0 − x′(2–49)

C2 =ε0A

x0 + x′

The total capacitance change ∆C is given by

∆C = C1 − C2. (2–50)

Substituting for C1 and C2, we obtain

C1 − C2 =ε0εrA

x0 − x′− ε0εrA

x0 + x′. (2–51)

This can be simplified to

C1 − C2 =2ε0εrA

x20 − x′2

x′. (2–52)

For small displacements i.e [x′ ¿ x0], x′2 can be neglected and the above equation can be

simplified as

C1 − C2 ' 2ε0εrA

x20

x′. (2–53)

34

Using Equation 2–4, Equation 2–53 can be simplified to

C1 − C2 = 2C0x0

x′. (2–54)

From Equation 2–54, it can be observed that the capacitance change is a linear function of the

change in gap distance for small displacements. Comparing Equation 2–54 with Equation2–9 it

can be observed that the change in capacitance for the dual back plate structure is twice that of

the structure with a single backplate.

We now consider the voltage across the plates of the two capacitors. If the voltage across

capacitors C1 and C2 is denoted by V1 and V2, respectively, and the charge stored is Q1 and Q2,

respectively, then

V1 =x0 − x′

ε0AQ1 (2–55)

V2 =x0 + x′

ε0AQ2,

Equation 2–56 show that the voltages across the plates of a capacitor are a non-linear function of

the displacement and charge stored in the plates of the capacitor. Similar to the case with a single

backplate, the above equations can be linearized using either a fixed charge or a fixed voltage.

This is discussed next. i.e,

V1 ∝ Q1x′ (2–56)

V2 ∝ Q2x′.

Fixed Charge Technique (Voltage Amplifier Interface Circuit). In the fixed charge

technique, the top and bottom backplates of the microphone with top and bottom capacitances

given by C1 and C2 are biased at a DC potential of +Vdc and −Vdc volts as shown in Figure 2-7.

A unity gain voltage amplifier is connected to the middle plate. Rdc is a bias resistor that sets the

DC operating point. The linearized relation between the input and output of a charge amplifier

above the cut-in frequency is given by

Vout =2Vdc

x0

x′. (2–57)

The detailed derivation of this equation is provided in Appendix B.

35

VxRDC -+ VoutC1C2-Vdc+Vdc

Figure 2-7. Schematic of a dual backplate capacitive transducer connected to a voltage amplifier.

Fixed Voltage Technique (Charge Amplifier Interface Circuit). In this technique, the

top and bottom backplates of the microphone with top and bottom capacitances given by C1

and C2 are biased at a DC potential of +Vdc and −Vdc volts. Figure 2-8 shows a dual backplate

capacitive transducer connected to a charge amplifier. A feedback capacitor Cint is connectedCint+-RDCC1C2-Vdc+Vdc Cp VoutCL

Figure 2-8. Schematic of a dual backplate capacitive transducer connected to a charge amplifier.

between the output of the amplifier and the inverting input. This capacitor integrates the charge

flowing out of the transducer. A bias resistor Rdc is connected in parallel to the feedback

capacitor and is used to set the DC operating point. The RC network consisting of Rdc and Cint

sets up a high pass filter with a cut-in frequency, of 12πRdcCint

. For all frequencies above the cut

in frequency the charge flowing from the transducer is integrated by the feedback capacitor. The

linearized relation between the input and output of a charge amplifier above the cut in frequency

is given by

Vout = −2C0Vdc

x0Cint

x′. (2–58)

36

The detailed derivation of this equation is provided in Appendix B.

Force Relations. We now consider the force on the movable plate for the differential

structure. Figure 2-9 shows the schematic of the dual backplate capacitive transducer and the

force acting on the movable plate. The force on the movable plate depends on the type of biasingF1F2 x'x0x0Fixed PlateMovable PlateFixed Plate +Vdc-Vdc xxFigure 2-9. Schematic of a dual backplate capacitive transducer showing forces on the movable

plate.

technique used. We first consider the fixed voltage biasing technique. The net electrostatic force,

Felectrostatic, on the movable plate can be expressed in terms of the individual forces ~F1 and ~F2 by

~Felectrostatic = ~F1 + ~F2. (2–59)

Using Equation 2–26, ~F1 and ~F2 are given by

~F1 =1

2V 2

dc

εA

(x0 − x′)2 (−x) (2–60)

~F2 =1

2V 2

dc

εA

(x0 + x′)2 (x). (2–61)

The two forces operating on the movable plate are acting in opposition. This is because the

force between the movable plate and each of the fixed plates is attractive. ~F1 is acting in the

negative x direction. The total force ~Felectrostatic is given by the sum of ~F1 and ~F2. Substituting

Equation 2–60 and Equation 2–61 in Equation 2–59 and simplifying, Felectrostatic is given by

~Felectrostatic

∣∣∣Vdc

= 2Vdc2 εAx0x

′(x0

2 − x′2)2 (−x). (2–62)

Comparing Equation 2–62 with Equation 2–26, it can be seen that the net electrostatic force with

a constant voltage bias is lower for a dual backplate capacitive transducer as compared to a single

37

backplate capacitive transducer. The force will still tend towards infinity as the fixed plates starts

moving towards the movable plate. At rest, there is no net force acting on the movable plate.

We now consider the case when the two plates are biased with a fixed charge. In this

case there are two components to the force. They are the force between the top backplate and

the movable plate and the force between the bottom backplate and the movable plate. Using

Equation 2–30, the two forces on the diaphragm are

~F1 =Q2

dc

2εA(−x) (2–63)

~F2 =Q2

dc

2εA(x).

The total force ~Felectrostatic |Qdcis given by the sum of the two forces given by Equation 2–63 i.e

~Felectrostatic |Qdc= ~F1 + ~F2 = 0 (2–64)

which is zero for constant charge case for matched dual backplates.

Quasistatic Pull-in. We now derive the pull in voltage and gap distance for the dual

backplate capacitive transducer structure.

Quasistatic Pull-in for Dual Backplate Transducer with Fixed Voltage Biasing. The

derivation of the pull-in voltage and pull-in gap distance for a dual backplate microphone with

fixed voltage biasing is similar to that of the single backplate case. The net electrostatic force is

given by Equation 2–62 and the restoring force is given by Equation 2–32. The net force is given

by

~Fnet =

(−2Vdc

2 εx0x′

(x0

2 − x′2)2 −

x′

Cm,d

)x. (2–65)

In the case of a dual backplate structure, there are two gap distances. Hence, we analyze the net

force by differentiating it with respect to the distance moved from the nominal gap x′ instead of

the gap distance. Differentiating Fnet with respect to x′, we obtain

∂Fnet =

[(2Vdc

2εAx0(x2

0 − x′2)2

) (x2

0 + 3x′2

x20 − x′2

)− 1

Cm,d

]∂x′. (2–66)

For the system to be stable, a small perturbation in the change in gap distance, i.e ∂x′ > 0, must

cause a decrease in net force i.e. ∂Fnet < 0.

38

This implies (2Vdc

2ε0Ax0(x2

0 − x′PI2)2

) (x2

0 + 3x′PI2

x20 − x′PI

2

)− 1

Cm,d

< 0. (2–67)

Defining the voltage at the transition point from stable to unstable region of operation by VPI and

the displacement from equilibrium position by x′PI , we have(

2VPI2ε0Ax0(

x20 − x′2

)2

)(x2

0 + 3x′2

x20 − x′2

)− 1

Cm,d

= 0. (2–68)

Substituting Equation 2–68 in Equation 2–65 and solving for x′PI , we have

x′PI = 0. (2–69)

This shows that the equilibrium position for a dual backplate structure biased with a fixed voltage

is at the rest position of the diaphragm. The pull in voltage is given by

VPI =

√x0

3

2Cm,dεA. (2–70)

Quasistatic Pull-in for Dual Backplate Transducer with Fixed Charge Biasing. The

net force on the dual backplate transducer with a fixed charge biasing as given by Equation 2–64

is zero. Hence the equilibrium position is x′ = 0. Based on the model used, there is no upper

bound on the charge that can be placed on the transducer plates. This is not practically true as

the model did not account for non-idealities such as curvature of the plates, or other dynamic

conditions. Based on the physical realization of the transducer, there will be limits on the

maximum charge that can be applied on the plates.

2.3 Structure of Microphone Used as Test Vehicle for Open and Closed Loop InterfaceCircuit Design

The overall goal of this work is to investigate open loop and closed loop interface circuits

for capacitive microphones. A dual backplate capacitive microphone was used as the test vehicle

to characterize various interface circuits. To facilitate the design of the interface circuit, a

model of the microphone that accurately captures the dynamics is required. In this section, the

microphone structure and material properties are described from which a model can be developed

. The actual model development is discussed in the next section.

39

The microphone consists of a solid diaphragm sandwiched between two porous backplates

over a large cavity. A vent is provided to equalize the pressure on both sides of the diaphragm.

The cross section of the microphone is shown in Figure 2-10. The microphones were fabricated

using the Sandia SUMMiT V process [64]. This five-layer poly process allows the fabrication of

ultra-planar poly layers with low in-plane stress. Two microphone structures were designed for

use in aeroacoustic application and for audio application. The material properties and dimensions

of the two microphone structures are listed in Table 2-1.Top backplateDiaphragm BottombackplateSubstrateCavityAcoustic holes 1C

2C

Figure 2-10. Cross section view of dual backplate microphone [64].

Table 2-1. Dimensions of aeroacoustic and audio microphone[64].

Property Aeroacoustic AudioRadius of Top Backplate 256µm 756µm

Thickness of Top Backplate 2.25µm 2.25µm

Radius of Bottom Backplate 213µm 713µm

Thickness of Bottom Backplate 2.5µm 2.5µm

Radius of Diaphragm 230µm 730µm

Thickness of Diaphragm 2.25µm 2.25µm

Thickness of Top Gap 2µm 2µm

Thickness of Bottom Gap 2µm 2µm

Radius of Holes 5µm 5µm

No. of holes in Top Backplate 557 5030

No. of holes in Bottom Backplate 367 4361

Depth of Cavity 650µm 650µm

Radius of Cavity 186µm 686µm

Table 2-2. Material properties of microphone structure.

Property MagnitudeYoung’s modulus of polysilicon (e) 1.6× 1011Pa

Poisson’s ratio of polysilicon (ν) 0.22

Density of polysilicon (ρp) 2.2× 103kg/m3

40

2.4 Lumped Element Model

In order to develop an interface circuit that will meet the overall system level specifications,

we need to develop a model that accurately captures the dynamics of the microphone as a

function of the dimensions and material properties. We use the technique of lumped element

modelling (LEM) to achieve this goal. LEM is valid when the length scale of interest is much

smaller than the characteristic wavelength of the physical phenomenon [46]. In this case, the

length scale of interest is the diaphragm diameter and the characteristic wavelength is the

acoustic wavelength, λ. Using LEM, a theoretical formulation for the resonant frequency and

damping coefficient is developed. The general technique for developing the LEM for a transducer

will be discussed next followed by the application of the technique to the microphone under

consideration.

To develop the LEM, we consider the power flow between the various mechanical elements

using the principle of conjugate power variables. In this technique, power is denoted as the

product of two generalized quantities, effort and flow. In the electrical domain, the effort variable

is the applied voltage and the flow variable is the electric current. The product of these two

quantities is the power. In the acoustic domain, the effort variable is pressure, and the flow

variable is volume velocity. Using the effort and flow variables in the system, we next discuss the

energy storage and dissipative elements in the system.

The ratio of the effort variable to the flow variable represents the generalized impedance in

the system. In the electrical domain, the ratio of the applied voltage to the current is equal to the

impedance which if in phase represents the electrical losses in the electrical domain. Similarly,

the ratio of the input pressure to the volume velocity is the acoustic impedance. A real acoustic

impedance is denoted by a resistor and it represents the energy loss mechanisms in the acoustic

domain. The physical cause of the energy loss in the acoustic domain is viscous damping and

radiation resistance.

The energy storage elements are discussed next. In the electrical domain, the capacitor

stores potential energy (energy associated with the effort variable) and the inductor stores kinetic

energy (energy associated with the flow variable). In the acoustic domain, the kinetic energy

and potential are stored by the motion and deflection of the elastic diaphragm respectively. The

41

distributed elastic deflection of the diaphragm is lumped into a rectilinear piston having the

same deflection as the center of the diaphragm and a spring. The equivalent mass of the piston is

determined by equating the kinetic energy of the distributed diaphragm motion into the kinetic

energy of the lumped piston motion. Similarly, the compliance of the spring is found by equating

the potential energy stored in the distributed diaphragm deflection to the potential energy in the

lumped compliance.

Finally, we discuss the rules that govern the interconnection of the various elements. In the

impedance analogy, elements that share the same flow and displacement variable are connected

in series while elements that share the same effort variable are connected in parallel. Also, for the

impedance analogy, by Kirchoff’s laws, the sum of all the efforts around a closed loop is zero,

and the sum of all the flows entering a node is zero.

The LEM of the dual backplate microphone structure is discussed next. All the LEM

parameters discussed are in the acoustic domain. Ideally, the top and bottom backplates are

rigid. However, physically they do deflect by a small amount. Hence, they are modelled as

capacitors Cbp1, Cbp2 which represents the storage of potential energy. The main loss mechanism

in the backplates is the viscous damping loss [72]. These are represented by Rbp1, Rbp2 which

are connected in parallel to the corresponding compliance as they both share the same effort

variable. The diaphragm responds to the input pressure Pin and deflects storing potential

energy and is modelled as a capacitor Cd. The diaphragm motion stores kinetic energy and

is modelled as an inductor Md. These elements share the same volume displacement (flow

variable) and are thus connected in series. Viscous losses associated with the diaphragm are

neglected. The cavity impedes the motion of the diaphragm by storing potential energy and

is modelled as a compliance Ccav. The cavity between the top and bottom back plates and the

diaphragm is neglected. The resistance of the vent is modelled by as a resistor Rv. Theoretical

formulation for each of the model parameters is listed in Table 2-3 [73, 74, 75]. Using the

formulation in Table 2-3, and the structural and material properties listed in Table 2-1 and

Table 2-2 respectively, the model parameters for the two microphones are calculated. The results

are listed in Table 2-4.

The LEM of the microphone with approximations discussed is shown in Figure ??. In the

frequency range of interest, the top and bottom plate compliances and the vent resistances can be

42

Table 2-3. Theoretical formulation for lumped element model parameters.Parameter Symbol ExpressionDiaphragm Mass Mma

9ρph

5πr2

Diaphragm Compliance Cmaπr6(1−ν2)

16Eh3

Cavity Compliance CcavV

ρairc2

Backplate Hole Resistance Ra12ηairB(A)

π2r2nx30

Vent Resistance Rv128ηairLeff

πD2vent

Table 2-4. Lumped element model parameters of aeroacoustic and audio microphone.

Parameter Symbol AeroacousticMicrophone

AudioMicrophone

Top backplate compliance (m4s2/kg) Cbp1 2.8× 10−17 1.9× 10−14

Bottom backplate compliance (m4s2/kg) Cbp2 6.9× 10−18 9.8× 10−15

Diaphragm Compliance (m4s2/kg) Cd 1.5× 10−17 1.6× 10−16

Cavity Compliance (m4s2/kg) Ccav 5.0× 10−16 6.8× 10−15

Top backplate hole resistance (kg/m4s2) Rbp1 1.6× 109 1.7× 108

Bottom backplate hole resistance (kg/m4s2) Rbp2 1.3× 109 1.6× 108

Vent Resistance (kg/m4s2) Rv 7.5× 1012 7.5× 1012

Diaphragm mass (kg/m4) Md 5.7× 104 5.6× 103

neglected. Under this condition, the microphone model can be simplified into a simple second

order LCR circuit as shown in Figure 2-11. The LCR system can be described by a second orderCdMdRbp1 CcavRbp2PinFigure 2-11. Low frequency LEM of dual backplate microphone.

displacement to pressure transfer function H(s) [76]

H(s) =1/Md

s2 + 2× ζ × 2πfres × s + (2πfres)2 , (2–71)

where the resonant frequency fres of the system is given by the expression

fres =1

2π

√1

MdCcavCd

Ccav+Cd

, (2–72)

43

and the damping coefficient ζ by the expression

ζ =1

Rbp1 + Rbp2

√Md

CcavCd

Ccav+Cd

. (2–73)

Substituting for the various parameters in Equation 2–72 and Equation 2–73, we obtain the

Table 2-5. Second order system parameters of microphones.Quantity Aeroacoustic (Theoretical) Audio (Theoretical) Aeroacoustic (Experimental)[76]fres 174kHz 31kHz 230kHzζ 0.018 0.15 0.025

100

102

104

106

108

−100

−80

−60

−40

−20

0

20

Mag

nitu

de (

dB)

100

102

104

106

108

−150

−100

−50

0

Pha

se (

deg)

Frequency (Hz)

Figure 2-12. Theoretical normalized frequency response of audio microphone.

resonant frequency and damping coefficient for the two microphone designs. The results are

listed in Table 2-5. A plot of the normalized theoretical transfer function of the audio and

aeroacoustic microphone is shown in Figure 2-13 and Figure 2-13 [76].

2.5 Summary

In this chapter, canonical capacitive transducers were introduced. The charge, voltage,

capacitance, and force relations for the single and dual backplate microphone were derived.

The structure and material properties of the microphone that are used as the test vehicle to

characterize the open and closed loop circuit described in Chapter 3 were presented. A lumped

element model of the microphone was then developed. A reduced second order model of the

microphone was derived from the general lumped element model from which the resonant

frequency and damping coefficient were extracted. Simulations results of the frequency response

of the microphone model were also presented.

44

100

102

104

106

108

−100

−50

0

Mag

nitu

de (

dB)

100

102

104

106

108

−150

−100

−50

0P

hase

(de

g)

Frequency (Hz)

Figure 2-13. Theoretical normalized frequency response of aeroacoustic microphone.

To design the closed loop circuit, a model of the interface circuit is required. Chapter 3

presents an overview of the various capacitive transducer interface circuits along with models

that will be used in Chapter 4 and Chapter 5 for the development of the overall closed loop

system.

45

CHAPTER 3INTERFACE CIRCUITS

3.1 Introduction

This chapter discusses the various open-loop and closed-loop capacitive transducer interface

circuits with an emphasis on circuits for capacitive microphones. For each technique, the

principle of operation is first explained. Then theoretical formulations for the input/output

characteristics, sensitivity, dynamic range, bandwidth, and minimum detectable signal are

developed. A review of commercial transducers and research prototype transducers reportedIntroduction tointerface circuitsOpen loop interfacecircuitsVoltage bufferCharge amplifierSynchronousmodulation/demodulationSwitched capacitoramplifier SummaryComparisonbetween thetechniques

Closed loopinterface circuits Analog techniqueDigital techniqueComparisonbetween thetechniquesPerformancemetrics

Figure 3-1. Overview of Chapter 3.

in the published literature using these interface circuits is presented. This chapter concludes

with a summary of the various techniques. A graphical overview of this chapter is provided in

Figure 3-1.

3.2 Performance Metrics of Capacitive Transducers

In this section, the main performance metrics [77] of capacitive transducers with an

emphasis on capacitive microphones is introduced. The sensitivity, S, of a capacitive transducer

is defined as the change in the output voltage for an input physical phenomenon-derived change

46

in capacitance. For capacitive microphones, the input phenomenon is a time varying pressure

signal, and the microphone sensitivity is measured in V olts/Pascal. Similarly, for a capacitive

accelerometer, the input is an acceleration commonly measured in g. Therefore, the units of

sensitivity for an accelerometer is V olts/g. The sensitivity of the transducer can be expressed

as the product of the mechanical sensitivity (Sm) and electrical sensitivity (Se). The mechanical

sensitivity denotes the transfer function between the change in capacitance for an input change

in physical phenomenon. The electrical sensitivity refers to the change in output voltage for an

input capacitance change.

The emphasis of this chapter is on interface circuits which measure capacitance. Hence,

the electrical sensitivity of the interface circuit is expressed in V/F . It should be noted that the

sensitivity is defined as the magnitude of the flat region of the frequency dependent transfer

function. For a linear transducer, the transfer function H(ω) is defined as the ratio of the Fourier

transform of the output of transducer Y (ω) to the Fourier transform of the input of the transducer

X(ω), i.e.

H(ω) =Y (ω)

X(ω). (3–1)

The transfer function is in general a complex quantity. Hence, the complete description includes

both the magnitude |H(ω)| and phase ∠H(ω)| as a function of frequency. The magnitude of the

transfer function, as defined in Equation 3–1, is thus a plot of the sensitivity of the transducer as a

function of frequency. For an ideal transducer, the phase must be constant and zero.

The typical frequency response of a capacitive transducer is shown in Figure 3-2. It can

be seen that over a certain frequency range, the frequency response magnitude is flat within

a given tolerance, say 3dB. For a transducer, this is the range of frequencies over which it

can be used and is defined as the bandwidth of the sensor. The lower and higher roll off of

the transfer function is caused by both the transducer structure and the interface electronics.

For a microphone, the lower end of frequency range (denoted by fl), also known as the cut on

frequency, is determined by either the biasing resistor of the interface circuit or the acoustic

resistance of the vent channel and cavity compliance [53]. Similarly, the higher end of the

frequency range (denoted by fh), also known as the cut off frequency, is determined by the

47

FrequencyMagnitude (dB)Frequency (Hz)Phase (deg) 900-180-90 Flat frequency response(bandwidth)fl fh Resonance Peak

Figure 3-2. Characteristic frequency response of a capacitive transducer.

bandwidth of the interface circuit or the mechanical resonance of the sensor structure which in

turn is determined by the diaphragm mass and compliance.

The next performance metric to be considered is the linearity of the sensor. The linearity

of the sensor is a measure of how close the output versus input calibration curve approximates

a straight line at a given frequency. A plot of the ideal and actual linearity of a transducer is

shown in Figure 3-3. The slope of the straight line provides the sensitivity of the transducer at

Input PressureOutput Voltage Ideal responseActual responseFigure 3-3. Characteristic ideal and actual response of a capacitive transducer.

that frequency. It can be seen that at high input amplitudes, the output of the transducer deviates

from the ideal straight line curve. The lower and higher ends of the linear range are determined

by both the sensor interface circuit and the sensor. The lower end is limited by system noise

such as thermal noise, 1/f noise, and mechanical noise. The higher end of the linear range is

determined by structural non-linearities such as spring stiffening [78] or by circuit non-linearities

48

such as clipping [79]. The dynamic range of a capacitive transducer is defined as the ratio of the

maximum and minimum input signal of the linear range.

The deviation of the output from the ideal linear curve causes distortion in the microphone

output. Distortion can be defined in two different ways based on the input signal. When the

system is excited at a single frequency, distortion is defined as the minimum input amplitude that

causes the output to deviate from linearity by a fixed percentage. For a measurement microphone,

the deviation is usually chosen to be 3%. When the transducer is characterized over a frequency

range, the distortion is defined in terms of the total harmonic distortion (THD). THD is defined

as the ratio of the sum of the power in all the harmonic frequencies (ωn) to the fundamental

frequency (ω0).

THD =

∑∞n=0 P 2(ωn)

P 2(ω0). (3–2)

The output noise floor of a transducer is the noise mechanism generated output for zero

input signal. Referred to the input, the input noise floor represents the minimum detectable signal

(MDS). The output referred noise voltage power spectral density (PSD) of the interface circuit

denoted by SVout is expressed in V 2/Hz. The electrical noise at the output of the interface circuit

can be referred to the interface circuit input by dividing the output noise by the square of the

electrical sensitivity. The input signal PSD of the interface circuit is expressed in F 2/Hz. Thus,

the output noise power in a system is dependent on the bandwidth of operation. The total output

noise power or mean square output noise voltage is obtained by integrating the output noise

voltage PSD over the measurement bandwidth i.e.

v2no =

∫ fh

fl

SVoutdf. (3–3)

and the rms output noise voltage is vn,rms =√

v2no. A characteristic noise PSD curve is shown

in Figure 3-4. The overall system noise includes noise contributions from both the sensor and

the interface circuit. At low frequencies, the noise PSD is dominated by the flicker noise [80]

of the interface circuit which has a 1/f spectral shape. It should be noted that flicker noise is

present only when a dc current flows. At high frequencies, the noise is dominated by the thermal

noise [80] above a corner frequency. The corner frequency is the point at which the asymptote of

the 1/f noise region meets the thermal noise floor. Thermal noise is present in all systems that

49

Frequency (Hz)Noise PSD (V2/Hz) 1/f Noise regionThermal1/f Noise regionCorner frequencyFigure 3-4. Characteristic noise floor of a capacitive transducer using a voltage amplifier

interface circuit.

are in thermodynamic equilibrium. The magnitude of the thermal noise PSD is proportional to

the dissipation in the system.

To study the effect of the interface circuit noise on overall system performance, the noise

models developed in this chapter consider only the electronics noise of the interface circuit

elements and the spectral shaping of these noise sources by the interface circuit elements.

The commonly used elements in the interface circuit are resistors, capacitors and operational

amplifiers (opamps).

The noise model of the resistor is considered first. The 1/f noise of a resistor is dependent

on the fabrication method used to manufacture the resistor. Metal film resistors have the lowest

1/f noise and have a flat frequency response across the entire spectrum. Figure 3-22 shows the

voltage and current noise representations of a resistor. The PSD of resistor voltage and current

noise representations is given by

SvR = 4kTR (3–4)

and

SiR =4kT

R(3–5)

respectively.

Ideally, capacitors do not have any noise associated with them. In practical applications,

capacitors have an equivalent series resistor (ESR) which has a noise associated with it. The

ESR of a capacitor is small in comparison with other physical resistors present in the system.

Hence the noise of the physical resistor dominates over the noise due to the ESR. Hence, noise in

capacitors are not considered in the discussions in this chapter.

50

R SvR(a) Voltage noise model

of resistor.

RSiR(b) Current noise

model of resistor.

Figure 3-5. Noise model of resistor.

The noise model for the opamp is discussed next. Figure 3-6 shows the noise model of an

opamp consisting of a voltage and current noise voltage source at the non-inverting input of

the amplifier. The fundamental physical phenomena which cause noise in the opamp are the

thermal noise, shot noise, and 1/f noise in the transistors and resistors inside the opamp. The

typical noise voltage PSD (Sv) and current noise PSD (Si) is shown in Figure 3-7. It can be

seen that at low frequency the PSD has a 1/f shape and at large frequency, the PSD is constant.

The point at which the asymptote of the 1/f noise meets the thermal noise floor is the corner

frequency and is denoted by fcv and fci for the voltage and current noise PSDs respectively. At

any given frequency, the voltage and current noise PSD, Sv(f) and Si(f) respectively, can be

approximately expressed in terms of the corresponding voltage and current thermal noise limits,

Svo and Sio by

Sv(f) = Sv0

[1 +

fcv

f

](3–6)

and

Si(f) = Si0

[1 +

fci

f

]. (3–7)-+ VoutSva Sia

Figure 3-6. Noise model of opamp showing voltage and current noise source.

3.3 Analog Open Loop Sense Techniques

The function of the sense electronics is to measure the capacitance change associated with

the deflection of the diaphragm and provide a corresponding voltage signal . In the open-loop

scheme, the change in capacitance is measured directly by voltage or charge biasing either the

51

backplates or the diaphragm and measuring the voltage or charge signal generated on the other

plate. No feedback signal based on the measured output signal is applied to the microphone

plates to null the deflection caused by the input phenomenon. The open-loop techniques can be

further classified into analog and digital schemes which are discussed next.

Frequency (Hz)Noise PSD (V2/Hz) 1/f Noise region Thermal Noise regionCorner frequencyfcvSv

fSv0(a) Plot of voltage noise PSD of

amplifier.

Frequency (Hz)Noise PSD (A2/Hz) 1/f Noise region Thermal Noise regionCorner frequencyfci fSiSi0

(b) Plot of current noise PSD ofamplifier.

Figure 3-7. Plot of noise PSD of amplifier.

The performance metrics discussed so far will be derived for the various open and

closed-loop interface techniques. The analog open-loop sense schemes are characterized by the

absence of a clock signal as compared to the digital open loop sense techniques. The commonly

used analog open-loop techniques sense the voltage change using a voltage amplifier under a

constant charge bias, sense the charge using a charge amplifier under a constant voltage bias,

and sense using synchronous modulation/demodulation. Each of these techniques is discussed

in detail. For each of these interface techniques, the principle of operation, formulation for

performance metrics, tradeoffs, and a literature review is presented. Figure 3-8 shows a flow

diagram for each section. The derivation of the equations for each of the interface techniques is

presented in Appendix B.

3.3.1 Sensing Using A Voltage Amplifier

Operating Principle. In the simplest case, the top and bottom backplates of the

microphone with top and bottom capacitances given by C1 and C2 are biased at a dc potential

of +Vdc and −Vdc volts. A unity gain voltage amplifier is connected to the middle plate. Rdc is

a bias resistor that sets the dc operating point. Figure 3-9 shows a schematic of a dual backplate

capacitive microphone connected to a voltage buffer including parasitics. Cp represents the

total parasitic capacitance at the input to the amplifier due to the packaging. The parasitic

capacitance of commonly used packaging techniques is presented in Table 3-1. For a single chip

52

Interface circuitPrinciple ofoperationPerformancemetricsTradeoffsLiterature reviewFigure 3-8. Organization of each interface circuit discussed in Chapter 3.VxRDC -+ VoutCLC1C2-Vdc

+Vdc Cp CiFigure 3-9. Schematic of a dual backplate microphone connected to voltage buffer.

solution in which both the microphone and interface circuitry are on the same die, the sensor and

interface circuitry are electrically connected using metal or poly lines and the parasitic or input

capacitance is < 1pF . For two chip solutions, the parasitic capacitance is on the order of a few

pF depending on the interconnect used such as bond wires or PCB tracks. Ci represents the total

input capacitance of the amplifier. For an ideal interface circuit with no parasitic capacitance, the

output of the circuit, for a given change in capacitance, ∆C, is given by,

Vout =Vdc

C0

∆C, (3–8)

53

Table 3-1. Parasitic capacitance for various packaging technologies.Technique Packaging Parasitic CapacitancePolysilicon or metallines

On die interconnect < 10fF/um (Layoutdependent)

Wire bond [81] Interconnect between unpackageddies

30fF/mm

PCB Trace (FR4 PCB) Interconnect between packaged dies 1− 2pF/cm (Layoutdependent)

BNC cable(RG164[82]])

Interconnect between differentboards

20.6pF/ft

which is the same as a single backplate microphone. The derivation of all the equations is

provided in Appendix B. For a real interface circuit with parasitic capacitances, the output

voltage is given by

Vout =Vdc

2C0 + Cp + Ci

2∆C. (3–9)

Equation 3–9 can be rewritten as

Vout =Vdc

C0

[2C0

2C0 + Cp + Ci

]∆C. (3–10)

Defining the overall voltage attenuation factor Hc as

Hc =

[2C0

2C0 + Cp + Ci

], (3–11)

Equation 3–10 can be written as

Vout = HcVdc

C0

∆C. (3–12)

Comparing Equation 3–12 and Equation 3–8, it can be seen that the output voltage is attenuated

by the factor Hc that is dependent on the parasitic capacitance.

Performance Metrics. The first performance metric that will be derived is the sensitivity

of the circuit. Using the definition of sensitivity discussed in Section 3.2 and using Equation 3–9,

the electrical sensitivity Se of the circuit is given by

Se =2Vdc

2C0 + Cp + Ci

. (3–13)

From this equation, it can be seen that the sensitivity of the circuit is reduced with increased

parasitic capacitance.

To determine the total output noise, the noise model shown in Figure 3-10 is used. The PSD

54

C2 -+ VoutCLC1 Zi RDCCp Ci Sva SiaSvRFigure 3-10. Noise model of dual backplate microphone connected to voltage buffer.

of the circuit SVout is determined by the amplifier noise and the thermal noise of the bias resistor

and is given by

SVout = Sva + Sia

∣∣∣∣ZiRdc

Zi + Rdc

∣∣∣∣2

+

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

SvR, (3–14)

where Zi = 1jω(2C0+Cp+Ci)

.

To obtain the minimum detectable capacitance per√

Hz, the noise PSD equation is divided

by the square of the electrical sensitivity Se followed by a square root. The minimum detectable

capacitance Cmin is given by

Cmin =

(2C0 + Cp + Ci

2Vdc

) √Sva + Sia

∣∣∣∣ZiRdc

Zi + Rdc

∣∣∣∣2

+

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

SvR [F/√

Hz] (3–15)

From the equation for Cmin, it can be seen that the minimum detectable capacitance can be

decreased by increasing the bias voltage. It can also be seen that the parasitic capacitance

increases the minimum detectable capacitance.

The upper end of the circuit dynamic range is limited by the maximum output voltage of the

amplifier and is dependent on the topology of the amplifier used. For a given power supply Vdd,

the maximum output voltage Vomax is determined by a circuit dependent voltage drop Vdrop below

the supply rails Vdd and is given by the expression

Vomax = Vdd − Vdrop. (3–16)

For example, for an actively loaded single stage amplifier, the minimum Vdrop is given by

the overdrive voltage across the load transistor. Dividing the above equation by the electrical

55

sensitivity, the maximum input capacitance Cmax that can be measured is

Cmax =2C0 + Cp + Ci

2Vdc

[Vdd − Vdrop] . (3–17)

This shows that the upper end of the dynamic range can be increased by decreasing the top and

bottom plate voltage and increasing the sense capacitance.

The next performance metric that we derive is the circuit bandwidth. The lower limit of the

frequency response is set by the total capacitance at the inverting node and the bias resistor. [83].

It is given by the expression

fl =1

2πRdc (Cp + Ci + 2C0). (3–18)

The upper limit of the bandwidth fh of this circuit is determined by the amplifier. For a folded

cascode amplifier, the bandwidth is determined by the unity gain frequency , and is expressed in

terms of the load capacitance CL and transconductance gm by the expression [79]

fh =1

2π

gm

CL

. (3–19)

Tradeoffs. The main advantage of this circuit is its simplicity. It has very small

component count and can be easily implemented on an IC or on a PCB. However, the circuit

has some cons which are discussed. The overall sensor sensitivity is reduced by the parasitic

capacitance which is not easily controllable. A plot of the electrical sensitivity as a function of

parasitic capacitance is shown in Figure 3-11 for different sensor capacitances. It can be seen

that as sensor capacitance is scaled down, the effect of parasitic capacitance is exacerbated. The

noise floor of the interface circuit given by Equation 3–14 is dependent on the filtering of the

amplifier and resistor noise by the sense and parasitic capacitance. Furthermore, the choice of

amplifiers also makes a difference as amplifiers are optimized for either low current noise or low

voltage noise and not both. Figure 3-12 shows a plot of the noise contributions by the various

noise sources and the total output noise.

To understand the effect of the various circuit elements, on the output noise PSD,

Figure 3-13 and Figure 3-14 are plotted. Figure 3-13 shows a set of plots of the output noise

PSD as the sensor capacitance is scaled from 100pF to 1pF for various parasitic capacitances

assuming a fixed bias resistor of 10MΩ.

56

0 5 10 15 20 25 30 35 40 45 50

10−1

100

Parasitic Capacitance (pF)

Sen

sitiv

ity N

orm

aliz

ed

with

Bia

s V

olta

ge (

V/V

/pF

)

Decreasing Sense Capacitance

1pF5pF10pF50pF100pF

Figure 3-11. Variation of sensitivity as a function of total parasitic capacitance for various sensecapacitances

Figure 3-13(a), Figure 3-13(c), and Figure 3-13(e) show these plots for an amplifier with

low voltage noise and Figure 3-13(b), Figure 3-13(d), and Figure 3-13(f) show these plots for a

low current noise amplifier. It can be seen that for a fixed bias resistor, an amplifier optimized for

low current noise has a lower noise floor as compared to an amplifier with low voltage noise. It

can also be seen that this is true for all combinations of sensor and parasitic capacitance.

Figure 3-14 shows a set of plots of the output noise PSD capacitances as the sensor

capacitance is scaled from 1pF to 100pF for various bias resistors assuming a fixed parasitic

capacitor of 10pFΩ. In Figure 3-14(a), Figure 3-14(c), Figure 3-14(f) show these plots for

an amplifier with low voltage noise and Figure 3-14(b),Figure 3-14(d), Figure 3-14(e) show

the plots for low current noise. It can be seen that for a fixed parasitic capacitor, an amplifier

optimized for low current noise has a lower noise floor as compared to an amplifier with low

voltage noise. It can also be seen that this is true for all combinations of sensor capacitance and

bias resistor.

Literature Review. The voltage amplifier is the most common interface circuit used

in measurement microphones and audio microphones both for commercial and research

57

10−2

100

102

104

106

108

1010

10−30

10−25

10−20

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Voltage NoiseCurrent NoiseResistor NoiseTotal Noise

Figure 3-12. Power spectral density of individual noise contributors and total output noise in avoltage amplifier based interface circuit. (Low Voltage Noise Amplifier (OP471)Sv0 = 10nV/

√Hz, Si0 = 1.6pA/

√Hz, fcv = 10Hz, fci = 10Hz, Rdc = 44MΩ,

Cp = 10pF ,Ci = 2.6pF , 2C0 = 1.7pF )

applications. Table 3-2, Table 3-3, and Table 3-4 list the properties of commercial and research

prototype voltage amplifiers used for capacitive microphones. One of the commonly used

commercial measurement microphone for aeroacoustic applications is the Bruel and Kjaer Type

4138 microphone [38].The nominal capacitance of this microphone is 6.2pF . The interface

circuit used is the Type 2670 voltage amplifier.

One of the commonly used commercial measurement microphone for aeroacoustic

applications is the Bruel and Kjaer Type 4138 microphone [38].The nominal capacitance of

this microphone is 6.2pF . The interface circuit used is the Type 2670 voltage amplifier. The Type

2670 amplifier has a flat frequency response from 15Hz − 200kHz and a noise level of 14µV

integrated over a 30Hz to 300kHz. The input capacitance of the preamplifier is 0.5pF . These

microphone are biased with 200V using a Bruel and Kjaer Type 2804 microphone power supply

unit.

58

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

10−6

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(a) Low Voltage Noise (Cp + Ci = 1pF )

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(b) Low Current Noise (Cp + Ci = 1pF )

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

10−6

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(c) Low Voltage Noise (Cp + Ci = 10pF )

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

Frequency (Hz)

Noi

se (

V2 /H

z)Cs = 1pFCs = 10pFCs = 100pF

(d) Low Current Noise (Cp + Ci = 10pF )

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

10−6

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(e) Low Voltage Noise (Cp + Ci = 100pF )

10−2

100

102

104

106

108

1010

10−18

10−16

10−14

10−12

10−10

10−8

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(f) Low Current Noise (Cp + Ci = 100pF )

Figure 3-13. Plot of output noise for voltage amplifier with a fixed bias resistor (10MΩ).(Low Voltage Noise Amplifier (OP471) Sv0 = 10nV/

√Hz, Si0 =

1.6pA/√

Hz, fcv = 10Hz, fci = 10Hz, Low Current Noise Amplifier (TL2274)Sv0 = 10nV/

√Hz, Si0 = 0.01pA/

√Hz, fcv = 10Hz, fci = 10Hz)

59

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(a) Low Voltage Noise (Rdc = 100kΩ)

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(b) Low Current Noise (Rdc = 100kΩ)

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(c) Low Voltage Noise (Rdc = 10MΩ)

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)Cs = 1pFCs = 10pFCs = 100pF

(d) Low Current Noise (Rdc = 10MΩ)

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(e) Low Voltage Noise (Rdc = 1GΩ)

10−2

100

102

104

106

108

1010

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(f) Low Current Noise (Rdc = 1GΩ)

Figure 3-14. Plot of output noise for voltage amplifier with a fixed parasitic capacitance of(10pF ). (Low Voltage Noise Amplifier (OP471) Sv0 = 10nV/

√Hz, Si0 =

1.6pA/√

Hz, fcv = 10Hz, fci = 10Hz, Low Current Noise Amplifier (TL2274)Sv0 = 10nV/

√Hz, Si0 = 0.01pA/

√Hz, fcv = 10Hz, fci = 10Hz)

60

Table 3-2 shows a list of commonly used Bruel and Kjær amplifiers suitable for aeroacoustic

measurement and their characteristics.

Table 3-2. Specification of Voltage Amplifiers for Bruel and Kjaer Microphones.Model Number Input Capacitance Noise Floor

(A-weighted)Bandwidth

Type 2660 0.3pF 0.8µV 20Hz-200kHz

Type 2669B 0.3pF 1.9µV 20Hz-200kHz

Type 2670 0.3pF 4.0µV 30Hz-300kHz

Commercial MEMS capacitive microphones are now available from Knowles acoustics and

Sonion Technologies. These microphone use an integrated voltage buffer along with an analog to

digital converter (ADC) to provide a digital output. The target application for these microphone

is in the high volume cell phone market where price is the important metric. Also for integration

with the rest of the system, a digital output is an important feature.

Knowles Acoustics sells commercial MEMS based microphones for audio applications

namely, the SiSonic series of microphones [5]. They consist of a MEMS microphone wirebonded

to a voltage amplifier. The interface circuitry operates on a 1.5V source. The high voltage (11V )

required for biasing the microphone is obtained by an on-chip charge pump. The circuit has a

bandwidth in excess of 10kHz. The performance metrics of the amplifier itself are not provided.

Sonion Technologies sells MEMS microphones for cell phone applications namely the

TC100 series microphones [47, 84]. It consists of a PMOS buffer amplifier cascaded with

a NMOS gain stage. The chip is powered by a 1.8V supply. The output of the amplifier is

processed via a ADC and thus the microphone has a digital output.

The National Semiconductors LV 10XX series of amplifiers [85] is specially designed

for electret condenser microphones and consists of a high gain, low input capacitance stage

followed by an optional sigma delta based analog to digital converter thus providing both analog

and digital outputs. The circuit runs on a 1.8 to 5V supply. The input capacitance is 2pF over

the entire power supply range. The gain variation is 8V/V to 25V/V over the entire product

family and power supply options. These amplifiers have a flat frequency response from 100Hz

to 110kHz. The input noise of these amplifiers is approximately 500nV/√

Hz. The primary

application of these interface circuits is for microphones used in cell phones.

61

Table 3-3 presents an overview of voltage amplifier circuits used in research prototype

capacitive microphones. It has been observed that in these publications, the overall microphone

sensitivity in V/Pa is reported and not the electrical sensitivity (V/F ). Hence, the gain reported

in Table 3-3 is the sensitivity of the amplifier alone and is expressed in V/V . The general trend

in the input stage of voltage amplifier implementation using custom ICs is the use of unity gain

single transistor CMOS stages . This is done to minimize input parasitic capacitance and input

current noise.

In the published literature, one of the earliest semiconductor voltage follower based

capacitive microphone interface circuit was reported in a patent by Killion et al. in 1970 [86].

The circuit consisted of a JFET voltage follower. Back-to-back diodes were used for biasing the

microphone capacitance.

In 1989, Murphy et al, [87] presented a silicon electret microphone that uses a CMOS

preamplifer. The amplifier had a reported gain of 0.9V/V . The overall device had a bandwidth

of 15kHz. The bias voltage used was not reported. In 1991, Bergqvist et al presented a single

backplate microphone with a perforated backplate. The microphone capacitance was 5pF and

was biased with a 5V dc battery. A modified Bruel and KjærType 2619 was used as the interface

circuit. The input parasitic capacitance of the interface circuit was 2pF , and the bandwidth was

from 20Hz to 20kHz. In 1995, Ning et al. [88], presented a voltage buffer based interface circuit

for a micromachined capacitive microphone to be used in cell phones.

In 1995, Ning et al. [88], presented a voltage buffer based interface circuit for a micromachined

capacitive microphone to be used in cell phones.The nominal capacitance of the sensor was

9.1pF . The input parasitic capacitance of the cables and the interface circuit was 12pF with the

amplifier contributing 2pF . The microphone was biased at a dc potential of 6V .

In 1996, Bernstein and Borenstein presented the first MEMS microphone with onchip

interface circuitry [18] in 1996. It consisted of a JFET source follower with an input parasitic

capacitance of 0.5pF .

In 1998, Pedersen and Bergveld reported a MEMS amplifier [59] with integrated CMOS

amplifier and dc-dc converter. The amplifier input consisted of a p-MOSFET based voltage

follower. A p-MOSFET was used because of its lower noise floor as compared to an n-MOSFET.

62

Table 3-3. Review of interface circuits used in MEMS microphones published in literature.Author Microphone

CapacitanceParasitic

Capacitance αGain Bandwidth Comments

Killion,1970[86]∗

NR NR, NR NR NR JFET input custom amplifier,Back-to-back diodes to bias

microphone plateMurphy etal,1989[87]

NR NR, NR 0.9 15kHz Custom CMOS amplifier

Sprenkelset al.,1991[89]

3pF 1pF , NR 0.9 NR JFET input amplifier

Kuhnel etal.,1992[90]

1pF 0.25pF , NR 1 20kHz Commercial Bruel andKjærType 2633 preamplifier

Bergqvistet al,1994[91]

5pF 2pF , NR 1 20Hz −20kHz

COTS∗∗ Bruel and KjærType2619 amplifier

Ning et al,1994[88]

9.1pF 2pF , 10pF 1 NR Custom amplifier.Microphone used in cell

phones.Bernstein etal, 1996[?]

NR 0.5pF , NR NR NR Custom JFET sourcefollower.

Hsu al,1997[14]

16.2pF 2pF , 10pF 1 NR COTS∗∗ HPA-COP4012amplifier. Input impedance is

10GΩ.Kabir al,1999[14]

2.4pF NR, NR < 1 100Hz−9kHz

Custom JFET sourcefollower.

Baker et al,2003[92]

NR NR, NR NR upto10kHz

Uses the current output of aJFET follower. Used formicrophones in cochlear

implantsKern et al,2004[93]∗

NR NR, NR NR NR Large back to back diodes areused to bias amplifier

Furst et al,2005[84]∗

NR < 10pF , NR NR NR PMOS unity gain stagedriving a NMOS gain stage

Loeppert etal,2006 [94]

0.5pF < 1pF ,0.25pF

1 NR Unity gain buffer with an0− 20dB gain opamp in

cascade. The output of thefirst stage drives the shield.

α Input Capacitances, Interconnect Capacitance∗ Patent

In 1998, Hsu et al reported a single backplate polysilicon condenser microphone [95]. The

device had a zero bias capacitance of 16.2pF . The interface circuit used was a HPACOP4012

preamplifier. It had an input impendance of 2.5GΩ. The input capacitance is not reported. The

microphone was polarized at 10V .

In 1999, Kabir et al. reported a MEMS microphone that used a doped p+ poly as the

membrane and gold backplates. The device had a zero bias capacitance of 2.4pF . During

63

normal operation, the amplifier was biased with a 9V dc supply. The bias resistor was a 16GΩ

poly resistor. The microphone output was buffered by a JFET input voltage follower that was

fabricated on the same chip. The microphone had a flat frequency response from 100Hz to

9kHz.

In 2003, Baker et al reported a JFET input preamplifier that used the current output of a

source follower as opposed to the traditional output voltage [92]. The amplifier was designed

for microphones used in cochlear implants. The amplifier was optimized for high power supply

rejection ratio (PSRR) which is a requirement for low noise design. The circuit operated on a 3V

power supply and had a flat frequency response up to 10kHz.

In 2004, Kern et al obtained a patent for a microphone interface circuit. The circuit biases

the microphone using large resistors from back-to-back diodes. Other performance metrics of the

circuit were not disclosed in the patent.

In 2005, Furst et al [84] of Sonion Technology obtained a patent for a two stage preamplifier

for an electret condenser microphone. It consists of a PMOS unity gain source follower driving

a NMOS gain stage. The circuit has an input capacitance of less than 10pF . Using a two stage

topology allows the independent tuning of the amplifier gain and the input capacitance. The

preamplifier is designed for use in telephony applications.

In 2006, Loeppert et al [94] presented the first commercial MEMS microphone. The

interface circuit consists of a voltage buffer with a 0.25pF input capacitance followed by a gain

stage. The microphone is biased by a 11V dc signal that is generated by a charge pump that is on

the same die as the amplifier.

General purpose operational amplifiers can also be used as interface circuits for capacitive

microphones using any of the packaging techniques listed in Table 3-1. Compared to custom

ICs, the input parasitic capacitance of these amplifiers are comparatively higher and is further

increased by the packaging technology used to connect the amplifier to the microphone. These

amplifiers are usually provided in open loop configuration. Thus, careful circuit design, which

may result in adding more components such as resistors and capacitors is required for the proper

operation of these amplifiers. These extra components may introduce parasitic capacitance

that have to be taken into consideration during the interface circuit design. A set operational

64

amplifiers recommended by the manufacturer for use as a voltage amplifier for microphones is

listed in Table 3-4 along with their performance specifications.

Table 3-4. Specification of a representative sample of operational amplifiers recommended bymanufacturers for use as voltage followers for capacitive transducers.

Model Number InputStage

Capacitance

Voltage Noise(Sv, fcv)

CurrentNoise

(Si, fci)

Bandwidth

AD8079(AnalogDevices)

1.5pF 3.2nV/√

Hz,2kHz

NR 20MHz

LM6211(NationalSemiconductors)

5.5pF 5.5nV/√

Hz,400Hz

NR 20MHz

TL2274 (TexasInstruments)

8pF 50nV/√

Hz ,200Hz

0.5fA/√

Hz,10Hz

2.25 MHz

OP285(AnalogDevices)

2.6pF 11nV/√

Hz ,10Hz

1.7pA/√

Hz,10Hz

6.5 MHz

3.3.2 Sensing Using A Charge Amplifier

Operating Principle. A charge amplifier consists of a opamp circuit with a capacitor in

the feedback path as shown in Figure 3-15. The inverting input is connected to the middle plate

of the microphone and the non-inverting input is grounded. RDC is a bias resistor that sets the dc

operating point of the amplifier input. The middle plate is biased at 0V by the principle of virtual

short between the non-inverting terminal and inverting terminal of the amplifier. The charge

flowing through the middle plate is integrated by the feedback capacitor Cint. The top and bottom

plates are biased at +Vdc and −Vdc respectively. The input-output relation of the circuit for a

capacitance change is given by the equation

Vout = −[

Vdc

Cint

]2∆C. (3–20)

Performance Metrics. From the input-output relationship given by Equation 3–20, the

electrical sensitivity of the circuit is given by the equation

Se =2Vdc

Cint

, (3–21)

which is twice that of a single backplate microphone. From the sensitivity equation, it can be

inferred that the sensitivity can be increased by increasing the bias voltage or decreasing the

65

Cint+-RDCC1C2-Vdc+Vdc Cp Ci VoutCL

Figure 3-15. Schematic of dual backplate microphone connected to a charge amplifier.

integrating capacitor. To determine the total output voltage noise PSD SVout , the noise modelC1 Cp Ci Cint +-RDC VoutCLC2 Zi SiRSva SiaFigure 3-16. Noise model of dual backplate microphone connected to charge amplifier.

shown in Figure 3-16 is used. Defining Ctot = 2C0 + Cp + Ci Zi = 1jω(2C0+Cp+Ci)

and

Zf = Rdc‖ 1jω Cint

, the total output noise PSD is given by

SVout = Sva

[1 +

(Zf

Zi

)]2

+ (SiR + Sia) Z2f . (3–22)

For frequencies above the cut on frequency i.e.(ω > 1

Rf Cint

), the output voltage noise PSD

equation can be simplified to

SVout = Sva

[1 +

(Ctot

Cint

)]2

+ (Sia + SiR)1

(ωCint)2 . (3–23)

66

Dividing SVout by the electrical sensitivity of the charge amplifier squared and taking the square

root, we obtain the minimum detectable capacitance per√

Hz is given by the equation

Cmin =Cint

2Vdc

√Sva

[1 +

(Ctot

Cint

)]2

+ (Sia + SiR)1

(ωCint)2 . (3–24)

From the equation for Cmin, it can be seen that the noise floor is increased by the parasitic

capacitance. Furthermore, the current noise PSD due to the bias resistor and the current noise of

the amplifier is shaped as 1/ω2 which increases the noise at low frequencies considerably.

The upper end of the dynamic range is limited by the maximum output voltage of the

amplifier and is dependent on the topology of the amplifier used. For a given power supply Vdd,

the maximum output voltage Vomax is determined by a circuit dependent voltage drop Vdrop below

the supply rails Vdd and is given by the expression

Vomax = Vdd − Vdrop. (3–25)

Dividing the above equation by the electrical sensitivity, the maximum input capacitance that can

be measured is

Cmax =Cint

2Vdc

[Vdd − Vdrop] . (3–26)

This shows that the upper end of the circuit dynamic range can be increased by decreasing the

top and bottom plate voltage and increasing the integrating capacitance.

The lower limit of the frequency response is set by the feedback capacitance and the

feedback resistor [83]. It is given by the expression

fl =1

2πRdcCint

. (3–27)

The upper end of frequency response of this circuit is determined by the bandwidth of the

amplifier and is dependent on the amplifier topology. For example, for a single stage folded

cascode amplifier with a transconductance gm, the bandwidth is given by the expression

fh =1

2π

gm

CL + Cint

. (3–28)

From the equation for fh, it can be inferred that the bandwidth is also increased when the Cint is

decreased.

67

Tradeoffs. The main advantage of the charge amplifier based circuit is the immunity of

the sensitivity to parasitic capacitance. The circuit sensitivity can be increased by reducing Cint

without increase in the noise floor. However, another consideration when reducing Cint is that

the bandwidth of the amplifier must be increased to ensure that there is sufficient loop gain for

the stable operation of the amplifier. Decreasing Cint to increase the sensitivity also reduces the

upper end of the dynamic range.

The main disadvantage of this circuit is the need for a large dc bias resistor Rdc because

the noise PSD due to this resistor is 1/f 2 shaped which considerably increases the noise at

low frequency. Choosing Rdc is a trade off between noise and the lower end of the frequency

response fl. Implementing a large Rdc resistor is non-trivial in an integrated circuit process.

Options include thick film resistors, back-to-back diodes, or low resistance poly resistors. Each

of these techniques has its own advantages and disadvantages[8]. Figure 3-17 shows a plot

10−5

100

105

1010

1015

1020

10−35

10−30

10−25

10−20

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Amplifier Voltage NoiseAmplifier Current NoiseResistor Current NoiseTotal Noise

Figure 3-17. Power spectral density of individual noise contributors and total output noise in acharge amplifier based interface circuit. (Low Voltage Noise Amplifier (OP471)Sv0 = 10nV/

√Hz, Si0 = 1.6pA/

√Hz, fcv = 10Hz, fci = 10Hz, Rdc = 44MΩ,

Cp = 10pF ,Ci = 2.6pF , 2C0 = 1.7pF )

of the PSD of various noise contributors in a charge amplifier and the total output referred

noise. It can be inferred that at low frequencies the resistor current noise is the dominant

noise mechanism and at higher frequencies the amplifier voltage noise is the dominant noise

mechanism. Figure 3-18 and Figure 3-19 plot the effect of scaling various circuit elements, on

68

the output noise PSD. Figure 3-18 shows a set of plots of the output noise PSD as the sensor

capacitance is scaled from 100pF to 1pF for various parasitic capacitance assuming a fixed bias

resistor of 10MΩ. Figure 3-18(a), Figure 3-18(c), and Figure 3-18(e) show these plots for a low

voltage noise amplifier and Figure 3-18(b), Figure 3-18(d), and Figure 3-18(f) show these plots

for a low current noise amplifier . It can be seen that, for a large fixed bias resistor(10MΩ), an

amplifier optimized for low current noise has a lower noise floor as compared to an amplifier

with low voltage noise. It can also be seen that this is true for all combinations of sensor and

parasitic capacitances. Figure 3-19 shows a set of plots of the output noise PSD as the sensor

capacitance is scaled from 100pF to 1pF for various bias resistors assuming a fixed parasitic

capacitor of 10pF . Figure 3-19(a), Figure 3-19(c), and Figure 3-19(f) show these plots for an

amplifier with low voltage noise and Figure 3-19(b), Figure 3-19(d), and Figure 3-19(e) show

the plots for a low current noise amplifier. It can be seen that, for a fixed parasitic capacitance,

an amplifier optimized for low current noise has a lower noise floor as compared to an amplifier

with low voltage noise where the difference in large for a large bias resistor.

Literature Review. Charge amplifiers are commonly used for capacitive accelerometers,

gyroscopes, and pressure sensors when the sensor is located at a distance far away from the

circuitry. To overcome the parasitics of the long parasitic leads, a charge amplifier is used.

Traditionally, in microphones, the output of the amplifier is buffered as close as physically

possible to the sensor. Therefore, very few capacitive microphones use a charge amplifier

interface circuit. Another common reason for the usage of voltage amplifiers over charge

amplifiers is the increased noise at low frequencies due to the 1/f 2 shaping of the current noise.

A summary of the literature survey is given in Table 3-5.

In 1999, Amendola et al. [96] reported a charge amplifier-based interface circuit for a

capacitive microphone.

The target applications for the microphone was measurements inside a resonant cavity

which had a narrow bandwidth centered at 25kHz. The amplifier had a simulated bandwidth

from 19Hz to 1.4MHz. The simulated sensitivity of the circuit was 2V/pC and a measured

sensitivity of 0.3V/pC.

69

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(a) Low Voltage Noise (Cp + Ci = 1pF )

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(b) Low Current Noise (Cp + Ci = 1pF )

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(c) Low Voltage Noise (Cp + Ci = 10pF )

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)Cs = 1pFCs = 10pFCs = 100pF

(d) Low Current Noise (Cp + Ci = 10pF )

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(e) Low Voltage Noise (Cp + Ci = 100pF )

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(f) Low Current Noise (Cp + Ci = 100pF )

Figure 3-18. Plot of output noise for charge amplifier with a fixed bias resistor (10MΩ).(Low Voltage Noise Amplifier (OP471) Sv0 = 10nV/

√Hz, Si0 =

1.6pA/√

Hz, fcv = 10Hz, fci = 10Hz, Low Current Noise Amplifier (TL2274)Sv0 = 10nV/

√Hz, Si0 = 0.01pA/

√Hz, fcv = 10Hz, fci = 10Hz)

70

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(a) Low Voltage Noise (Rdc = 100kΩ)

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(b) Low Current Noise (Rdc = 100kΩ)

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(c) Low Voltage Noise (Rdc = 10MΩ)

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)Cs = 1pFCs = 10pFCs = 100pF

(d) Low Current Noise (Rdc = 10MΩ)

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(e) Low Voltage Noise (Rdc = 1GΩ)

10−2

100

102

104

106

108

10−15

10−10

10−5

Frequency (Hz)

Noi

se (

V2 /H

z)

Cs = 1pFCs = 10pFCs = 100pF

(f) Low Current Noise (Rdc = 1GΩ)

Figure 3-19. Plot of output noise for charge amplifier with a fixed parasitic capacitance of(10pF ).(Low Voltage Noise Amplifier (OP471) Sv0 = 10nV/

√Hz, Si0 =

1.6pA/√

Hz, fcv = 10Hz, fci = 10Hz, Low Current Noise Amplifier (TL2274)Sv0 = 10nV/

√Hz, Si0 = 0.01pA/

√Hz, fcv = 10Hz, fci = 10Hz)

71

In 2005, Martin et al. [97] reported a dual backplate MEMS capacitive microphone for use

in aeroacoustic applications that used a commercial-off-the-shelf (COTS) Thermoptics DN620

charge amplifier which has a sensitivity of 1V/pC and a bandwidth of 100kHz. The feedback

elements consisted of a 1pF capacitor in parallel with a 1GΩ resistor.

Table 3-5. Review of charge amplifier interface circuits used in capacitive microphones.Author Type of

Sensor/SensorCapacitance

Sensitivity Feedbackcapacitor

Bandwidth Comments

Amendolaet al. 1999[96]

Microphone0.7pF

0.3V/pC witha 10V bias,

NR 19Hz −1.5MHz

JFET input custom amplifier.Uses a switched capacitortechnique to obtain stable

operationMartin etal. 2005[97]

Microphonedifferential

capacitor with1pF ,0.7pF

nominalcapacitance

1V/pC with a9V bias

1pF 300Hz−20kHz

COTS Thermoptics DN620[98] charge amplifier

Commercially available general purpose operational amplifiers can be used as a charge

amplifier by employing a feedback resistor and capacitor. A representative sample of general

purpose amplifiers that are recommended by the manufacturer for use as a charge amplifier by

using a feedback resistor and capacitor is listed in Table 3-6.

Table 3-6. Specification of a representative sample of general purpose operational amplifiersrecommended by the manufacturer for use as charge amplifiers using a feedbackresistor and capacitor.

Model Number Input Stage Noise Floor CornerFrequency

Bandwidth

OPA128 (TexasInstruments) [99]

DiFET 27nV/√

Hz 300Hz 1MHz

OPA111 (TexasInstruments) [100]

DiFET 8nV/√

Hz 300Hz 800kHz

AD745 (Analog Devices)[101]

FET 3.2nV/√

Hz 2kHz 20MHz

3.3.3 Sensing Using Synchronous Modulation/Demodulation

Operating Principle. The fundamental idea behind this technique is to improve the

noise performance [65, 46] of the circuit by modulating the capacitive signal to a high carrier

frequency above the low 1/f corner frequency of the amplifier. This high frequency signal is

then amplified and demodulated. During the demodulation and subsequent low pass filtering

process, the original signal is recovered and the noise is filtered out.

72

MultiplierVac sin(wct) Vout(Demod) Lowpass Filter+Vac sin(wct)

-Vac sin(wct) Cp CiC1C2 -+RDC vmod vdemodFigure 3-20. Schematic of capacitive microphone with a synchronous modulation and

demodulation technique using a voltage amplifier based circuit.

In this technique, the top and bottom plates are excited by a sinusoidal signal of equal

magnitude (Vac) but 180 degrees out of phase. The excitation frequency (ωc) is chosen to be

much higher ( 100×) than the resonant frequency of the sensor. This is done so as to prevent the

electrostatic excitation of the sensor by the ac waveform. The interface circuit used can be either

a voltage amplifier or a charge amplifier. A schematic of the system using a voltage amplifier and

charge amplifier interface circuit is shown in Figure 3-20 and Figure 3-21 respectively.

Charge Amp MultiplierVac sin(wct) Vout(Demod) Lowpass FilterCintVx+Vac sin(wct)-Vac sin(wct)

RdcCp CiC1C2 -+

Figure 3-21. Schematic of a capacitive microphone with a synchronous modulation anddemodulation technique using a charge amplifier based circuit.

The amplitude modulated (AM) signal is converted back to a baseband signal using a

synchronous demodulator. The carrier frequency used to demodulate the output of the charge

amplifier is phase locked to the modulating a signal applied to the top and bottom backplate. The

73

Frequency (Hz)Voltage (V) ffm fc(a) Spectrum of various signals involved in

synchronous modulation/demodulationtechnique

Frequency (Hz)Voltage (V) ffm fcfc-fm fc+fm(b) Spectrum of signals at the middle plate

of the microphone.

Frequency (Hz)Voltage (V) ffm fc(c) Spectrum of signal at output of demodulator

Frequency (Hz)Voltage (V) fm(d) Spectrum of signal at output of

low pass filter.

Figure 3-22. Plot of spectrum at various nodes of Figure 3-21

synchronous demodulator consists of an analog multiplier followed by a low pass filter. This

circuit overcomes the noise due to amplifier 1/f noise and the 1/f 2 shaped current noise of the

bias resistor and current noise of the amplifier by modulating high frequency carrier frequency

with the low frequency acoustic signal. This signal is then amplified, demodulated, and low pass

filtered to obtain the original signal. During the demodulation process the low frequency 1/f and

1/f 2 noise are modulated to the carrier frequency which is then filtered out while the acoustic

signal at the carrier frequency is translated to the baseband and passes through. The relation

between the capacitance input and the low pass filtered output of this technique is given by [46]

Vout = Hc

[V 2

ac

C0

]∆C. (3–29)

for a voltage amplifier and by

Vout =

[V 2

ac

Cint

]∆C. (3–30)

for a charge amplifier where U = 1V is a scale factor. The dimension of Equation 3–29 and

Equation 3–30 needs consideration. In practice, the demodulator [102] is implemented as an an

74

analog multiplier with a transfer function given by

Z =XY

U, (3–31)

where Z is the output of the multiplier measured in V olts, X and Y are the inputs to the

multiplier measured in V olts and U is a scale factor also measured in V olts. Thus, the output

of the demodulator has the dimension of V olts and Equations 3–29 and 3–30 are dimensionally

consistent.

Performance Metrics. From the input output relationship given by Equation 3–29 and

Equation 3–30, the electrical sensitivity of the circuit is given by the equation

Se =Hc

U

V 2ac

C0

[V/F ] . (3–32)

for a voltage amplifier and by

Se =V 2

ac

UCint

[V/F ] . (3–33)

for a charge amplifier.

From the above equation, it can be inferred that the sensitivity can be increased for both

interface circuits by increasing the peak ac bias voltage, Vac. The bias voltage can not be

increased without bound. There are two main factors that determine the maximum value of

the ac signal. They are the electrostatic pull-in limit which was discussed in Chapter 2 and the

actuation of the microphone plates by the electrical ac voltage instead of the input acoustic

signal. Although the frequency of excitation is 100× higher than the resonant the resonant

frequency, if the input amplitude is large, the diaphragm can vibrate at the high carrier frequency.

For the charge amplifier based interface circuit, the sensitivity can also be increased by

decreasing the value of the integrating capacitor. The minimum value of the integrating capacitor

is determined by the limitations of the fabrication process and the overall bandwidth of the

circuit.

For illustration, the sensitivity of a voltage amplifier based interface circuit using square

waves for modulation and demodulation is derived. Let the top plate voltage vtp and bottom plate

75

voltage vtp be given by

vtp = +Vdc − vac(t)

vbp = −Vdc + vac(t), (3–34)

where

vac(t) = Vac 0 < t <1

2

2π

ωc

vac(t) = 01

2

2π

ωc

< t <2π

ωc

. (3–35)

Also, let us assume that the demodulator voltage Vc(t), is given by

Vc(t) = Vc 0 < t <1

2

2π

ωc

Vc(t) = 01

2

2π

ωc

< t <2π

ωc

. (3–36)

The output of the demodulator, vdemod(t), is given by the expression

Vdemod(t) = vmod(t)× Vc(t). (3–37)

The output of the demodulator is low pass filtered. From Equation 4–4, it can be seen that

demodulation is a non-linear operation. The entire process of demodulation and low pass filtering

can be linearized by ignoring the harmonics at the output of the low pass filter as they will be

attenuated by the filter. Thus, ignoring the harmonics which are attenuated by the low pass filter,

the output of the filter can be shown to be

Vout(t) =∆C

C0

Hc

U

(Vc

2

(Vdc +

Vac

2

)+

2Vc

π

2Vac

π

), (3–38)

for a voltage amplifier and

Vout(t) =∆C

Cint

1

U

(Vc

2

(Vdc +

Vac

2

)+

2Vc

π

2Vac

π

). (3–39)

for a charge amplifier. The derivation of the above equation is provided in Appendix A.5. Thus,

the sensitivity is given by

Se =Hc

C0

1

U

(Vc

2

(Vdc +

Vac

2

)+

2Vc

π

2Vac

π

), (3–40)

76

for a voltage amplifier and

Se =1

Cint

1

U

(Vc

2

(Vdc +

Vac

2

)+

2Vc

π

2Vac

π

). (3–41)

For the reminder of this section, we use the simplified sensitivity. To determine the

total output noise, the noise model shown in Figure 3-23 is used for a voltage amplifier and

Figure 3-24 is used for a charge amplifier. For the voltage amplifier interface circuit, the totalCp CiC1C2 MultiplierVac sin(wct) Vout(Demod) Lowpass Filter-+RdcZi Sva SiaSvR Voltage Buffer SmultiplierFigure 3-23. Noise model of synchronous modulator and demodulator using voltage amplifier.

Cint +-RDC CLCp CiC1C2 MultiplierVac sin(wct) Vout(Demod) Lowpass FilterCharge AmpSiaSiRSva Smultiplier

Figure 3-24. Noise model of synchronous modulator and demodulator using charge amplifier.

input noise is given by

SVout = Sva + Sia (Zi ‖ Rdc)2 +

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

SvR + Smultiplier, (3–42)

where Zi = 1jω(2C0+Cp+Ci)

and Smultiplier is the output referred noise PSD of the multiplier. For

the charge amplifier interface circuit, the total output noise is given by

SVout = SV a

[1 +

(Ctot

Cint

)]2

+ Smultiplier. (3–43)

77

Dividing the total output noise, Equation 3–42 and Equation 3–43, by the corresponding

electrical sensitivity, we obtain the minimum detectable capacitance and is given by the equation

Cmin =(2C0 + Cp + Ci) U

V 2ac

√SV a + Sia (Zi ‖ Rdc)

2 +

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

SvR + Smultiplier. (3–44)

for a voltage amplifier and

Cmin =CintU

V 2ac

√Sva

[1 +

(Ctot

Cint

)]2

+ Smultiplier. (3–45)

for a charge amplifier. The upper end of the dynamic range is the same for both interface circuits

and is given by

Vomax = Vdd − Vdrop. (3–46)

Dividing the maximum output voltage equation by the corresponding electrical sensitivity, the

maximum input capacitance that can be measured is given by

Cmax =(2C0 + Cp + Ci) U

V 2ac

[Vdd − Vdrop] . (3–47)

for a voltage amplifier and

Cmax =CintU

V 2ac

[Vdd − Vdrop] . (3–48)

for a charge amplifier. This shows that the upper end of the dynamic range can be increased by

decreasing the peak ac bias voltage, Vac for both interface techniques.

The lower limit of the frequency response is the same as the dc voltage amplifier and charge

amplifier techniques considered previously. It is given by the expression

fl =1

2πRdc (2C0 + Cp + Ci). (3–49)

for a voltage amplifier and

fl =1

2πRdcCint

. (3–50)

for a charge amplifier. The upper limit of the frequency response of this circuit is determined by

the cutoff frequency flpf of the low pass filter and is given by the expression

fh = flpf . (3–51)

78

Tradeoffs. This technique has all the advantages of the voltage and charge amplifier

techniques with the additional benefit that the 1/f and 1/f 2 noise components are attenuated. It

does not suffer from the problem of aliasing of the broadband white noise of the amplifier to the

baseband as is the case in switched capacitor based circuits. The circuit is purely analog in nature

and reduces the demands placed on layouts as routing mixed signal circuits is avoided.

There are two main disadvantages with this technique. A large bias resistor is needed for the

operation of the circuit. Implementing this resistor is a non-trivial problem. For example, in the

ADXL-50, a 3MΩ resistor was used and was fabricated using a special resistor layer. Another

solution is to use back-to-back diodes. The issues in using back to back diodes are leakage

currents and poor transient performance. The second major disadvantage of this technique

is the use of the low pass filter. The low pass filter will cause phase delay which needs to be

compensated when used in closed-loop operation as will be shown in Section 3.5.1. Furthermore,

the multiplier noise, increases the output noise.

Literature Review. In this section, a review of capacitive transducers, especially

capacitive microphones and accelerometers, that utilize synchronous modulation and demodulation-based

interface circuits is presented. A summary of the literature survey is provided in Table 3-7.

Table 3-7. Summary of previous synchronous modulation/demodulation based open loopcapacitive transducer interface circuit.

Author / Type ofTransducer

TransducerBandwidthOpen Loop

NominalCapacitance

CarrierSignal

Sensitivity Comments

Kraft et al.1998 [104](accelerometer)

56 7.2pF 5Vpp

1MHz700mV/g Charge amplifier

interface circuitLi et al. 2000 [103] NR NR NR 75V/g Charge amplifier

interface circuitYakabe et al.2006 [105] (patent)

NR NR NR NR Charge amplifiercircuit using a two

opamps.

In 2000, Li et al. 2000 [103] reported an open loop accelerometer using synchronous

modulation/demodulation as the interface circuit. They reported a sensitivity of 75V/g when

the input was in ±0.1g range. The characteristics of the carrier signal and the bandwidth of the

device was not reported.

79

Kraft et al.[104] reported an analog open loop accelerometer that used 2Vp−p 1MHz carrier

signal. The device had a reported sensitivity of 0.7V/g and a bandwidth of 300Hz. The open

loop bandwidth of the device was 56Hz.

Yakabe et al. [105] obtained a patent for a modified form of a voltage amplifier synchronous

modulation based interface circuit that allows for reduced sensitivity to parasitic capacitance.

This is accomplished by placing the sensor output signal, an extra feedback capacitor, and an

auxiliary opamp in the feedback path of a primary amplifier. No details of the performance

specifications are presented.

3.4 Digital Open Loop Sense Techniques

Digital sense techniques are interface circuits in which the continuous time output of the

sensor is converted to discrete time signals by sampling the sensor output and then processing

the sampled data. These circuits are implemented using switched capacitor circuits [79]. In these

circuits, a resistor is replaced with appropriately connected MOSFET switches and capacitors

and driven by non-overlapping clock waveforms that simulate a resistor. Switched capacitors

thus eliminate the need for large resistors. Switched capacitors using the technique of correlated

double sampling (CDS) [106] can attenuate dc offsets and 1/f noise from the interface circuit.

The fundamental idea in the CDS scheme is to measure the noise dc offset voltage at some

instant of time and subtract it from the measured signal during the next instant. This is performed

in two phases which are time multiplexed. During the sampling phase, the noise and offsets are

measured and stored. Afterwards, during the signal processing phase the offset free amplifier is

available for operation. The operation performed by the system can be expressed in terms of the

output signal y[n], the input signal x[n], and the 1/2 period previous input signal x[n− 12] by the

equation

y[n] = x[n]− x[n− 1/2]. (3–52)

Using the z-transform, the transfer function H(z) of the above system can be expressed as

H(z) = 1− z−12 . (3–53)

80

Substituting z = ejwT and simplifying, we can obtain the magnitude transfer function as

∣∣H(ejw)∣∣ = 2sin

(ωT

4

). (3–54)

It can be seen from this transfer function that the CDS operation puts a zero at dc (i.e ω = 0)

and has a high pass response for increasing frequencies up to the Nyquist frequency. Thus,

theoretically, CDS eliminates dc offsets and high pass filters the input signal.

Sensing Using Switched Capacitor Amplifier. Figure 3-25 shows one implementation

of a switched capacitor amplifier that implements CDS. The switched capacitor amplifier

VoutCLC1C2+ V Cp Ci +-CresetCgain0 V 0 V Vcm

- VFigure 3-25. Switched capacitor implementation of correlated double sampling.

consists of two capacitors Cgain and Creset and four switches arranged as shown in Figure 3-25.

The output common mode voltage, Vcm, is chosen so as to maximize the output range. For a

circuit with 0 − 5V supply rail, Vcm is chosen to be 2.5V. The switches are driven with two non

overlapping clocks φ1 and φ2.

The equivalent circuit during each clock phase is shown in Figure 3-26. During the reset

phase (φ1), the noise voltages are measured and stored on the integrating capacitor. During the

amplify phase (φ2), the circuit performs the actual measurement. To perform the measurement,

step voltages of equal magnitude ∆V but opposite in sign are applied to the top and bottom

plates respectively. The input output relation during the amplify phase is given by [79],

Vout =

[∆V

Cgain

]2∆C. (3–55)

81

-+CresetCgain Vcm-+0 CLVout(a) Reset Phase φ1.

-CgainCreset-CgainCreset0 +0

CL Vout(b) Amplify Phase φ2.

Figure 3-26. Equivalent circuit of switched capacitor amplifier during amplify and reset phase.

Performance Metrics. From the input output relationship given by the above equation,

the electrical sensitivity of the circuit is given by the equation,

Se =2∆V

Cgain

. (3–56)

From the above equation, it can be inferred that the sensitivity can be increased by varying the

height of the sampling pulse or decreasing the integrating capacitor.

The noise analysis of the switched capacitor network is done using a simplified model for

the amplifier noise based on the work by Gobet et al [107]. The complete noise model is shown

in Figure 3-27. The detailed derivation of the noise sources is in Appendix B. The noise analysisC1=C0C2=C0 -CgainCreset-CgainCreset+V+

CL Voutv2nCp 4kTRonRonFigure 3-27. Noise model of switched capacitor amplifier during amplify phase.

82

of this technique is based on the work by Wongkomet [108]. The switched capacitor interface

circuit is an oversampled system. The main sources of noise are the kT/C noise associated with

the switches and the wide band white noise of the amplifier that is aliased to the baseband. The

total capacitance CT at the input of the amplifier that is sampled by the switches is

CT = 2C0 + Cp + Cgain. (3–57)

The total kT/C noise at the output can be expressed in terms of the sampling frequency, fs, the

total capacitance, CT , and the gain capacitance Cgain, and is given by

SkT/C =1

fs

[CT

Cgain

]2kT

CT

. (3–58)

The total sampled wide band noise at the output v2opamp noise at the output can be expressed

in terms of the sampling frequency, fs, the total capacitance, CT , the gain capacitance Cgain, and

the unity gain bandwidth fu of the amplifier by

Svopamp =

[CT

Cgain

]2

Svnfu

fs

π

2. (3–59)

Adding Equation 3–58 and Equation 3–59 we obtain the total output noise as

Svo =1

fs

[CT

Cgain

]2kT

CT

+

[CT

Cgain

]2

Svnfu

fs

π

2. (3–60)

Equation 3–60 can be divided by the sensitivity to determine the minimum detectable

capacitance per√

Hz and is given by the expression

Cmin =

√1

fs

[CT

2∆V

]2kT

CT

+

[CT

2∆V

]2

Svnfu

fs

π

2. (3–61)

The upper end of the circuit dynamic range is limited by the maximum output voltage of the

amplifier and is dependent on the topology of the amplifier used. It is given by the expression

Vomax = Vdd − Vdrop. (3–62)

Dividing the above equation by the electrical sensitivity the maximum input capacitance that can

be measured is given by

Cmax =Cint

∆V[Vdd − Vdrop] . (3–63)

83

This shows that the upper end of the circuit dynamic range can be increased by decreasing the

height of the sense pulse and increasing the integrating capacitor.

The bandwidth of this circuit is determined by the closed-loop bandwidth of the amplifier.

Based on the discussion in Appendix B, for a switched capacitor amplifier, the closed-loop

bandwidth fu can be expressed in terms of the duty cycle of the sense phase m(< 1), number of

settling time constants nτ , and the sampling frequency fs, [41]

fu =1

2π

[m

nτfs

]−1

. (3–64)

The amplifier core is made of a folded cascode amplifier whose open-loop bandwidth famp is

given in terms of the total output capacitance CLT ,

CLT = CL + Cgain||(Cp + 2C0), (3–65)

by the expression

famp =1

2π

gm

CLT

. (3–66)

The closed-loop bandwidth fu is related to the open-loop bandwidth famp by the feedback factor

β,

β =CT

Cgain + CT

, (3–67)

by the expression

fu = βfamp. (3–68)

Tradeoffs. The main advantage of this technique is that it eliminates the need for the

bias resistor, making this technique easily amenable for standard IC processes. It has the

advantage of the synchronous modulation/demodulationtechnique in that it reduces the 1/f

noise components. Furthermore, it removes the dc offset which is not done by the synchronous

modulation/demodulation technique.

The main disadvantages are as follows. Being a sampled data system, the wideband noise

of the amplifier is aliased into the baseband thus increasing the noise floor in the bandwidth of

interest. This problem is not present in the synchronous modulation/demodulation technique.

To mitigate this effect, the minimum allowable closed-loop bandwidth must be chosen for the

amplifier. Based on the discussion in Appendix B, the minimum closed-loop bandwidth is given

84

by

fu =1

2π

[m

nτfs

]−1

. (3–69)

Literature Review. In 2001, Yamada et al. [66] reported a switched capacitor interface

circuit for capacitive pressure sensors with a sense capacitor of 1nF .. The interface circuit was

implemented using discrete components. The clock frequency used was 10kHz with a reset

capacitor of 3.9nF and a reset capacitor of 101.2pF .

In 2004, Potter et al. of Knowles Acoustics received a patent [109] for a switched capacitor

based interface circuit for a capacitive microphone. It is designed so as to reduce the input offset

voltage and 1/f noise. Performance specifications were not specified in the patent.

In 2006, Jawed et al [110] presented the simulation results of a switched capacitor based

interface circuit for a single backplate capacitive microphone. The nominal capacitance of the

microphone was 4.5pF and the pull in voltage was equal to 3.5V . The parasitic capacitance was

on the order of a few pF . The microphone had a bandwidth extending from 50Hz to 20kHz.

The circuit is a simpler version than the structure shown in Figure 3-25. It has only one feedback

capacitor and uses a fixed on-chip poly-poly dummy capacitor to form a pseudo-differential

structure.

3.5 Closed-Loop Sense Techniques

The fundamental concept behind the closed-loop schemes in capacitive sensors is to use an

external force to balance the force due to the input phenomenon. In capacitive microphones, a

voltage source generates an electrostatic force which counters the pressure induced deflection and

restores the diaphragm to its equilibrium position. The voltage used to generate the electrostatic

force is thus a measure of the input acoustic signal. This section is based on the work developed

by Hunt [111].

In closed-loop schemes, there are two phases of operation, namely sense and feedback.

During the sense phase, the capacitance change is measured and during the feedback phase, an

electrostatic force is applied using a voltage to either the backplate or the diaphragm to null the

deflection. These two phases are separated in time in the case of digital closed-loop schemes

and in frequency in the case of analog closed-loop schemes. This separation is essential and is

done to prevent the excitation signal used to the measure the capacitance change from interfering

85

with the feedback signal [69]. To implement the force feedback scheme, there are two common

approaches. In one approach, a separate set of plates for sense and force feedback [68, 67, 11] are

used while for another approach, the same plates can be multiplexed for the sense and feedback

phase [2, 112].

The main advantages of the closed-loop approach is increased linearity and dynamic range

[11, 42, 113]. Bandwidth improvement beyond the resonant frequency is also predicted for the

analog closed-loop interface circuit approach. Since the feedback electrostatic force keeps the

plate at the center position, the diaphragm becomes much stiffer than the simple open-loop case

which results in increased bandwidth. Force feedback also allows one to use higher voltages by

reducing instability due to pull-in voltage and thereby increasing the sensitivity.

The advantages provided by the closed-loop schemes come with their own limitations

and constraints. Since the sensor is a feedback loop, the stability of the loop must be carefully

considered during the design of the electronics. Large voltages, which might not be easily

available in current CMOS technologies, may be required to balance large input sound pressure

levels. For example, to force balance a 160dB acoustic signal, approximately 45V is required

which is not a commonly available voltage in standard IC processes.

The detailed operating principle of the various closed-loop techniques and their performance

metrics are discussed next.

3.5.1 Sensing Using Closed-Loop Analog Interface Circuit

In the closed-loop analog force feedback technique, the sense and feedback signal are

separated in frequency. In this technique, the sense phase is similar to the open-loop synchronous

modulation and demodulation technique discussed earlier. Thus, for the sense phase the top

and bottom plate are biased with a high frequency ac modulation signal Vacsin(wct) of equal

magnitude but of opposite polarity. For the feedback phase, a low pass filtered version of the

demodulated output signal denoted by vf is used. The voltage required to produce a net feedback

force is generated by summing vf to a dc bias voltage Vdc of equal magnitude but of opposite

polarity applied to the top and bottom electrode respectively.

The design of the dc bias voltage is discussed later in this section. Thus, three different

voltages are summed and applied to the top and bottom plates. The top and bottom plate voltages

86

vtp and vbp is thus given by

vtp = +Vacsin(wct)− Vdc + vf (3–70)

vbp = −Vacsin(wct) + Vdc + vf .

Figure 3-28 shows a schematic of the analog closed-loop technique.

MultiplierVc (t) Vout(Demod) Lowpass Filtervmod-Vdc+vac (t)+vfVdc-vac (t)+vf Cp CiC1C2 Feedback signal at base bandCompensatorvf -+ vdemodRDC

Figure 3-28. Schematic of analog closed-loop force feedback scheme.

The net force acting on the movable plate ∆F can be expressed as the difference between

the force, Ftp, acting between the top plate and the middle plate and the force, Fbp, acting

between the bottom plate and the middle plate and is given by the expression

∆F = Ftp − Fbp. (3–71)

Assuming that the middle plate is kept at ground potential because of negative feedback of the

amplifier and using Equation 2–61, Ftp and Ftp are given by the expressions

Ftp =1

2εA

v2tp

[x0 − x′]2, and (3–72)

Fbp =1

2εA

v2bp

[x0 − x′]2.

Substituting Equation 3–70 and Equation 3–72 in Equation 3–71, neglecting high frequency

terms as they will be filtered by the low pass filter, and assuming x′ << x0, we obtain

∆F = 2εAx0x

′((

2πVac

)2+

(Vdc + Vac

2

)2+ v2

f

)− (

Vdc + Vac

2

)x2

0vf

x40

. (3–73)

87

During steady state operation, the displacement of the middle plate is highly attenuated i.e.

x′ ≈ 0. (3–74)

Substituting Equation 3–74 in Equation 3–73, for small displacements we obtain

∆F = 2εAVdc + Vac

2

x20

vf . (3–75)

Equation 3–75 shows that for small displacements (i.e. x′ << x0), the net electrostatic force on

the middle plate is a linear function of the feedback voltage.

The design of the bias voltage is based on the force corresponding to the maximum pressure

Pmax that the sensor has to balance. By equating the work done by the electrostatic force

between the plates of a capacitor to the mechanical work done for an applied pressure Pmax, we

obtain the voltage required Vdc

Vdc =

√2Pmaxx2

0

ε0

. (3–76)

Performance Metrics. The sensitivity of this technique is the same as that of the

synchronous modulation/demodulation technique using a voltage amplifier. It is given by

Se =Hc

C0

(2Vc

π

2Vac

π

). (3–77)

The noise floor is given by

SVout = Sva + Sia |(Zi ‖ Rdc)|2 +

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

SvR. (3–78)

The low frequency cut off is the same as that of a voltage buffer based interface circuit and is

given by

fl =1

2πRdc (2C0 + Cp + Ci). (3–79)

The upper end of the bandwidth is determined by the closed loop response of the system. As the

closed loop system is non-linear, a closed form expression is not available. An estimate of the

system bandwidth can be determined graphically by plotting the magnitude frequency response

of the linearized closed loop system.

Literature Review. Table 3.5.1 provides a review of microphones and accelerometers

that use a synchronous modulation and demodulation based interface circuit. It can be seen that

88

this technique is commonly used for low bandwidth applications i.e. mainly accelerometers.

The reason for this is that simultaneously meeting carrier frequency requirements and feedback

voltage requirements is a challenging problem with current semiconductor technology. One way

in which the high frequency required for sensing can be overcome is to sense the diaphragm

position using optical techniques [114] and use electrostatics only for the feedback phase.

Commercially the synchronous modulaiton/demodulation technique has been used in the Analog

Devices (ADXL-50) accelerometer.

Table 3-8. Summary of previous synchronous modulation/demodulation based closed-loopcapacitive transducer interface circuit.

Author / Type ofTransducer

TransducerBandwidth

Open Loop /closed-loop

NominalCapacitance

CarrierSignal α

Sense /Feedbackcapacitors

Comments

van der Donk et al1992 [115] (singlebackplatemicrophone) (Design1)

30Hz /400Hz

NR NR1MHz

Commonplates

van der Donk et al1992 [115] (singlebackplatemicrophone) (Design2)

400Hz /7kHz

NR NR1MHz

Commonplates

Hadjiloucas et al.,1995 [116] (singlebackplatemicrophone)

NR / 50kHz(Theoretical)

NR NR NR Commonplates

Optical sensingusing Fabry-Perot

interferometer.

Hall et al.,2005 [114](singlebackplatemicrophone)

Diaphragmresonance at44.8kHz

(Theoretical)

NR NR NR Commonplates

Optical sensingusing Michaelson

interferometer.

Analog Devices1993 [2](accelerometer)

14kHz /1kHz

NR 5Vpp

2.5MHzCommon

platesCommercially

available

Kampen et al 1994 [7](accelerometer)

NR / NR NR 2Vpp

1MHzCommon

platesPark et al. 1998 [112](accelerometer)

NR / 350Hz 0.4pF 1Vpp

50kHzCommon

platesSensitivity is

39mV/g

Kraft et al.1998 [104](accelerometer)

56 / 300Hz 7.2pF 5Vpp

1MHzCommon

platesSensitivity is700mV/g

Luo et al.2002 [117](accelerometer)

8.9kHz /400Hz

0.064pF 1V pp2MHz

Separateplates

Sensitivity is2.2mV/g Noise

Floor is 1mg/√

Hzα Peak to Peak Voltage,Frequency

In 1992, van der Donk et al. [115] reported analog closed loop control for a single backplate

microphone. The microphone consisted of interdigitated electrodes with acoustic holes on the

89

backplate. Two different microphone designs were tested. One of the microphones consisted of

a two fingers with 16 acoustic holes and an open loop −3dB frequency of 30Hz. The second

microphone consisted of 10 fingers with 81 acoustic holes and an open loop −3dB frequency

of 400Hz For both microphones, a bias voltage of 7V were used. A 1MHz carrier signal used.

In closed-loop operation, the bandwidth of the two microphones increased to 400Hz and 7kHz

respectively. The feedback loop was compensated using a simple proportional gain controller.

In 1995, Hadjiloucas et al. [116] reported a force feedback microphone that uses optical

sensing and electrostatic force feedback. The movement of the microphone diaphragm is

detected using a Fabry-Perot interferometer. Since the diaphragm position is detected optically,

no ac signal is required for the operation of this sensor.

In 2005, Hall et al. [114] reported a measurement microphone that uses optical sensing with

electrostatic force feedback. The sensing is done using a Michaelson interferometer. The laser

required for sensing is integrated on the sensor itself using a vertical cavity surface emitting laser.

The backplate of the microphone is perforated and integrates the diffraction gratings. The paper

does not report any closed-loop results.

Next, closed loop accelerometers are discussed. In 1993, Analog Devices ADXL-50 [2]

produced a commercial accelerometer that uses closed-loop control with a 2Vp−p, 1MHz carrier

signal. It uses the same plates for both sense and feedback.

In 1994, Kampen et al. [7] reported a closed-loop accelerometer that uses a 2Vp−p 1MHz

carrier signal. In this design, the same capacitor was used for both sense and feedback. No

performance metrics of the accelerometer is provided.

In 1998, Kraft et al. [104] reported a analog closed-loop accelerometer that uses a 2Vp−p

1MHz carrier signal. The device has a reported sensitivity of 0.7V/g and a bandwidth of

300Hz. The open loop bandwidth of the device is 56Hz.

In 1998, Park et al. [112] reported a closed loop accelerometer that uses a 1Vp−p 50kHz

carrier signal. The sensitivity of the accelerometer is 39mV/g and the closed-loop bandwidth is

350Hz. This sensor uses the same plates for sensing and feedback.

In 2002, Luo et al. [117] reported a lateral accelerometer with a linear range of ±13g and

a noise floor of 1mg/√

Hz. The carrier signal used was a 1Vp−p 2MHz signal. The sense and

demodulation circuitry is on the same die as the sensor. In this sensor, separate capacitors are

90

used for sense and force feedback. The sensor resonant frequency is 8.9kHz. A compensator

consisting of a single pole low pass filter at 400Hz is introduced in the forward path after the

demodulator which limits the bandwidth.

In 1990 Joyce et al. [118] reported a capacitive force for atomic force microscopy that

uses analog closed-loop force feedback. The nominal capacitance of the sensor is 0.4pF and

the resonant frequency is 30kHz. The sensor was excited with a 2.5MHz carrier signal. They

report a minimum detectable force of 10−8N which corresponds to a displacement of 0.5nm for

a bandwidth of 1kHz.

3.5.2 Sensing Using Digital closed-loop Interface Technique

In the digital technique for closed-loop force feedback, the sense and feedback signals are

time-multiplexed. The ∆Σ modulation based force feedback technique is used. In this section,

the general operating principle of a first order ∆Σ modulator is first explained. This principle is

then extended to a case study of a ∆Σ modulator interface technique for the microphone.

∆Σ modulation is a technique used in high precision analog-to-digital converters (ADC).

∆Σ modulators are inherently oversampled systems and trade precision in time for precision

in amplitude. This allows one to use coarse analog circuitry with precise digital circuitry for

analog to digital conversion. The principle of operation of the ∆Σ modulation is illustrated in

the block diagram of a first order ∆Σ modulator shown in Figure 3-29. It consists of a discrete

time integrator whose output is quantized using a one-bit quantizer. The input to the integrator

is the error between the analog input signal and the quantizer output. The system is operated at

a sampling frequency, fs, that is much higher than the Nyquist frequency fN of the input signal.

Over many periods, the average error signal e is driven to zero by the feedback loop assuming

that the loop is properly compensated. The input information can be recovered from the output

bitstream by low pass principle is used as an interface technique, the discrete time integrator is

replaced by the microphone which is modelled as a second order system. Figure 3-30 shows

a schematic of the mechanical ∆Σ modulator. The forward path is represented via three

physical blocks namely, the microphone, a charge amplifier, a discrete time compensator and a

comparator. The feedback path is represented via two functional blocks (digital to analog (D/A)

converter and voltage to force (V/F) block) which represent the electrostatic feedback force

91

+ - Decimationand Lowpass filterIntegrator QuantizerFirst Order DeltaSigma Loop 1 >1AnalogInput 11-z-1e

Figure 3-29. Schematic of first order ∆Σ modulator.

applied on the plates at an instant of time. The summing node computes the difference between

the force corresponding to the input acoustic pressure signal and the electrostatic feedback force.

A feedback force is applied over time that nulls this error signal.Sensor+-InputPressure Area 2-z-1CompensatorComparator DigitalBitstreamx/C D/AAmpMechanicalDomain ElectricalDomainV/FFigure 3-30. Schematic of second order mechanical ∆Σ modulator.

Operating Principle. The operation of the system is divided into the sense phase during

which time the capacitance is measured and the feedback phase when an electrostatic force

is applied to the backplates to null the diaphragm deflection. During the sense phase, the

displacement of the diaphragm is first converted into a capacitance change by appropriately

biasing the top and bottom plates. This capacitance change is measured using the switched

capacitor technique discussed earlier in the open-loop techniques. The output of the charge

amplifier is given as the input to a two tap finite impulse response (FIR) filter. The compensator

is used to stabilize the second order loop. The output of the filter is quantized via a comparator

which produces a high speed single bit output signal at the over sampling frequency. The one bit

output is used during the feedback phase. This signal drives the logic that generates the feedback

92

signal which is then applied to the top and bottom plate. This one bit signal is decimated and low

pass filtered to obtain a multibit word that represents the input acoustic signal.

Performance Metrics. The noise floor of the ∆Σ modulation based interface is

determined by the quantization noise. Assuming that the noise floor Pe is dominated by the

quantization noise, it can be expressed in terms of the oversampling ratio M by [79]

Pe ' ∆2π4

60M−5 (3–80)

The ∆Σ modulator is a non-linear closed-loop system. Linear systems theory cannot be

applied for the analysis of these systems. Some of the existing work in the literature [119, 6]

do not discuss the bandwidth variation with closed-loop ∆Σ techniques. Kraft [69] discusses

an analytic method using the describing function technique [120] to qualitatively predict the

bandwidth improvement. The conclusion based on his work is that the feedback voltage increases

the sensor bandwidth as long as the input signal frequency is below the limit cycle frequency

predicted by the describing function analysis.

Tradeoffs. The main advantage of this technique is that the time averaged feedback force

is derived from the number of fixed height, fixed width pulses applied to the top and bottom

plates and not the amplitude of the feedback voltage. This provides a linear feedback voltage to

force relationship which was not possible with the analog closed-loop technique.

The main disadvantage of this technique is the complexity of the circuit. The other

disadvantages of this technique as we scale device geometries down are discussed in the next

section on scaling.

3.6 Scaling Analysis of ∆Σ Interface Techniques

In this section, the circuit requirements for the ∆Σ modulator as we scale device geometry

is analyzed. In general, for a given material, as the size of the mechanical element is reduced,

the resonant frequency increases. Therefore, to obtain the same performance using the ∆Σ

based interface technique, the oversampling frequency must be increased. With the increased

oversampling frequency, high bandwidth amplifiers are required to meet the settling time

constraints. High bandwidth amplifiers imply larger device geometry which in turn leads to large

parasitics that increase the noise floor.

93

To get an understanding of the frequency consideration, Table 3-9 shows a comparison of

the sampling frequencies required for sensors with increasing resonant frequencies. The target

dynamic range is 120dB. To achieve the target dynamic range, a second order modulator needs

an oversampling ratio of approximately 725. This is rounded up to 1000X to provide a margin

of safety. To determine the closed-loop bandwidth fu, we use Equation 3–69 with nτ = 7 (i.e.

0.1% settling), and m = 0.25 (i.e. 25% of time spent in sense phase). The next issue to consider

Table 3-9. Frequency requirements of ∆Σ interface circuits with increasing resonant frequency.Property Accelerometer Audio microphone Aeroacoustic

microphonefres 1kHz[8] 20kHz 200kHzfs 1MHz[8] 20MHz 200MHzfu 4.5MHz 90MHz 900Mhz

for high dynamic range capacitive sensors using feedback techniques is the voltage required

to balance the input at maximum input signal level. Table 3-10 shows the voltage required to

balance the maximum pressure for audio grade and aeroacoustic microphones. From Table 3-9

Table 3-10. Feedback voltage requirements of ∆Σ interface circuits with increasing dynamicrange.

Property Audio microphone Aeroacoustic microphoneMaximum input 120dB 160dB

Feedback voltage 6V 45V

and Table 3-10, it can be seen that designing a ∆Σ modulation based controller for aero acoustic

application is a non-trivial problem. This is because current semiconductor manufacturing

process technologies do not have 45V processes which support amplifiers with a 900Mhz gain

bandwidth product. One method to overcome this problem is to use separate voltages for sensing

and feedback using off chip drivers.

Literature Review. Table 3.6 provides a review of capacitive transducers using ∆Σ

based closed-loop techniques. This technique has been reported extensively for capacitive

accelerometers. The use of this technique for closed loop force feedback in high bandwidth

operations is very challenging due to the large simultaneous gain bandwidth and voltage

requirements for these applications.

The first digital closed-loop accelerometer was reported by Henrion et al.[42] in 1990. The

system operates at a clock frequency of 512kHz. The reported system sensitivity is 1V/g. The

94

Table 3-11. Summary of previous ∆Σ based closed-loop capacitive transducer interface circuit.Author / Type ofTransducer

TransducerBandwidth

Open-Loop /Closed-loop

NominalCapacitance

ClockFrequency

Sense /Feedbackcapacitors

Comments

Henrion et al.,1990 [42](accelerometer)

266 Hz /350 Hz

NR 512kHz Commonplates

Sensitivity is 1V/g

Yun et al., 1992 [6](accelerometer)

Theoreticalresonant

frequency ofsensor15kHz

NR 1MHz Separateplates

Only open loopmode of operationwas tested thought

the chip has theelectronics forclosed-loop.

Wu et al., 1992 [121](microphone)theoretical paper

25kHz NR 5MHz Commonplates

Kraft et al.,1998 [104](accelerometer)

NR 7.2pF 500kHz Commonplates

Lemkin et al.,1998 [122](accelerometer)

Theoreticalresonant

frequency ofsensor

3.4kHz

101fF 500kHz Commonplates

Sensitivity is 1V/g,Noise floor is

110µg/√

Hz (Onlyx-axis data is

presented)Moon et al.,2000 [123, 10](accelerometer)

Theoreticalresonant

frequency ofsensor15kHz

0.1pF 1MHz Separateplates

Edelson 2001 [124](microphone)

NR / NR NR NR NR NR

resonant frequency of the sensor was 266Hz and the measured resonant frequency with the

electronics use 350Hz.

In 1992, Yun el al. [6] reported the design of a digital closed-loop accelerometer. In this

design separate capacitors was used for sense and feedback. The fabricated device was tested

only in the self test open loop mode using electrical excitation.

In 1994, Wu et al. [121] presented a theoretical paper on the design of a ∆Σ based

closed-loop controller. The proposed interface circuit uses interferometric optical sensing to

determine the diaphragm position of a dual backplate microphone and electrostatic feedback. The

circuit is designed to have a overall system bandwidth of 25kHz. The oversampling frequency

used is 5MHz.

95

In 1998, Kraft et al. [104] reported a digital closed-loop accelerometer that uses a10kHz

clock signal. The open loop bandwidth of the device is 56Hz and the closed-loop bandwidth is

300Hz.

In 1998, Lemkin et al. [122] presented a three axis MEMS accelerometer. It uses a switch

capacitor amplifier for detecting the capacitance change. The circuit was characterized at a clock

frequency of 500kHz. The x-axis accelerometer has a sensitivity of 1V/g with a noise floor of

110µg/√

Hz.

In 2001, Edelson et al [124] of Borealis Technical Limited obtained a patent for a

∆Σ modulation based force balanced microphone. The microphone described is of the

electrodynamic type but the patent covers electrostatic devices also. In this patent, the same

plates are used for both sensing and for feedback.

3.7 Summary

In this chapter, the commonly used open and closed-loop interface techniques were

reviewed. Theoretical formulation for the performance metrics of the various techniques were

developed. Tradeoffs for each of the techniques was explained. Requirements of ∆Σ modulation

based interface circuits as device geometry is scaled was then addressed. Chapter 4 and Chapter

5 present a detailed design procedure for the design of the analog and digital closed-loop

controller, respectively.

96

CHAPTER 4DESIGN OF ANALOG INTERFACE CIRCUIT

4.1 Introduction

In this chapter, the design and simulation of an analog closed-loop interface circuit is

presented. This chapter begins with the development of a model for the closed-loop system. This

model is based on the lumped element model of the microphone developed in Chapter 2 and

the model of the synchronous modulator/demodulator developed in Chapter 3. Open and closed

loop time domain simulation of the model for sinusoidal and step input is presented next. This is

followed by the details of the circuit implementation . This includes the design of the interface

circuit components namely the amplifier, demodulator and compensator. This chapter concludes

with a discussion of the limitations of the circuit. A graphical overview of this chapter is shown

in Figure 4-1.

Implementation ofinterface circuitIntroduction

Limitations of theinterface circuitSummaryDesign of interfacecircuitAmplifier designDemodulatordesignCompensatordesign

Simulation Open loopsimulationClosed loopsimulationMatlab model

Figure 4-1. Overview of Chapter 4.

4.2 Simulation

The simulation of the complete system involves the development of a model that accurately

captures the non-linearities of the demodulator and voltage to force transfer function in Simulink.

This model is then simulated for both open-loop and closed-loop mode of operation. A block

diagram of a closed-loop microphone is shown in Figure 4-2. The input to the system is a

97

Sensor(Force todisplacement) InterfacecircuitPressure CompensatorArea Displacementto voltageVoltage toForceElectrostaticforceNetforce+-Inputforce

Figure 4-2. Block diagram of analog closed-loop system showing microphone and interfacecircuit.

time varying pressure signal generated by the acoustic source. The input pressure acting on the

constant area of the microphone diaphragm produces an input force. The net force acting on

the diaphragm is the difference between the input force and the electrostatic feedback force.

The diaphragm displacement is electrostatically transduced as a change in capacitance by

appropriately biasing the microphone plates [37]. Synchronous modulation/demodulation [125]

is used as the interface circuit to detect the capacitance change. The output of the circuit after

compensation provides the feedback voltage. This voltage causes an electrostatic force which

opposes the input force and acts to reduce the diaphragm displacement.

4.2.1 Simulink Model

The second order model of the microphone in the acoustic domain developed in Chapter 2

is used for the microphone model. A linear model for the interface circuit and voltage-to-force

block is developed using the small displacement approximation. Using the lumped element

microphone model, interface circuit model, and voltage-to-force transfer function model, the

compensator is designed.

The microphone is modeled as a second order system given by the equation

Hsensor =1/m

s2 + 2ζ (2πfres) s + (2πfres)2 , (4–1)

developed in Chapter 2.

The interface circuit measures the change in capacitances C1 and C2 induced by the input

pressure acting on the diaphragm. The top and bottom plates of the microphone are excited

by a dc voltage (Vdc) superimposed on a square wave ac carrier (vac) of opposite polarity. The

excitation frequency (ωc) is chosen to be much higher than the resonant frequency of the sensor

98

to prevent the ac signal from exciting the microphone diaphragm. The top and bottom plate

voltage, vtp and vbp, with no feedback is given by

vtp = +Vdc − vac(t) ; vbp = −Vdc + vac(t). (4–2)

Cp represents the parasitic capacitances due to the interconnection between the microphone and

interface circuit, and Ci is the amplifier input capacitance. Rdc is a bias resistor that sets the dc

operating point at 0V . A unity gain amplifier is connected to the middle plate of the microphone.

The output of the unity gain amplifier vmod is given by

vmod =C10 + C20

C10 + C20 + Cp + Ci

x′

x0

vtp, (4–3)

where x0 is the nominal gap distance between the plates of the microphone, x′ is the displacement

of the diaphragm from its equilibrium position, and C10 and C20 are the equilibrium microphone

capacitances. In Equation 4–3, the ratio C10+C20

C10+C20+Cp+Ciis defined as the attenuation factor and is

denoted by Hc. The output of the amplifier is connected to a demodulator which multiplies the

modulated middle plate voltage with a carrier signal (vc(t)) which is in phase with the top plate

voltage. The output of the demodulator, vdemod, is given by the expression

vdemod = vmod × vc(t), (4–4)

and has signals at the base band, carrier frequency, and multiples of the carrier frequency. The

output of the demodulator is low pass filtered and is given by

Vout =x′

x0

Hc

[2

π

Vc

2

2

π

Vac

2

]. (4–5)

Using Equation 4–5, the transfer function of the interface circuit, Hint is given by

Hint =x′

Vout

=Hc

x0

[2

π

Vc

2

2

π

Vac

2

]. (4–6)

The voltage-to-force block models the transduction of the feedback voltage vf to an

electrostatic force acting on the diaphragm. The forces between the top plate and the diaphragm,

Ftp, and between the bottom plate and the diaphragm, Fbp, are given by

Ftp =1

2εA

v2tp

[x0 − x′]2; Fbp =

1

2εA

v2bp

[x0 − x′]2, (4–7)

99

where the top and bottom plate voltages vtp and vbp are expressed in terms of the feedback

voltage vf by the expression

vtp = +Vdc − vac(t) + vf ; vbp = −Vdc + vac(t) + vf . (4–8)

The feedback voltage vf is generated by the compensator. The design of the compensator is

discussed in the next section. The net electrostatic feedback force on the diaphragm Fe is given

by the difference of Ftp and Fbp i.e.,

Fe = Ftp − Fbp. (4–9)

For small displacements (x′ ≈ 0), Fe can be linearized to

Fe = 2εAVdc

x20

vf . (4–10)

Equation 4–10 represents the linearized input-output relation between the feedback voltage and

the force on the microphone diaphragm. Using Equation 4–10, the feedback transfer function,

Hfb is given by

Hfb =Fe

vf

= 2εAVdc

x20

. (4–11)

The function of the compensator is to filter the high frequency modulating signal and

provide appropriate gain and phase so that the resultant closed loop system is stable. The

compensator consists of two stages. The first stage is a high-gain low-pass filter that sets a

dominant pole at low frequency. The second stage consists of a lead-lag section that provides

primarily phase lead to obtain sufficient phase margin. The loop gain of the system without the

compensator, Tnc(s), is given by

Tnc(s) = Hmic ×Hint ×Hfb. (4–12)

From the uncompensated system Bode plot in Figure 4-4, it can be seen that the system has

very low loop gain at dc and a high Q resonant peak due to the complex conjugate poles of

the microphone. To improve the loop gain and provide sufficient phase margin, a two stage

compensator given by the transfer function H(s)

H(s) =

[750

2π · 1 · 103

s + 2π · 1 · 103

] [s + 2π · 230 · 103

s + 2π · 30 · 103

], (4–13)

100

is used. The bode plot of the compensator is shown in Figure 4-3. It can be seen that the

100

102

104

106

108

−100

0

100

200

Mag

nitu

de (

dB)

100

102

104

106

108

−100

0

100

Pha

se (

deg)

Frequency (Hz)

Figure 4-3. Bode plot of compensator.

compensator has a high gain low frequency pole at 1kHz. A high frequency zero at 230kHz is

used to provide phase margin. The loop gain of the system with compensator, T (s), is given by

T (s) =1/m

s2 + 2ζ(2πfres) + (2πfres)2(4–14)

×Hc

x0

(2

π

Vc

2

2

π

Vac

2

)

×2εAVdc

x20

(4–15)

×[750

2π · 1 · 103

s + 2π · 1 · 103

] [s + 2π · 230 · 103

s + 2π · 30 · 103

].

A Bode plot of the compensated loop gain is also shown in Figure 4-4. It can be seen that the

system has a phase margin of 42 and a dc loop gain of 87.

The complete closed loop Simulink model is shown in Figure 4-5. The microphone

and compensator are modeled using a “s-domain” transfer function block which implements

Equation 4–1 and Equation 4–13 respectively. The synchronous modulator/demodulator interface

circuit model and voltage-to-force subsystem model implement Equation 4–4 and Equation 4–9

respectively using multipliers and gain blocks. Thus, a time domain model of the closed loop

system has been developed. Open and closed loop operation for step and sinusoidal inputs were

simulated and is presented next.

101

100

102

104

106

108

−100

−50

0

50

100

Frequency HzM

agni

tude

(dB

)

without compensatorwith compensator

100

102

104

106

108

−300

−200

−100

0

Pha

se (

deg)

Frequency (Hz)

without compensatorwith compensator

Figure 4-4. Bode plot of loop gain with and without compensator.

Input

FeedbackForce

Demodulated Output

Net

Force

Displace−ment Middle Plate

Voltage

displacement

Top_plate_voltage

feedback_voltage

Force

Voltage to Force

Hc/d0

Voltage Buffer Sensitivity

vtp

Top Plate Voltage

PulseGenerator

ProductPressure

1/m

s +2*zeta*wns+wn*wn2

Microphonenumlpf

denlpf

Low Pass FilterA

1Effective Area

X

YZ

Demodulator(AD734)

numcomp

dencomp

Compensator

Kamp

Amplifier

Force

Figure 4-5. Simulink model of analog closed-loop control system.

4.2.2 Simulation Results

In this section, the open and closed loop simulation results of the capacitive microphone are

presented. To demonstrate closed loop operation, a 2Pa (100dB re. 20µPa), 2kHz sinusoidal

pressure input is used as the test signal. From linear control theory [126], during closed loop

operation, the diaphragm displacement at a given frequency will be attenuated by the loop gain

evaluated at that frequency. From the time domain simulation (Figure 4-7), it can be seen that the

output displacement for a 2kHz input is reduced by a factor of 40 which matches the attenuation

in diaphragm displacement predicted by the loop gain (Figure 4-4). To further examine closed

loop operation, a 1m drop test was simulated. The pressure corresponding to a 1m drop acting

on the diaphragm is simulated by a 1ms, 0.029Pa(63dB) pulse. The diaphragm displacement is

102

1

vtp

vdc

vdc

vac

(a) Simulink model oftop plate voltagesubsystem.

1Z

1/Kmul

mutliplier attenuation

multiplier2Y

1X

(b) Simulink model of demodulator.

Bottom Plate Voltage

1

Force

u(1)*u(1)

vol_squared2

u(1)*u(1)

vol_squared1

0.5*e0*A/((d0+u(1))^2)

function2

0.5*e0*A/((d0−u(1))^2)

function1

Product2

Product1

−1

Gain

3

feedback_voltage

2

top_plate_voltage

1

displacement

(c) Simulink model of voltage-to-force subsystem

Figure 4-6. Subsystems used in Simulink model.

attenuated from 6.2pm to 7.1 × 10−2pm during the pulse (Figure 4-8). This matches the dc loop

gain of 87(38dB) obtained from the loop gain Bode plot (Figure 4-4).

4.3 Design of Analog Interface Circuit

The design of the analog closed-loop controller circuit involves the design of the summing

amplifier for top and bottom plate voltage generation, input buffer amplifier, demodulator, low

pass filter, and compensator. The design of each of these circuits is discussed next.

4.3.1 Design of Amplifier for Top and Bottom Plate Voltage Generation

The top and bottom plate voltages are generated using a matched pair of summing amplifier.

The two main requirements of this amplifier are as follows. First, the unity gain bandwidth of

the amplifier must be higher than the modulation frequency. For the aeroacoustic microphone

with a measured resonant frequency of 230kHz, the modulation frequency was chosen to be

one decade above the resonant frequency at 2MHz. Second, the amplifier must accept a dc input

greater than the voltage required for force balancing at the maximum input sound pressure level.

The voltage required for the two microphone structures discussed in Chapter 2 is repeated

in Table 4-1. Based on the table, it can be seen that we need an amplifier operating at a voltage

103

0 0.5 1 1.5 2

x 10−3

−2

0

2

Inpu

t P

ress

ure

(Pa)

0 0.5 1 1.5 2

x 10−3

−0.5

0

0.5

Time (s)

Dia

phra

gm

Dis

plac

emen

t (nm

)

Without feedback

0 0.5 1 1.5 2

x 10−3

−0.5

0

0.5

Time (s)

Dia

phra

gm

Dis

plac

emen

t (nm

)

With feedback

Figure 4-7. Diaphragm displacement with and without feedback.

0 0.5 1 1.5 2 2.5 3

x 10−3

0

0.05

Time (s)

Inpu

t Pre

ssur

e (P

a)

0 0.5 1 1.5 2 2.5 3

x 10−3

−0.01

0

0.01

Time (s)

Dia

phra

gm

Dis

plac

emen

t (nm

)

Without Feedback

0 0.5 1 1.5 2 2.5 3

x 10−3

−0.01

0

0.01

Time (s)

Dia

phra

gm

Dis

plac

emen

t (nm

)

With Feedback

Figure 4-8. Diaphragm displacement with and without feedback.

greater than 45V with a unity gain bandwidth of at least 2MHz. Such amplifiers are not

available commercially. The maximum operating voltage of high bandwidth commercially

available amplifiers is ±15V . An OP275 dual operational amplifier which has two matched

amplifiers with a unity gain bandwidth of 11MHz at an operating voltage of ±15V is used. To

prevent power supply noise from entering the system, the top and bottom plate dc voltages are

provided by batteries regulated using a linear regulator. The maximum pressure that can be force

balanced is approximately 134dB.

The schematic of the summing amplifier circuit that generates the top and bottom plate

voltages is shown in Figure 4-9. In this figure Vdc and −Vdc represent the dc voltages used

104

Table 4-1. Feedback voltage requirements of aeroacoustic and audio microphone for forcebalancing maximum input pressure.

Property Audio microphone Aeroacoustic microphoneMaximum input 120dB(20Pa) 160dB(2000Pa)

Feedback voltage 5V 45V

for force balancing, vac(t) and −vac(t) are the voltages required for synchronous modulation

and demodulation, and vf is the feedback signal generated by the circuit. The ac voltages are

generated by two Agilent 33014 signal generators that are exactly phase shifted by 180 degrees.

The amplitude of the ac signal is 5Vpp. +- RRRRVdc-Vacsin(wt)vf Vtp+- RRRR-VdcVacsin(wt)vf Vbp

Figure 4-9. Schematic of summing amplifier that generates top and bottom plate voltages.

4.3.2 Input Buffer Amplifier Design

The input amplifier is a simple unity gain follower and is shown in Figure 4-10. The

unity gain amplifier was implemented using a low noise, high bandwidth amplifier, TLE2074

[127] configured for unity gain. A quad opamp was chosen so that the four aeroacoustic

microphones on each sensor die could be interfaced using a single chip. This amplifier

operates on a ±15V power supply, has an input capacitance of 10.6pF , an input referred

noise voltage of 11nV/(Hz)12 , and an input referred noise current of 1.6 fA/(Hz)

12 . The

middle plate of the microphone is biased using two surface mount 22MΩ resistors in a

105

1210 (3.2mm× 2.5mm× 0.6mm) package wired in series, i.e,

Rdc = 44MΩ. (4–16)

The total parasitic capacitance at the input node is given by the sum of the PCB trace capacitance

and the input capacitance of the amplifier. The total parasitic capacitance is approximately 20pF .

4.3.3 Demodulator Design

The output of the interface circuit is demodulated by the the Analog Devices AD835 four

quadrant analog multiplier IC [102]. This IC is powered with a ±5 power supply and has a

200MHz full power bandwidth. If the two input signals to the multiplier are X and YRDC -+ VoutFigure 4-10. Schematic of voltage amplifier.

respectively and the output signal is W , then the transfer function of the multiplier is given

by

W =XY

1. (4–17)

A schematic of the demodulator IC is show in Figure 4-11.AD 734 10111267 X1X2Y2Y1 W2W1InputSignalCarrierSignal DemodulatedOutputFigure 4-11. Schematic of analog multiplier (AD835) showing relevant pins.

4.3.4 Compensator Design

The compensator was implemented using two opamps. The schematic of the compensator

for the first stage and second stage is shown in Figure 4-12. The transfer function of the circuit

106

shown in Figure 4-12(a), Hc1, is

Hc1 =Rf1

R11

[1

1 + Rf1Cf1s

], (4–18)

and the transfer function of the schematic shown in Figure 4-12(b), Hc2, is

Hc2 =Rf2

R12

[1 + sR12C12

1 + sRf2Cf2

]. (4–19)

For the transfer function given in Equation 4–18 and Equation 4–19, the component values used

are listed in Table 4-2. The various circuitry used in the closed loop operation are soldered on

two different PCBs. This is discussed in the next section.

Table 4-2. Element values for resistors and capacitors used in compensator.Element Value Element ValueR11 1kΩ C11 680pFRf1 5.1kΩ Cf1 1000pFR12 1kΩRf2 1590kΩ Cf2 100pFR11 +- Cf1Rf1 VoutVin

(a) Schematic of first stage of compensator.R12 +- Cf2Rf2C12 VoutVin(b) Schematic of second stage of

compensator.

Figure 4-12. Schematic of two stage compensator.

107

4.4 Integration of Interface Circuit Components on a PCB

Buffer amplifiersOptical portBreakout headersBias resistorsFigure 4-13. Annotated photograph of PCB1 showing buffer amplifier, breakout headers and

optical port. Summing amplifierfor top and bottomplate voltage Demodulator CompensatorFigure 4-14. Annotated photograph of PCB2.

The complete system consisting of the microphone and interface circuit is characterized

in an acoustic pressure coupler (APC). The details of the APC are provided in Chapter 6. To

facilitate mounting of the microphone in the APC, the circuitry is divided into two separate

printed circuit boards (PCBs). The microphone and buffer amplifier are soldered onto the

microphone PCB (denoted as PCB1) which is mounted onto the APC while the remainder of

the circuitry consisting of the demodulator, compensator, and top and bottom plate voltage

generation circuitry PCB are mounted on another PCB (denoted as PCB2). The two boards

are electrically connected with each other using a ribbon cable. This cable couples the top and

bottom plate voltages generated by the PCB2 to the microphone plates on PCB1. This cable also

108

connects the buffer amplifier output from PCB1 to the PCB2. Figure 4-13 and Figure 4-14 shows

an annotated picture of the PCB1 and PCB2. The headers for the ribbon cable are shown in the

figures.

4.5 Noise model

In this section, the noise model of the interface circuit is developed using the noise

parameters of the components used in the system. The noise floor of the forward path system

is determined by the the buffer amplifier, gain amplifier, demodulator, and compensator and

is shown in Figure 4-16. The total output referred noise of the forward path is determined byvmod-+ MultiplierVref(Demod)vdemodR1 +-RfCc0 R12 +- Cf2Rf2VoutR11 +-Cf1Rf1C11 Cc1BufferAmplifier GainAmplifier CompensatorStage 1 CompensatorStage 2Figure 4-15. Schematic of forward path of the closed loop system

summing the noise at the output of each stage of the forward path with the appropriate gain. This

noise model is valid in the bandwidth of operation of the closed loop system which extends from

300Hz to 20kHz. In the bandwidth of interest, the noise spectrum is determined y the thermal

noise of the various components and is flat over the spectrum. Hence in this analysis, the shaping

of the noise by the various components is not considered.

Noise at the output of the buffer amplifier. The noise PSD at the output of the buffer

amplifier, S1, is determined by the voltage noise PSD of the buffer amplifier, Sva1, and is given

by

S1 = Sva1. (4–20)

Noise at the output of the gain amplifier. The noise PSD at the output of the gain

amplifier, S2, is determined by the output noise PDS of the previous stage, S1, voltage noise PSD

of the input resistor R1, voltage noise PSD of the feedback resistor, Rf , and voltage noise PSD,

Sva2, and current noise PSD, Sia2, of the amplifier and is given by

S2 = S1

(Rf

R1

)2

+ 4kTR1

(Rf

R1

)2

+ 4kTRf + Sva2

(Rf

R1

)2

+ Sia2 (Rf )2 . (4–21)

109

Table 4-3. Magnitude of parameters used in noise analysisParameter Magnitude UnitsVoltage noise of inputamplifier (Sva1)

18 nV/√

Hz

Voltage noise of gainamplifier (Sva2)

3.8 nV/√

Hz

Current noise of gainamplifier (Sia2)

0.6 pA/√

Hz

Voltage noise of multiplier(Smultiplier)

50 nV/√

Hz

Voltage noise of compensatorfirst stage amplifier (Sva3)

7 nV/√

Hz

Current noise of compensatorfirst stage amplifier (Sia3)

1.5 pA/√

Hz

Voltage noise of compensatorsecond stage amplifier (Sva4)

7 nV/√

Hz

Current noise of compensatorsecond stage amplifier (Sia4)

1.5 pA/√

Hz

Input resistance of gainamplifier (R1)

1 kΩ

Feedback resistance of gainamplifier (Rf )

4 kΩ

Input resistance ofcompensator first stageamplifier (R11)

1 kΩ

Feedback resistance ofcompensator first stageamplifier (Rf1)

5.5 kΩ

Input resistance ofcompensator second stageamplifier (R12)

1 kΩ

Feedback resistance ofcompensator second stageamplifier (Rf2)

1590 kΩ

Sfwdpath 1 mV√

Hz

SOL 5 uV√

Hz

Noise at the output of the multiplier. The noise PSD at the output of the multiplier, S3, is

determined by the output noise PSD of the previous stage, S2, the internal voltage noise PSD of

the multiplier, Smultiplier, and the demodulator voltage Vref ,and is given by

S3 = S2 × (Vref )2 + Smultiplier. (4–22)

110

Noise at the output of the first stage of compensator. The noise PSD at the output of

the compensator first stage, S4, is determined by the output voltage noise PSD from the previous

stage, S3, voltage noise PSD of the input resistor R11, voltage noise PSD of the feedback resistor

Rf1, and voltage noise PSD Sva3 and current noise PSD Sia3 of the amplifier and is given by

S4 = S3

(Rf1

R11

)2

+ Sva3

(Rf1

R11

)2

+ 4kTR11

(Rf1

R11

)2

+ 4kTRf1 + Sva3

(Rf1

R11

)2

+ Sia3 (Rf1)2 .

(4–23)

Noise at the output of the second stage of compensator. The voltage noise PSD at the

output of the compensator second stage, S5, is determined by the voltage noise PSD from the

output of the previous stage, S4, voltage noise PSD of the input resistor R12 amplifier, voltage

noise PSD of the feedback resistor Rf2, and voltage noise PSD Sv43 and current noise PSD Sia4

of the amplifier and is given by

S5 = S4

(Rf2

R12

)2

+ Sva4

(Rf2

R12

)2

+ 4kTR12

(Rf2

R12

)2

+ 4kTRf2 + Sva4

(Rf2

R12

)2

+ Sia4 (Rf2)2 .

(4–24)

Theoretical noise floor. The magnitude of the various components in the above equation

listed in Table 4-3. Substituting the values in the Equation 4–24 we obtain

102

103

104

105

10−3

10−2

10−1

100

101

Frequency

rms

nois

e vo

ltage

(m

V)

Forward path noiseOpen loop noise

Figure 4-16. Plot of theoretical noise floor of the open loop system and forward path system

111

SOL = S3 = 5uV/√

(Hz) (4–25)

and

Sfwdpath = S5 = 1mV/√

(Hz) (4–26)

Thus, the noise at the output of forward path of the demodulator is high due to the components

that are required to generate the large gain in the forward path. It can be seen that the forward

path noise is very high. The reason for the high noise floor is the need for large gain in the

forward path to achieve a large loop gain. One solution to reduce the noise and still maintain the

large gain would be to use amplifiers with lower noise. In this work, all the ICs utilize the same

±15V power supply whereas lower noise ICs usually are single ended and operate at 3.3V and

1.8V . Hence, to use these lower noise components, multiple power supply rails are required.

Also, as the ICs are single ended, appropriate level shifting needs to be performed to obtain

stable operation.

4.6 Limitations of the Current Implementation of the Interface Circuit

In this section, the two main limitations of the interface circuit designed in this chapter

are reiterated. The interface circuit was designed to meet the dynamic range and bandwidth

specifications of an aeroacoustic microphone of 60dB − 160dB and a bandwidth in excess of

160kHz.

The voltage required to force balance the maximum input pressure of 160dB as shown in

Table 4-1 is 45V . This cannot be met due to power supply limitations of ±15 for the commercial

off the shelf operational amplifiers that are used in the design. The bandwidth of the overall

system is determined by the compensator. The compensator design was limited to an overall

bandwidth of only 20kHz because of the gain bandwidth constraints of the amplifiers used.

4.7 Summary

In this chapter the design, simulation and implementation details of the analog interface

circuit was presented. Some of the limitations of the current design was discussed. The

characterization results of the complete system is presented in Chapter 6. Chapter 5 discusses the

design and simulation of the digital closed-loop interface circuit

112

CHAPTER 5DESIGN OF DIGITAL CLOSED LOOP INTERFACE CIRCUIT

5.1 Introduction

In this chapter, the design procedure for a ∆Σ modulation based interface circuitry is

presented. This chapter begins with a top down design methodology for determining system

level ∆Σ interface circuit parameters starting from microphone system specification. This is

followed by the design of the interface circuit components, namely the amplifier, compensator

and comparator. Closed loop time domain simulation of the model using the Simulink tool in

MATLAB is presented next. A graphical overview of this chapter is shown in Figure 5-1.

SummarySimulationComponent designDesign procedureAmplifier designCompensatordesignComparator design Matlab modelClosed loopsimulationIntroduction

Figure 5-1. Overview of Chapter 5.

5.2 Design of ∆Σ Interface Circuit

In this section, the design of the complete ∆Σ interface circuit is discussed. The design

procedure for the key parameters of each of the blocks of the ∆Σ modulator from overall system

level specification is also explained. The transistor level design of each of the components is

presented in Section 5.3. The sequence of operation of the various blocks and the overall system

level timing is explained in Section 5.4. Section 5.5 describes the system level simulation of the

microphone and ∆Σ system using Matlab.

113

The system level block diagram of the ∆Σ modulator is repeated in Figure 5-3. The design

of the interface circuitry involves the design of the components inside the box labeled “electrical

domain”. The ∆Σ modulator based interface technique is a sampled data system. Hence, all the

blocks need a clock signal for their operation. Therefore, the first step in the design procedure

of the interface circuit is to determine the sampling frequency fs. The sampling frequency is a

function of the resonant frequency of the mechanical system and the dynamic range specification

of the overall system. This is illustrated in Figure 5-2. The blocks in ellipsoidal boxes represent

the system level input specification and rectangular boxes represent the assumptions used for the

design and the parameters derived from the design procedure. The dynamic range is determined

SamplingfrequencySettling time(Closed loop BW)

Percentage of timefor sense/feedback+

BandwidthDynamic RangeEffective feedbackvoltage

+Noiseconsideration+Amplifier gmand W/LCompensatordesign

Figure 5-2. Flow chart for design of ∆Σ modulator component parameters from system levelspecification.

by the noise sources in the system. The main sources of noise are the sampled thermal noise of

the amplifier, kT/C noise of the switches, and quantization noise. For an ideal ∆Σ modulator,

the noise floor is dominated by the quantization noise. The sampled thermal noise and kT/C

noise is assumed to be below the quantization noise floor. Assuming that the noise floor is

dominated by the quantization noise, the dynamic range DR, in dB, of a one-bit second order

∆Σ modulator can be expressed in terms of the oversampling ratio M(= fs/2fres) by the

relation [79]

DR = −7 + 50log10(M). (5–1)

114

Using the above relation, the sampling frequency of the system is determined.Sensor+-InputPressure Area 2-z-1CompensatorComparator DigitalBitstreamx/C D/AAmpMechanicalDomain ElectricalDomainV/FFigure 5-3. Schematic of second order mechanical ∆Σ modulator.

Once the sampling frequency is determined, the next step is the partitioning of the time

available during one clock cycle T (= 1/fs) into the sense and feedback phase. To maximize

the dynamic range and bandwidth, the time spent in the sense phase must be minimized and the

time spent in the feedback phase must be maximized. The time spent in feedback is determined

by the maximum pressure that must be force balanced and the maximum voltage Vmax available

in the system. The voltage required to force balance the maximum input pressure Pmax can be

expressed in terms of the nominal capacitance C0, the capacitance area A, and the nominal gap

distance of the capacitor x0 by the expression

Vfb,max '√

2PmaxAx0

C0

. (5–2)

This voltage must be available during the fraction of time τfb spent in feedback. If the maximum

voltage available in the system is Vmax, then

τfb

T=

Vfb,max

Vmax

. (5–3)

Using the above relation, the time spent in feedback can be determined. Then, the time spent in

sense τsense is given by

τsense = T − τfb. (5–4)

Next, we consider the partitioning of the time spent in the sense phase. The time spent during

sense τsense is determined by the settling time requirements of the amplifier τamp, compensator

115

τcompen, and comparator τcompar and is related by the expression

τsense = τamp + τcompen + τcompar. (5–5)

The individual blocks must to satisfy two conflicting criteria, namely high speed (settling time

requirements) and low noise. To achieve this, the circuit is first designed for low noise and

then tested for settling time requirements. If the low noise design does not satisfy the speed

requirements, the circuit design is reiterated by changing the gain capacitor to meet the settling

time requirements, and the noise performance is reevaluated. Theoretical formulation for the

noise and settling time for each of the components are described in Section 5.3.

Once the individual components are designed, the sequence of operation of the individual

parts of the sense and feedback phase is designed. This is explained in Section 5.4. For this

work, the timing signals are generated off chip using a Alter EPM7128 [128] complex

programmable logic device (CPLD). This allows one to have better control of the sense and

feedback phase during the initial testing phase. Based on this information the system level

simulations (Subsection 5.4) are performed.

5.3 Component Design

In this section, the transistor level design of the amplifier, compensator, and comparator

is explained. For each component, the procedure to design the component with low noise is

described. A theoretical formulation for the noise and the settling time is also developed.

5.3.1 Switched Capacitor Amplifier

The design of the switched capacitor amplifier involves the design of the amplifier core so as

to reduce the thermal noise. A folded cascode topology with a PMOS input stage was chosen so

as to reduce the noise of the input amplifiers and improve the output voltage swing. The switches

are arranged such that the output common mode is centered around 2.5V while the input is at

ground. Centering the output voltage at the midpoint of the power supply rails allows one to

maximize the output dynamic range of the amplifier. Similarly, setting the input common mode

voltage of the amplifier at ground maximizes the voltage that can be applied across the top and

bottom capacitors during the sense and feedback phase. An input common mode voltage of zero

(ground) is within the common mode voltage range of the PMOS input folded cascode amplifier.

116

The schematic of the amplifier core and the switched capacitor amplifier is shown in Figure 5-11.

CresetV+ -+Cgain0 V0 V

(a) Switched capacitor amplifier.

VcpVcnV+V- VoutM1 M2M11M3 M6M5 M8M7

M10M9 M4VbnVbp

(b) Amplifier core.

Figure 5-4. Transistor level schematic of amplifier.

The design of the amplifier closely follows the work by Wongkomet [108]. The following

assumptions are made:

• The amplifier core is a simple single stage amplifier that can be treated as single pole

system which is common in switched capacitor circuits.

• The gain capacitor Cgain is arbitrarily chosen to provide a closed-loop gain of 10 − 20dB.

This value may be changed to optimize the noise performance.

• The total parasitic capacitance at the input node is fixed and can be estimated.

• The amplifier closed-loop bandwidth is designed to be at the minimum value required

based on the settling time constraints. This prevents excess noise from aliasing into the

baseband.

The amplifier schematic during the amplify phase used for the rest of the analysis is shown

in Figure 5-5. The thermal noise of the amplifier can be expressed in terms of the amplifier

transconductance gm and the ratio of the total transistor noise to the input transistor noise nf by

the expression[79]

Svn = 4kT2

3gm

nf . (5–6)

117

Creset-+Cgain0 V0 VC0 CLCp,ampCp,extC0 CLTFigure 5-5. Schematic of amplifier during amplify phase.

For a well designed amplifier, only the input transistors contribute noise, and nf is equal to two.

In practice it can be greater. From the discussion in the previous chapter, the total output thermal

noise of the amplifier is

Svopamp =

[CT

Cgain

]2

Svnfu

fs

π

2. (5–7)

In the above equation, CT is given by

CT = 2C0 + Cp + Cgain. (5–8)

The parasitic capacitance, Cp, can be split into the input capacitance of the amplifier, Cp,amp and

other external parasitics Cp,ext. Therefore, CT can be expressed as

CT = 2C0 + Cp,amp + Cp,ext + Cgain. (5–9)

For any transistor, the transconductance gm, can be expressed in terms of the input capacitance

Cp,amp, and the unity gain frequency, fT , as

gm = 2πfT Cp,amp. (5–10)

Substituting, Equation 5–6 and Equation 5–9 in Equation 5–7, we obtain

Svopamp =

[2C0 + Cp,amp + Cp,ext + Cgain

Cgain

]28kT

3

1

2πfT Cp,amp

fu

fs

π

2. (5–11)

118

This equation is optimized for noise by varying the input capacitance of the amplifier.

Differentiating the above equation with respect to Cp,amp and equating to zero we obtain

Cp,amp = 2C0 + Cp,ext + Cgain. (5–12)

From the previous equation, it can be inferred that to minimize the noise of the amplifier,

the input capacitance must be equal to the total capacitance at the amplifier summing node.

Substituting Equation 5–12 in Equation 5–10, gm can be designed. From the transconductance,

the W/L of the transistors of the amplifier can be calculated.

Once the transconductance is designed, the load capacitor is designed to meet the bandwidth

requirement. As discussed in the previous chapter, the closed-loop bandwidth of the switched

capacitor amplifier is given by

fu =1

2π

[m

nτfs

]−1

. (5–13)

The closed-loop bandwidth fu is related to the open-loop bandwidth famp by the feedback factor

β,

β =CT

Cgain + CT

, (5–14)

and the open-loop gain,

famp =1

2π

gm

CLT

, (5–15)

by the expression

fu = βfamp. (5–16)

The total load capacitance CLT , is given by the expression

CLT = CL + Creset + Cgain|| [2C0+Cp,amp + Cp,ext] (5–17)

Substituting Equation 5–16 in Equation 5–15, we obtain

fu =1

2π

gm

CLT

(5–18)

=1

2π

gmβ

CL + Creset +Cgain[2C0+Cp,amp+Cp,ext]

Cgain+2C0+Cp,amp+Cp,ext

.

119

Rearranging the above equation, we obtain

CL =Cgain

2C0 + Cgain + Cp,amp + Cp,ext

[gm

2πfu

− (2C0 + Cgain + Cp,amp + Cp,ext)

]− Creset.

(5–19)

Substituting for Cp,amp from Equation 5–12 and fu from Equation 5–13 into the previous

equation, we obtain

CL =Cgain

2

[fT

12π

nτ fs

m

− 1

]− Creset. (5–20)

This can be simplified to

CL ' πmCgainfT

nτfs

− Creset. (5–21)

This is the load capacitance required to satisfy the low noise requirements and settling time

constraints. If the actual load capacitance which is formed by the compensator is larger, then a

larger integrating capacitor can be used and the procedure is reiterated. Thus, the amplifier has

been designed to meet the settling time constraints and minimize noise.

5.3.2 Compensator Design

The function of the compensator is to provide feedback to stabilize the second order

feedback loop. One of the proposed solutions in the literature [119] for compensating a ∆Σ

modulation based capacitive sensor is to use a two tap discrete time finite impulse response

(FIR) filter. The filter transfer function can be expressed in terms of a design parameter α by the

general z-domain transfer function,

K(z) =α− z−1

α + 1. (5–22)

The design parameter α is designed so as to reduce the total system noise and provide stable

compensation. For the initial design, α was chosen to be 2 using [119] and verified via simulation

and not via analytical methods. The settling time of the compensator is determined by the RC

time constant of the compensator capacitance and the on-resistance of the switches.

The actual transistor level implementation of the compensator is shown in Figure 5-6. The

circuit consists of only switches and capacitors, and the transfer function is determined by the

principle of charge sharing. Since this circuit does not have any amplifiers, the settling time is

considerably reduced. It consists of three capacitors C1, C2, and C3 connected to switches that

120

are driven by the clock signals generated from the Sampl, Eval, and Chop signals. Capacitor C1

always holds the current information while capacitors C2 and C3 hold the information from the

previous clock cycle alternatively. The Chop signal which runs at a clock frequency equal to half

the system frequency is used to alternate between C2 and C3 for storing the information from the

previous cycle. The compensator has two phases of operation namely, Sample and EvaluationVinSampl*Chop Sampl*ChopEval*ChopSampl EvalC1C2 Vout- -++ -- Eval*ChopC3++ --

++Sampl*ChopSampl*Chop

VcmVcm VcmVcm VcmEval*Chop Eval*Chop

EvalChopSamplFigure 5-6. Transistor level schematic of compensator.

phase. During the Sample phase, the output of the amplifier is sampled on to capacitors C1 and

one of the two capacitors C2 and C3 as determined by the chop signal. The derivation of the

transfer function of the circuit is done by analyzing the two half cycles of this circuit as shown in

Figure 5-7. Figure 5-7(a) shows the case when capacitor C1 and C3 are being charged with the

information from the current cycle while C2 holds the amplifier output from the previous cycle.

The charge on the three capacitors during the sampling phase at some instant of time k is given

by

Q1 = C1 [Vin(k)− Vcm] , (5–23)

Q2 = C2 [Vin(k − 1)− Vcm] , (5–24)

121

and

Q3 = C3 [Vin(k)− Vcm] . (5–25)VinSampl*Chop Sampl*ChopEval*ChopSampl EvalC1C2 Vout- -++ -- Eval*ChopC3++ --

++Sampl*ChopSampl*Chop

VcmVcm VcmVcm VcmEval*Chop Eval*Chop

(a) Sample phase.

VinSampl*Chop Sampl*ChopEval*ChopSampl EvalC1C2 Vout- -++ -- Eval*ChopC3++ --

++Sampl*ChopSampl*Chop

VcmVcm VcmVcm VcmEval*Chop Eval*Chop

(b) Evaluation phase.

Figure 5-7. Compensator schematic during the two phases of operation.

During the Evaluation phase of the same cycle, shown in Figure 5-7(b), the plates of

capacitor C2 are reversed and connected to the output. Applying charge conservation, we equate

the final charge on the capacitors connected to the output node to their respective initial charges.

This can be expressed as

(C1 + C2) [Vout(k)− Vcm] = C1 [Vin(k)− Vcm]− C2 [Vin(k − 1)− Vcm] . (5–26)

Taking the z-transform of the previous equation and rearranging the terms, we obtain,

Vout(k) =C1 − C2z

−1

C1 + C2

Vin(k)− C1

C1 + C2

Vcm. (5–27)

From Equation 5–27, it can be seen that the transfer function of the compensator has a DC

offset. When this compensator is used in closed-loop, this offset will cause the center plate to

be displaced from the center position. This does not affect the operation of the circuit or its

performance metrics. Neglecting the offset, Equation 5–27 can be simplified as

Vout(k) =C2

C1 + C2

[C1

C2

− z−1

]Vin(k). (5–28)

122

The compensator is followed by the comparator. Therefore, the term C2

C1+C2is not important.

Comparing Equation 5–28 with Equation 5–22, we obtain

α =C1

C2

. (5–29)

5.3.3 Comparator Design

The comparator used in the ∆Σ modulator consists of a open-loop amplifier followed

by a positive feedback stage. The net feedback of the comparator is determined by the Latch

signal. The comparator has two phases of operation namely “Track” and “Latch”. During the

track phase (Latch = 0), the negative feedback in the comparator is greater than the positive

feedback, and the comparator functions as an open-loop amplifier. During the latch phase

(Latch = 1), the positive feedback is greater than the negative feedback, and the comparator

output goes high or low corresponding to whether the the input signal is greater or less than the

reference voltage. In this system, the reference voltage is 2.5V . The schematic of the comparator

is shown in Figure 5-8. The latch mode time constant is given in terms of the load capacitance

Vbn LatchM1 M2 Vout+Vout-V+V-M3 M4M5 M6M7 M11M8M8 M9 M10

Figure 5-8. Transistor level schematic of comparator

CL, transconductance gm, change in input signal ∆V0, and the change in the output logic signal

∆Vlogic by the equation [79]

τcompar =CL

gm

ln∆V0

∆Vlogic

(5–30)

123

The time constant of the comparator stage is much lower than the amplifier and compensator

stages and can be neglected.

5.3.4 Bias Network Design

The currents and voltages required to set the operating points of the amplifier, comparator,

and compensator is generated via the on-chip bias generation network shown in Figure 5-11.

This network designs the bias voltages (Vbn, Vcn, Vbp, Vcp) and the bias currents.VbpVcpVbn VcnM1 M4M2 M3

M8 M7M9 M6 M11M10 M13M12M14 M18

M17M15 M16M5RbFigure 5-9. Schematic of bias network.

5.4 System Level Timing

In the previous section, the various building blocks of the ∆Σ interface technique was

explained. For the proper operation of the circuit, the various building blocks must operate in a

correct sequence. This section describes the sequence of operation of the various blocks and the

timing consideration required for the sequencing. The various time intervals discussed in this

section are related to the settling times discussed in Section 5.3.

The overall sequence of operation of the microphone system is shown in Figure 5-10.

The clock signals involved in each phase of operation are shown inside the block. The various

components of the ∆Σ modulator, namely switched capacitor amplifier, compensator, and

comparator have two phases of operation. The two phases of operation of the amplifier are the

124

reset phase and the amplify phase and is controlled by clocks φ1 and φ2 respectively. The two

phases of operation of the compensator are sample and evaluate and is controlled by three clock

signals namely Sampl, Eval, and Chop. The two phases of operation of the comparator are

track and latch and is controlled by one clock signal, namely Latch. The various phases of the

building blocks of the ∆Σ modulator and the clock signals used to control them are listed in

Table 5-1. The complete interface circuit is shown in Figure 5-11.

Table 5-1. Clock signals used in the various components of the ∆Σ modulator.

Component Phases ClockAmplifier Reset, Amplify φ1, φ2

Compensator Sample, Eval Sampl, Eval, Eval

Comparator Track, Latch Latch

Sense(Reset, Amplify)Compensate(Sampl, Eval, Chop)Compare(Track, Latch)Feedback(TP, BP)Digital Output

InputPressure

Figure 5-10. Flowchart showing the sequence of operation of the overall ∆Σ modulation basedinterface circuit.

The timing diagram begins at the reset phase of the amplifier during the sensing operation.

At instant denoted by 1, the reset phase ends and the amplifier is prepared to enter the amplify

phase. The time from 1 to 2 is the non overlap period of the switched capacitor amplifier. At the

instant 2, the amplifier comes into the amplify phase. The time from 2 to 3 is the time required

for the amplifier to settle before starting a new measurement. At instant 3, the top (TP ) and

125

bottom (BP ) plates voltages make a step equal in magnitude but opposite in sign to perform

the measurement. During this period, the Sampl clock is high and the compensator is in the

Sampling phase. The sampling capacitors form the load capacitance of the amplifier. The time

from 1 to 4 is the time required for the amplifier to settle, τamp, discussed earlier.

Once the amplifier has settled and the output of the amplifier has been sampled on to the

compensator capacitors, the compensator enters the evaluation mode. The period from 4 to 5 is

the non-overlap time for this to occur. Once the amplifier enters the evaluation mode, it takes

some time to settle and this is the time from 5 to 6. This is the settling period of the compensator

and is denoted by τcompen. Once the comparator settles, the comparator needs to make a decision.

At instant 6, the comparator goes from the track mode to the latch mode. The output of the

comparator goes high or low depending on the compensator input as compared to the reference

voltage. Based on the output of the comparator, an external circuitry changes the top and bottom

plate voltages to null the diaphragm deflection.Creset Vcm-+Cgain0 V0 V

Sampl*Chop Sampl*ChopSampl*EvalSampl*Eval Sampl*ChopEval*ChopSampl EvalC1C2- -++ --

Sampl*Chop Eval*ChopC3++ --++

VcmV+ Vout+-LatchSwitched CapacitorAmplifier Compensator Comparator

VcmVcm VcmVcm VcmFigure 5-11. Schematic of ∆Σ modulator circuit.

The time period from 6 to 8 is the latch mode time constant, τcompar. The period from 6 to

7 is the non overlap period during which the amplifier goes to the reset phase and prepares for

another measurement. Finally, the time from the end of the feedback phase to the time instant 1

is adjusted so that the top and bottom plate voltages during the sense phase is spent equally high

and low. The function performed by the system during the various time intervals are given in

Table 5.4.

126

Figure 5-12. System level timing diagram over one complete cycle.

Table 5-2. Function performed during each time interval.Time Interval FunctionT01 Time for equalizationT12 Non-overlap time of amplifierT23 Amplifier settling before measurementT34 Amplifier settling timeT45 Non overlap time of compensatorT56 Settling time of compensatorT67 Non-overlap time of amplifierT78 Latching time of comparator

5.5 System Level Simulation

The system level simulation of the closed-loop system was carried out using the Simulink

tool in Matlab 7.0. Figure 5-13 shows the Simulink model of the microphone system. The

microphone was modelled using a “s-domain transfer function” block with a second order

transfer function given by

H(s) =1/Md

s2 + 2ζ(2πfn)s + (2πfn)2. (5–31)

The input to the microphone system block is the “summing” block which computes the

difference between the force corresponding to the input pressure signal modeled using a “signal

127

Feedback Force

Displacement Output

Zero-OrderHold

netforce

fbforceb

disp

fbforce

input

fbforcet

pdm

Switch

SignalGenerator

6e9

den(s)

Microphone

Manual Switch

-1

Gain

1-0.5z -1

1

Compensator

Band-LimitedWhite Noise

1-bitquantizer

f(u)

0.5*8.854e-12*(pi*(230e-6)^2)*(D*5)^2/(2e-6-u(1))^2

Figure 5-13. Simulink Model of the ∆Σ modulator based interface circuit.

generator” block and the electrostatic feedback force. This error signal forms the input to the

microphone which is represented by a “s-domain transfer function” block. The output of the

microphone block is inputted to the compensator which is modeled using the “z-domain transfer

function” block. The comparator is modeled as a “zero order hold” and “one-bit quantizer”

block. The magnitude of the feedback force is computed using the “equation” block whose inputs

are the current displacement and a predetermined feedback voltage . The sign of the force is

determined by a “2 to 1 multiplexer” block which is driven by the output of the comparator. The

output of the multiplexer forms the electrostatic feedback signal. The simulation parameters

are as listed in Table 5.5. Preliminary simulation results of the voice grade microphone are

Table 5-3. Parameters used in closed loop simulation.Parameter MagnitudeResonant Frequency fres 30 kHzDamping Coefficient ζ 0.15Sampling Frequency fs 2.56MhzInput frequency 5kHzOversampling Ratio M 256Solver Type Fixed point (ODE45)Step Size 1/fs

Length of FFT 5120Frequency Resolution 500Hz

presented here. The voice grade microphone was excited with a 5kHz size wave pressure source

with an amplitude corresponding to 2000Pa. The power spectral density of the output signal ∆Σ

modulated bitstream is shown in Figure 5-14. From Figure 5-14, it can be seen that the output

128

bitstream has a signal spike at the input frequency of 5kHz. At higher frequencies, the rising

noise shape of the output bitstream can be seen.

102

104

106

108

10-8

10-6

10-4

10-2

100

Frequency

Pow

er S

pect

ral D

ensi

ty o

f Sig

ma

Del

ta M

odul

ated

Sig

nal

Figure 5-14. Power spectral density of output ∆Σ modulated bitstream.

5.6 Circuit Implementation

Circuit requirements for the implementation of ∆Σ modulation based controller, as a

function of resonant frequency and dynamic range, presented in Chapter 3 is repeated below in

Table 5-4 and Table 5-5 respectively.

Table 5-4. Frequency requirements of ∆Σ interface circuits with increasing resonant frequency.Property Accelerometer Audio microphone Aeroacoustic

microphonefres 1kHz[8] 20kHz 200kHzfs 1MHz[8] 20MHz 200MHzfu 4.5MHz 90MHz 900Mhz

Table 5-5. Feedback voltage requirements of ∆Σ interface circuits with increasing dynamicrange.

Property Audio microphone Aeroacoustic microphoneMaximum input 120dB 160dB

Feedback voltage 6V 45V

From Table 5-4 and Table 5-5 it can be seen that to implement a digital closed loop

controller for an aeroacoustic microphone the process technology must support voltages in excess

129

of 45V with a gain bandwidth of 900MHz. This is not feasible with current IC technology.

Hence, in this work, only a closed loop analog controller was implemented.

5.7 Summary

In this chapter, a design procedure for the development of a ∆Σ modulator for a capacitive

microphone based on the system level specification was developed. A system level simulation

was performed to verify the functionality of the approach. The requirements of the IC fabrication

technology to implement the controller was discussed. Based on this discussion, it was concluded

that a digital closed loop controller was not feasible with current process technology.

In the next chapter, the experimental setup and experimental results to characterize an

analog closed loop controller are presented.

130

CHAPTER 6EXPERIMENTAL SETUP AND RESULTS

6.1 Introduction

In this chapter, the experimental setup and experimental results for characterizing the

capacitive microphone using an analog controller is presented. The chapter begins with a

literature review of test apparatus that can perform simultaneous acoustic, electrical and optical

measurement. This is followed by the design and characterization of the acoustic pressure

coupler. Experimental results of open loop and closed loop measurements of the microphone

are presented next. The experimental results are compared to simulation results. The simulation

results presented include modeling of circuit phenomena such as saturation of amplifiers and

thermal noise. This chapter concludes with a summary of the various results. A graphical

overview of this chapter is provided in Figure 6-1.

SummaryExperimentalresultsExperimental setupIntroductionPressure coupler Pressure couplercharacterizationOpen loopcharacterizationClosed loopcharacterization

Literature reviewDesignFigure 6-1. Overview of Chapter 6.

6.2 Acoustic Pressure Coupler

The acoustic characterization of the microphone involves performing experiments to

determine the sensitivity, dynamic range, noise floor, and frequency response of the microphone.

As part of the characterization, the performance of the microphone with and without a feedback

131

controller is evaluated. To study the effect of feedback, a test setup that allows measurement of

the electrical output of the microphone and the input acoustic signal is required.

6.2.1 Design of Acoustic Pressure Coupler

The pressure coupler consists of a rigid-walled duct with a square cross section (8.5mm ×8.5mm). On one end, a BMS4590P compression driver is used to excite the duct using a Techron

7450 power amplifier controlled by the PULSE multi-analyzer system. A cut away section of the

pressure coupler is shown in Figure 6-2.Inlet for helium Rectangular duct Plug for referencemicrophone(a) Photograph of cutaway section of pressure coupler showing

rectangular duct with 8.5mm square cross section.Optical portPlug for referencemicrophone Inlet for heliumPCB

(b) Photograph of assembled pressure coupler showing PCB,plug for reference microphone and optical port.

Figure 6-2. Photograph of acoustic pressure coupler.

On the opposite face of the duct, a Bruel and Kjaer Type 4138 microphone is mounted at

normal incidence to the acoustic waves and serves as the reference microphone. The device

under test (DUT) is mounted at grazing incidence to the acoustic waves close to the reference

microphone. The distance between the DUT and reference microphone d is 2.4mm. This

132

determines the bandwidth over which the pressure coupler can be used. The frequency f at

which the pressure seen by the DUT and reference microphone are 90 degrees out of phase is

related to the velocity of sound in air c by

f =d/4

c. (6–1)

An inlet and exit port is machined in the duct to allow the chamber to be filled with helium.

Up to the maximum frequency of operation, the DUT and the reference microphone are

exposed to the same pressure. This is ensured by making the distance from the DUT and the

reference microphone less than a quarter wavelength at the maximum frequency of operation.

Also to ensure that the higher order modes are sufficiently attenuated at the end of the test

section, the cross section dimensions are established such that the cut on frequency is higher

than the maximum frequency of interest. To increase the operating frequency range, the duct is

filled with helium as the isentropic speed of sound in helium is 2.7 times as that in air. Since the

distance between the DUT and the reference microphone is fixed, this will increase the maximum

frequency by approximately 2.7X . The minimum frequency of operation of the pressure coupler

is 300Hz and is determined by the speaker. The maximum frequency of operation of the pressure

coupler filled with helium is 18.3kHz and is determined by the duct dimensions. Without

helium, the pressure coupler can be operated up to a frequency of 6.7kHz.

6.3 Experimental Results

6.3.1 Characterization of Pressure Coupler

The pressure coupler was characterized by mounting a Bruel and KjærType 4138

microphone at the location where the DUT is to be mounted. The pressure coupler was excited

with a periodic random bandlimited white noise signal from 100Hz to 25.6kHz with 4 periods

using the PULSE system. Since the speaker has a built in bandpass filter with a low frequency

cut in of 300Hz, all the data plotted is shown from 300Hz. The spectrum of the microphone

output was measured using an FFT analyzer with 800 lines. A plot of the input pressure signal as

a function of frequency is shown in Figure 6-3.

The frequency response between the reference microphone and the second Bruel and

Kjaer Type 4138 microphone is shown in Figure 6-4 with air and helium as the medium in the

133

duct respectively. It can be seen that magnitude and phase frequency response between the

microphones is flat within 3dB from 300Hz to 5.6kHz in air and from 300Hz to 14.2kHz in

helium respectively. The frequency response shows that the two microphones are exposed to the

same acoustic field. Furthermore, it can be seen that the bandwidth of the system with helium is

approximately 2.7 times as that of the system with air.

102

103

104

105

110

115

120

125

130

135

140

Pre

ssur

e (d

B)

Frequency

Figure 6-3. Plot of input pressure signal as a function of frequency.

The roll-off of the magnitude frequency response plot is because of the relative position of

the reference microphone and DUT. In the acoustic pressure coupler, the reference microphone

is placed at normal incidence to the acoustic source and the DUT is placed at grazing incidence

to the acoustic source. At low frequencies (large wavelength), both the reference microphone

and the DUT are subjected to the same acoustic pressure amplitude. With increasing frequency

(smaller wavelength), the pressure amplitude on the reference microphone remains constant

whereas the pressure amplitude on the DUT keeps on decreasing and reaches a minimum based

on the duct dimension and then increases. In the open and closed loop frequency response plots

shown later in this chapter, this effect has been mitigated by multiplying the magnitude frequency

response between the DUT and the reference microphone by the inverse of the magnitude

frequency response shown in Figure 6-4.

Once the pressure coupler was characterized, open loop and closed loop characterization

of the microphone are performed. Figure 6-5 shows a block diagram of the characterization

134

102

103

104

105

0

0.5

1

1.5

2

2.5

Frequency (Hz)

Gai

n (V

/V)

AirHelium

102

103

104

105

−100

0

100

200

300

Frequency (Hz)

Pha

se (

Deg

rees

)

AirHelium

Figure 6-4. Comparison of frequency response of pressure coupler with air as medium and withhelium as medium.

procedure used. The first experiment performed on the microphone is to obtain the frequencyOpen loopcharacterizationFrequency responsewith dc biasClosed loopcharacterizationCompensatorcharacterization

Figure 6-5. Block diagram describing characterization procedure used.

response of the microphone with only a dc bias and a unity gain follower. This experiment is

performed to characterize the microphone and ensure that a working microphone is available

for further tests. The next set of experiments consists of characterizing the microphone with

a dc and ac bias. A synchronous modulation/demodulation interface circuit is used in these

experiments. These experiments provide the frequency response, linearity and noise floor of the

microphone in open loop configuration. To facilitate stable closed loop operation, a compensator

is required. The compensator, independent of the rest of the system, is characterized next. This is

135

accomplished by exciting the compensator with a swept sine signal and measuring the frequency

response. Finally, the closed loop configuration is characterized. The closed frequency response,

linearity, and noise floor is measured. The results of the experiments described are presented

next.

6.3.2 Open Loop Frequency Response of Microphone with Voltage Amplifier (dc bias)

The first test performed on the microphone is to obtain the frequency response of the

microphone with only a dc bias and a unity gain follower. For this test, the PCB consisting of

the microphone and buffer amplifier, is mounted in the acoustic pressure coupler. A Bruel and

KjærType 4138 microphone is used as the reference microphone. The microphone is excited

with a periodic random bandlimited white noise signal going from 100Hz to 25.6kHz with 4

periods using the PULSE system. The interface circuit used for this test is a voltage buffer.

102

103

104

10−2

100

102

Sen

sitiv

ity (

µV/P

a)

Corrected DataRaw Data

102

103

104

−100

0

100

200

300

Frequency (Hz)

Pha

se (

Deg

.)

Figure 6-6. Frequency response with dc bias (5V ) with air medium.

The top and bottom plate of the microphone is biased with a regulated ±5V dc bias. Since the

speaker has a built in bandpass filter with a low frequency cut in of 300Hz, all the data plotted is

shown from 300Hz. The spectrum of the DUT and reference microphone output was measured

using an FFT analyzer with a 4Hz bin width and 1000 averages and is shown in Figure 6-6. The

roll-off of the microphone magnitude frequency response is due to the relative placement of the

reference microphone and DUT which was discussed earlier in this chapter in Section 6.3.1. The

frequency response corrected for the placement of DUT and reference microphone is also shown.

136

102

103

104

10−1

100

101

Sen

sitiv

ity (

µV/P

a)

102

103

104

−100

0

100

Frequency (Hz)

Pha

se (

Deg

.)

Figure 6-7. Frequency response with dc bias (5V ) with helium medium.

The magnitude and phase frequency response is shown in Figure 6-6. It can be seen that the

microphone has a flat frequency response from 300Hz to 5.6kHz with a sensitivity of 3.8uV/Pa

at 1kHz. Over this frequency range the phase varies from 39 deg to 9 deg.The acoustic pressure

coupler is then filled with helium and the experiment is repeated. The magnitude and phase

frequency response of the microphone in helium medium is shown in Figure 6-7. The system has

a flat frequency response from 300Hz to 13.4kHz and a sensitivity of 3.9uV/Pa.

6.3.3 Open Loop Frequency Response of Microphone with Synchronous Modulator /Demodulator (dc + ac bias)

In this section, the open loop characterization of the microphone is presented. The block

diagram of the open loop system described in Chapter 2 is repeated in Figure 6-8. The top

Charge Amp MultiplierVac sin(wct) Vout(Demod) Lowpass FilterCintVxVdc+Vac sin(wct)-Vdc-Vac sin(wct)

RDCCp CiC1C2 AFigure 6-8. Schematic of capacitive microphone with a synchronous modulation and

demodulation technique using a voltage amplifier based circuit.

137

and bottom plate 1MHz sine wave voltages are generated using two Agilent 33014C function

generator that are 180 deg out of phase. Two different ac voltage amplitudes are used, 6Vpp and

9Vpp. The reference input to the demodulator is obtained from another Agilent 33014C function

generator that is phase locked to the top plate voltage with a 5Vpp signal. The test setup used is

similar to the previous experiment.

102

103

104

101

102

Sen

sitiv

ity (

µV/P

a)

9V

pp

6Vpp

Theoretical (6Vpp

)

Theoretical (9Vpp

)

102

103

104

−200

−100

0

100

200

Frequency (Hz)

Pha

se (

Deg

.)

Figure 6-9. Open loop frequency response measured at the output of low pass filter (Node A,Figure 6-8) with dc (5V ) and ac bias voltages (6Vpp and 9Vpp and demodulator at5Vpp) after compensating for magnitude frequency response slope introduced by theacoustic pressure coupler.

102

103

104

100

101

102

Sen

sitiv

ity (

µV/V

/Pa)

9V

pp

6Vpp

102

103

104

−200

−100

0

100

200

Frequency (Hz)

Pha

se (

Deg

.)

Figure 6-10. Open loop frequency response normalized to the peak ac voltage measured at theoutput of low pass filter (Node A, Figure 6-8) with dc (5V ) and ac bias voltages(6Vpp and 9Vpp and demodulator at 5Vpp) after compensating for magnitudefrequency response slope introduced by the acoustic pressure coupler.

138

0 50 100 150 200 250 300 3500

500

1000

1500

2000

2500

3000

3500

Input pressure (Pa)

Out

put v

olta

ge (

µV)

9V

pp

6Vpp

Figure 6-11. Open loop linearity of the open loop system as measured at the output of thedemodulator (Node A,Figure 6-8 ) for two different ac bias voltage at an inputfrequency of 2kHz. The straight line fit has a regression value, R2, of 0.98

A dc bias of 5V is used. The microphone is excited with a periodic random bandlimited

white noise signal going from 100Hz to 6.4kHz with 4 periods using the PULSE system. The

spectrum of the DUT and reference microphone output was measured using an FFT analyzer

with a 4Hz bin width and 1000 averages. The open loop frequency response of the system after

accounting for the acoustic pressure coupler is shown in Figure 6-9 along with the theoretical

sensitivity. At 2kHz, the microphone has a sensitivity of 7.3uV/Pa for a 6Vpp ac bias and

10.47uV/Pa for a 9Vpp ac bias. Table 6-1 shows a comparison between the theoretical and

simulated values for the sensitivity. A plot of the sensitivity of the system normalized to the peak

ac bias voltage is shown in Figure 6-10. It can be seen that both the curves coincide with each

other. This shows that the sensitivity is linearly related to the peak ac voltage.

Table 6-1. Comparison of simulated and experimental sensitivity.BiasingTechnique

Bias Voltages Simulation Experimental

dc dc voltage : 5V 4µV/Pa 3.9µV/Pa

dc + ac dc voltage : 5V , Top and bottom plate acvoltage 6Vpp, Demodulator : 5Vpp

7µV/Pa 7.3µV/Pa

6.3.4 Linearity of Open Loop Microphone

The linear range of the open loop system with ac bias is presented next. The microphone is

excited with a 2kHz acoustic wave of increasing amplitude. A plot of the rms output voltage as a

139

0 50 100 150 200 250 300 3500

50

100

150

200

250

300

350

400

Input pressure (Pa)

Out

put v

olta

ge (

µV/V

)

9V

pp

6Vpp

Figure 6-12. Linearity of the open loop system normalized to peak ac bias voltage as measured atthe output of the demodulator (Node A,Figure 6-8 ) for two different ac bias voltageat an input frequency of 2kHz. The straight line fit has a regression value, R2, of0.98

function of increasing input pressure is shown in Figure 6-11. It can be seen that the microphone

has a linear response up to 315Pa(143dB) for 6Vpp and 9Vpp ac bias. The maximum applied

pressure was stopped at 143dB to prevent possible damage to the device. The slope of the line

in the linearity plot is a measure of the sensitivity of the system at 2kHz. The microphone

itself has been shown to be linear up to 166dB [64]. The circuit operates with a ±15 power

supply and hence will be linear up to this pressure input. The slope of the input pressure versus

output voltage curve is 7.29uV/Pa for a 6Vpp ac bias and 10.3uV/Pa for a 9Vpp ac bias. This

corresponds to the sensitivity of the microphone at 2kHz discussed in Section 6.3.3. A plot of

the open loop linearity of the microphone normalized to the peak ac bias voltage is shown in

Figure 6-12. It can be seen that the curves for ac bias voltages of 6Vpp and 9Vpp approximately

coincide with each other.

6.3.5 Noise Floor of Open Loop Microphone

The noise floor of the system is obtained by measuring the output for no acoustic input.

In this experiment, the input to the amplifier driving the speaker was disconnected. A plot

of the power spectral density at the output of the demodulator for two different ac bias

voltages (6Vpp and 9Vpp is shown in Figure 6-13. From Figure 6-13, the noise floor at 2kHz

is 1.76uV . Dividing the noise floor with the sensitivity, the minimum detectable signal (MDS) is

140

101

102

103

104

100

101

102

Frequency (Hz)

rms

nois

e vo

ltage

(µV

)

9V

pp

6Vpp

Theory

Figure 6-13. Noise floor of microphone for two different ac bias voltages measured at the outputof the demodulator.

obtained. The MDS at 2kHz for 6Vpp and 9Vpp ac bias is 0.24Pa(81.6dB) and 0.17Pa(78.5dB)

respectively. The theoretical noise floor derived in Chapter 4 is also superimposed on the plot.

It is seen that the experimental noise is lower than the theoretical noise. One possible reason for

this could because the amplifier noise specification used are the typical values. The actual noise

values could be lower than the typical values provided in the data sheet.

6.3.6 Compensator Characterization

For stable closed loop operation, a compensator is required to provide adequate gain and

phase margin. In this section, the results of the compensator characterization independent of

the system is presented. For this experiment, a 1uV swept sine signal was used as the input

to the compensator circuitry. The output of the compensator was measured, and a magnitude

and phase frequency response plot of the compensator is shown in Figure 6-14. A plot of the

theoretical compensator response discussed in Chapter 4 is overlaid on the experimental plot in

Figure 6-14. From Figure 6-14, it can be seen that the compensator has a dc gain of 77.8dB. It

can also be seen that the compensator has a dominant pole at 1kHz and a non-dominant pole at

30kHz. The zero of the system is at 230kHz and is not captured in Figure 6-14. This is because

the spectrum analyzer (SRS785) has a bandwidth of 101.3kHz. It can be observed from the

phase frequency plot that the phase does not continue reducing after the second pole but starts to

141

increase indicating the presence of a high frequency pole. It can be seen that the location of the

pole and zero positions are the same between simulation and experiment.

100

102

104

106

108

−100

−50

0

50

100

Mag

nitu

de (

dB)

TheoryExperiment

100

102

104

106

108

−100

0

100

Pha

se (

deg)

Frequency (Hz)

Figure 6-14. Theoretical and experimental frequency response of compensator.

6.3.7 Closed Loop Frequency Response

In this section, the results of closed loop operation of the system is presented. The block

diagram of the closed loop system described in Chapter 4 is repeated in Figure 6-15. FromSensor(Force todisplacement) IntefacecircuitPressure CompensatorArea Displacementto voltageVoltage toForceElectrostaticforceNetforce+-Inputforce A B

Figure 6-15. Block diagram of analog closed-loop system showing microphone and interfacecircuit.

linear control theory [126], during closed loop operation, if the forward path of the system has

a high gain, the signal at any point in the forward path of a closed loop system is attenuated by

the loop gain. Thus, to demonstrate closed loop operation, the frequency response of the system

measured at the output of the interface circuit (Node A in Figure 6-15) is compared to the open

loop response shown in Figure 6-9. The frequency response of the closed loop system measured

142

at the output of the interface circuit (Node A in Figure 6-15) is shown in Figure 6-16 along with

the theoretical curve for ac bias voltages of 6Vpp and 9Vpp. This frequency response is compared

to the frequency response of the open loop system shown in Figure 6-17 and Figure 6-18 for 6Vpp

and 9Vpp ac bias. The magnitude frequency response at 2kHz is 1.27uV/Pa with a 6Vpp ac bias

102

103

104

10−1

100

101

102

Sen

sitiv

ity(u

V/P

a)

6Vpp

9Vpp

Theoretical 6Vpp

Theoretical 9Vpp

102

103

104

−200

−150

−100

−50

0

50

100

150

200

Pha

se (

deg)

Frequency

Figure 6-16. Closed loop frequency response measured at the output of demodulator with dcbias of 5V , ac bias of 9Vpp, and demodulator at 5Vpp (Node A in Figure 6-15).Frequency response corrected for reference microphone and DUT location.

voltage and 1.89uV/Pa with a 9Vpp ac bias voltage. An increase in phase was observed in closed

loop response at the output of the demodulator which was not observed in open loop. The cause

of this phase increase is not clear but may be due to the coupling capacitors used between the

stages. Compared with the open loop magnitude frequency response measured at 2kHz, with the

same bias voltage, this represents a 5× reduction in diaphragm displacement. Thus the system

operates in a stable fashion in closed loop. The experimental loop gain of the system, T evaluated

at 2kHz, is given by the product of the system sensitivity , H1, expressed in uV/N evaluated

at 2kHz, compensator gain H2, evaluated at 2kHz, and voltage to force transfer function, H3,

evaluated at 2kHz , i.e.

T = H1 ×H2 ×H3 (6–2)

It should be noted that in this work, the voltage to force transfer function was not experimentally

evaluated. Therefore, H3 is calculated using Equation 4–10. Also, the sensitivity of the system

in uV/Pa obtained from Figure 6-9 is converted to uV/N by dividing the sensitivity by the

143

102

103

104

10−1

100

101

102

Sen

sitiv

ity(µ

V)

Open LoopClosed Loop

102

103

104

−200

−100

0

100

200

Pha

se (

deg)

Frequency

Figure 6-17. Closed loop frequency response measured at the output of demodulator (Node A inFigure 6-15) with dc bias of 5V , ac bias of 6Vpp, and demodulator at 5Vpp in openand closed loop operation. Frequency response corrected for reference microphoneand DUT location.

effective area of the diaphragm. Using Equation 6–2, the experimental loop gain of the system

is 5.28. From linear control theory, the diaphragm displacement is attenuated by 1 + T . This

implies that the diaphragm displacement should be attenuated by 6.28×. The actual diaphragm

displacement is only 5×. This discrepancy can be attributed to the modeling errors used in

the voltage to force transfer function. Figure 6-17 and Figure 6-18 show a comparison of the

magnitude and phase frequency response in open and closed loop operation with an ac bias of

6Vpp and 9Vpp respectively compensated for the reference microphone and DUT location.

The frequency response of the closed loop system at the output of the compensator (Node

B, Figure 6-15) after compensating for the transfer function of the pressure coupler is shown

in Figure 6-19. The magnitude frequency response at 2kHz is 2.63mV/Pa with a 6Vpp ac bias

voltage and 3.56mV/Pa with a 9Vpp ac bias voltage.

6.3.8 Closed Loop Linearity

A plot of the closed loop linearity measured at the output of the compensator (Node B,

Figure 6-15) for 6Vpp and 9Vpp ac bias voltages ac bias voltages is shown in Figure 6-20. It can

be seen that the system has a linear response upto an input pressure of 315Pa(144dB). Further

144

102

103

104

10−1

100

101

102

Sen

sitiv

ity(µ

V)

Open LoopClosed Loop

102

103

104

−200

−100

0

100

200

Pha

se (

deg)

Frequency

Figure 6-18. Closed loop frequency response measured at the output of demodulator (Node A inFigure 6-15) with dc bias of 5V , ac bias of 9Vpp, and demodulator at 5Vpp in openand closed loop operation. Frequency response corrected for reference microphoneand DUT location.

increase in input pressure was not carried out to prevent possible damage to the microphone

diaphragm. The slope of the input pressure versus output voltage curve is 2.63mV/Pa for

a 6Vpp ac bias and 3.56mV/Pa for a 9Vpp ac bias. This corresponds to the sensitivity of the

microphone at 2kHz in Figure 6-19. A plot of the open loop linearity of the microphone

normalized to the peak ac bias voltage is shown in Figure 6-21. It can be seen the plots for for ac

bias voltages of 6Vpp and 9Vpp approximately coincide with each other.

6.3.9 Closed Loop Noise Floor

The noise floor of the system is obtained by measuring the output of the compensator

for no acoustic input. In this experiment, the input to the amplifier driving the speaker was

disconnected. A plot of the power spectral density at the output of the demodulator for 6Vpp and

9Vpp ac bias voltages is shown in Figure 6-22. From Figure 6-22, the noise floor at 2kHz is

1.11mV . Dividing the noise floor with the sensitivity, the minimum detectable signal (MDS) is

obtained. The MDS at 2kHz for 6Vpp and 9Vpp ac bias is 106.5dB and 103.8dB respectively.

The large noise floor is discussed in the next section.

145

102

103

104

10−1

100

101

102

Sen

sitiv

ity(m

V)

6V

pp

9Vpp

102

103

104

−200

−100

0

100

200P

hase

(de

g)

Frequency

Figure 6-19. Closed loop frequency response measured at the output of compensator (NodeB in Figure 6-15) with dc bias of 5V ac bias of 9Vpp, and demodulator at 5Vpp.Frequency response corrected for reference microphone and DUT location.

0 50 100 150 200 250 300 3500

200

400

600

800

1000

1200

Input pressure (Pa)

Out

put v

olta

ge (

mV

)

9V

pp

6Vpp

Figure 6-20. Linear range of system in closed loop configuration as measured at the output ofthe compensator (Node B in Figure 6-15) with 6Vpp and 9Vpp ac bias voltages for aninput frequency of 2kHz. The straight line fit has a regression value, R2, of 0.97

6.4 Discussion

A closed loop analog controller for a MEMS dual backplate capacitive microphone

has been characterized in terms of frequency response, noise floor, and linear range. The

performance characteristics of the system in open and closed loop operation is listed in Table 6.4.

The reduction in the output of the demodulator is approximately 5× which is approximately

consistent with that predicted to the reduction of loop gain.

146

0 50 100 150 200 250 300 3500

20

40

60

80

100

120

140

Input pressure (Pa)

Out

put v

olta

ge (

mV

/V)

9V

pp

6Vpp

Figure 6-21. Linearity of the closed loop system normalized to peak ac bias voltage as measuredat the output of the compensator (Node B in Figure 6-15 ) for two different ac biasvoltage at an input frequency of 2kHz. The straight line fit has a regression value,R2, of 0.98

101

102

103

104

102

103

104

105

Frequency (Hz)

rms

nois

e vo

ltage

(µV

)

9V

pp

6Vpp

Figure 6-22. Noise floor of the circuit in closed loop operation as measured at the output of thecompensator (Node B in Figure 6-15) with 6Vpp and 9Vpp ac bias voltages.

The performance metrics of the open loop microphone using synchronous modulation

and demodulation interface circuit is compared to the performance metrics of the microphone

using a low noise voltage amplifier and a charge amplifier [64]. Martin reports a sensitivity

of 166uV/Pa and 368uV/Pa with a 9.3V bias using a voltage amplifier and charge amplifier

respectively. The reported interface circuits have a noise floor of 22.7dB and 41.5dB with a

voltage and charge amplifier respectively. The linear range of the interface circuit extends up

to an input pressure of 166dB. Based on this information, the dynamic range reported in this

147

Table 6-2. Characterization results of microphone in open and closed loop mode of operation.Bias condition Sensitivity at

2kHzNoise floor Linear range

Open loop (ac 6Vpp) 7.3uV/Pa 81.6 81.6dB−143dB

Open loop (ac 9Vpp) 10.47uV/Pa 78.5 78.5dB−143dB

Closed loop (ac 6Vpp) 2.63mV/Pa 106.5 106.5dB −143dB

Closed loop (ac 9Vpp) 3.56mV/Pa 103.8 103.8dB −143dB

work is considerably lower. The reasons are as follows. In this work, the amplifiers are chosen

to have a large bandwidth to be used in synchronous modulation and demodulation and a high

operating voltage and slew rate to support the feedback voltage requirements whereas in the work

published by Martin only open loop operation was investigated. Amplifiers which simultaneously

satisfy the high voltage, bandwidth and slew rate conditions have higher noise than amplifiers

with lower bandwidth and lower power supply voltages. This is because the transistors used to

implement the amplifiers must have larger size to support the increased current required for the

high frequency operation and the high voltage requirement. The closed loop interface circuit

also has increased component count due to the need for a high gain compensation network.

All these factors increase the noise floor of the closed loop microphone system. In closed loop

accelerometers, the bandwidth of the sensor is lower (approximately 1kHz). This reduces the

bandwidth requirement of the amplifiers used to implement closed loop control. Hence closed

loop accelerometers can potentially be implemented with a lower noise floor.

Closed loop capacitive interface circuits have primarily been used for low bandwidth

(1 − 2kHz) application such as accelerometers [68, 67, 11, 2, 112]. The main advantage

of a closed loop interface circuit is the possibility of increased bandwidth and linear range.

Also closed loop interface circuits have the potential to address pull in issues as the diaphragm

deflection is reduced. In this work, a proof of concept closed loop interface circuit has been

presented for a comparatively higher bandwidth ( 20kHz) application compared to potential

closed loop accelerometer applications. Closed loop control was demonstrated by showing that

the diaphragm deflection was reduced during closed loop operation. This was verified for two

different voltage bias conditions. The disadvantages of closed loop interface circuits is a higher

148

noise floor because of the increased number of components needed and the requirement of a high

gain stage due to the small voltage-to-force factor.

6.5 Summary

In this section, the experimental results were presented. The design and characterization of

the test setup was first presented. This was followed by open and closed loop characterization

of the microphone. A comparison of the interface circuit performance was compared to other

interface circuits for the same device and with interface circuits for other capacitive transducers.

149

CHAPTER 7CONCLUSION AND FUTURE WORK

In this chapter, the key goals of the work and the results are summarized. Key contributions

of this research are highlighted. This chapter concludes with a discussion on the avenues for

further research in this area.

7.1 Conclusion

The goal of this work is to design and characterize interface circuits that are optimized

for miniature capacitive transducers. As transducer geometry is scaled down, improved circuit

techniques are required to measure the sensor output. This is because at small geometries sensor

capacitance is comparable to unwanted parasitic capacitance which reduces the transducer

sensitivity. Also, at reduced sensor geometry, the voltage required to bias the microphone could

cause the microphone plates to pull in.

In this work, an extensive study of open loop and closed interface techniques for capacitive

sensors has been presented along with theoretical formulations for key performance metrics.

An analog closed loop controller for a dual backplate MEMS capacitive microphone was

designed. A detailed MATLAB model which captures key dynamics of the sensor and controller

was developed. Noise models of the closed loop system was also developed. Open and closed

loop simulations were performed for step and sinusoidal excitations. From these simulations, it

can be seen that in closed loop operation, the diaphragm displacement is attenuated which can

potentially address pull in issues.

A proof of concept closed-loop analog controller for a MEMS capacitive microphone was

developed and characterized. A test apparatus was developed to characterize the system over the

audio range by operating the microphone in a helium medium which increases the bandwidth of

the test apparatus. Characterization of the microphone in open and closed loop mode of operation

is presented. Results show that stable closed loop operation of the microphone is feasible with

increased sensitivity and the potential to address pull-in issues.

7.2 Future Work

The future areas of research in this project can be partitioned into simulation related and

hardware implementation related future work. These two topics are discussed next.

150

7.2.1 Simulation

In the open and closed loop Matlab simulations presented in this work, a 2nd order linear

model of the microphone was used. This can be expanded to include a detailed non-linear model

of the microphone which incorporates pull-in effects and mechanical non-linearities of the

microphone.

Another area of research is detailed transistor level simulations using SPICE. Transistor

level simulations allows noise analysis of the system which is not possible with MATLAB

simulations. To successfully perform these simulations, the microphone must also be modeled in

SPICE using analog modeling blocks. Furthermore noise models for the circuit elements must be

available.

7.2.2 Hardware Implementation

A number of improvements can be suggested for the next version of the closed loop

controller. In the current work, a two PCB approach wherein the microphone and buffer amplifier

is mounted on one PCB and the controller is mounted on a different PCB and connected using

ribbon connectors is used. This increased the 60Hz pick-up of the circuit. In future versions

of the controller, a single PCB which incorporates both the microphone and the controller can

be used. In the current work, dual in-line package (DIP) components were used to allow easy

testing and debugging. The downside of using DIP components is increased parasitics and noise.

Future versions of the controller may use surface mount components in order to reduce parasitic

capacitance and electromagnetic coupling.

It was also noticed that 60Hz noise in both the input channels of the demodulator caused

120Hz noise signals at the output of the demodulator. One of the sources of 60Hz pick up is the

cables connecting the function generator output to the controller PCB. This source of noise pick

up can be reduced by generating the clock signal on the PCB itself using oscillator ICs.

Another avenue for research could be to monolithically integrate the interface circuit and

controller using a high voltage, high frequency, and low noise process. This will greatly improve

circuit performance because of the reduced parasitics which will improve the sensitivity. Also

monolithic integration will eliminate the need for cables that are used for clock generation as the

clock signal can be generated on chip.

151

APPENDIX A

A.1 Derivation of Sensitivity for a Voltage Follower

In this technique the top and bottom backplate of the microphone with top and bottom

capacitances given by C1 and C2 are biased at a dc potential of +Vdc and −Vdc volts. A unity

gain voltage amplifier is connected to the middle plate as shown in Figure A-1 This resultsVxRDC -+ VoutCLC1C2-Vdc+Vdc Cp Ci

Figure A-1. Noise model of dual backplate microphone connected to voltage buffer.

in fixed charge of +Qdc and −Qdc on the top and bottom capacitor respectively. Cp and Ci

represent the interconnect parasitic capacitance and the input capacitance of the amplifier

respectively. The top and bottom plate capacitance is given by

C1 =ε0A

x0 − x′(A–1)

C2 =ε0A

x0 + x′

The nominal capacitance C0 is given by the expression

C0 =ε0A

x0

(A–2)

Equation A–2 can be expressed in terms of the nominal capacitance C0 and a varying capacitance

∆C using the relation

C1 = C0 + ∆C1 (A–3)

C2 = C0 −∆C2

152

Using Equation A–1 the voltage across the top and bottom capacitor V1 and V2 respectively is

given by

V1 =x0 − x′

ε0A(A–4)

V2 =x0 + x′

ε0A

This shows that the voltage varies linearly with gap distance. The voltage across each capacitor

can also be expressed in terms of the fixed charge Qdc as

V1 =Qdc

C0 + ∆C(A–5)

V2 =Qdc

C0 −∆C.

Substituting Equation A–1, Equation A–2 in Equation A–6 we obtain

εA

x0 − x′= ∆C1 +

x′

x0

(A–6)

εA

x0 + x′= ∆C2 − x′

x0

Solving Equation A–6 for ∆C1 and ∆C2

∆C1 =x′

x0

εA

x0 − x′(A–7)

∆C2 =x′

x0

εA

x0 + x′

To obtain the output voltage we solve for the voltage at the inverting node using the

principle of superposition. Initially we consider only the output due to the top capacitance. This

implies that the bottom plate is grounded. The initial charge on the top capacitor Q1i system is

given by

Q1i = C0Vdc (A–8)

The final charge is given by

Q1f = C1V1 − C2VoutC1 (A–9)

Equating Equation A–8 and Equation A–9 we obtain

C0Vdc = C1V1 − C2VoutC1 (A–10)

153

Substituting for C1 as C0 + ∆C and V1 as Vdc − VoutC1 in Equation A–10 we obtain

C0Vdc = (C0 + ∆C) V1 − C2VoutC1 . (A–11)

Solving for VoutC1 we obtain

VoutC1 =∆C1

C1 + C2

Vdc. (A–12)

Similarly for VoutC2 we obtain

VoutC2 =∆C2

C1 + C2

Vdc. (A–13)

The total output of the amplifier Vout is the sum of outputs given by Equation A–12 and

Equation A–13,

Vout =∆C1 + ∆C2

C1 + C2

Vdc (A–14)

If the capacitance change ∆C1 and ∆C2 are equal, i.e,

∆C1 = ∆C2 = ∆C (A–15)

and using Equation A–1, in Equation A–14 we obtain

Vout =∆C

C0

Vdc. (A–16)

From the input output relation given by Equation A–16, the electrical sensitivity of the circuit is

given by the equation

Se =Vdc

C0

. (A–17)

A.2 Noise Analysis for a Capacitive Microphone with a Voltage Follower

The complete noise model of the circuit with all the noise generators of the interface circuit

is shown in Figure A-2. The current and voltage noise spectral density (PSD) of the amplifier are

denoted by Sia and Sva respectively. The current and voltage noise PSD Si(f) and Se(f) can be

expressed as a function of the current and voltage noise corner frequency fci and fce by

Se(f) = v2ia(f) = v2

ia

(1 +

fce

f

)(A–18)

Si(f) = i2

ia(f) = i2

ia

(1 +

fci

f

)

154

C2 -+ VoutCLC1 Zi RDCCp Ci Sva SiaSvRFigure A-2. Noise model of dual backplate microphone connected to voltage buffer.

The power spectral density of the noise of the resistor is denoted by SvR. It is given by

SvR = 4kTRdc. (A–19)

The impedance of the parasitic capacitances and sense capacitor denoted by Zi is given by

Zi =1

jω (2C0 + Cp + Ci). (A–20)

We now use superposition to calculate the output voltage noise power spectral density. We

first consider only the noise generator Sva. With only the Sva noise generator, no current flow in

Zi or Rdc. The noise at the output Svo1 is given by

Svo1 = Sva. (A–21)

Next we consider only the noise generator Sia. It can be seen that the total impedance seen by

this noise generator is is the parallel combination of Zi and Rdc. Thus the noise generated at the

output Svo2 is given by

Svo2 = Sia

∣∣∣∣ZiRdc

Zi + Rdc

∣∣∣∣2

. (A–22)

Finally we consider the noise due to the resistor. It can be seen from the circuit that noise due to

the resistor is shaped by the voltage divider consisting of the of Rdc and Zi. Hence the noise at

the output Svo3 due to the resistor is given by

Svo3 = SvR

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

. (A–23)

155

Using superposition the power spectral density of the output noise voltage v2no of the circuit is

given by the sum of Equation A–21, Equation A–22, Equation A–23

Svo = Sva + Sia

∣∣∣∣ZiRdc

Zi + Rdc

∣∣∣∣2

+ SvR

∣∣∣∣Zi

Zi + Rdc

∣∣∣∣2

. (A–24)

It should be noted that the noise analysis presented here considers only the noise sources

due to the electrical interface circuit. The thermo-mechanical sources of noise associated with the

sensor itself are not considered in this analysis.

A.3 Derivation of Sensitivity for a Charge Amplifier

The top and bottom plate capacitor is given by

C1 = C0

[1 +

x′

x0

](A–25)

C2 = C0

[1− x′

x0

]

The charge on each capacitor is given by

Q1 = C1Vdc (A–26)

and

Q2 = −C2Vdc

The net charge transferred is given by

∆Q = Q1 + Q2 (A–27)

The output voltage for a charge amplifier is given by

Vout = Cint∆Q (A–28)

Substituting for Q1 and Q2 in Equation A–28 and simplifying

Vout =

[Vdc

Cint

]∆C. (A–29)

From the input-output relationship given by Equation A–29 the electrical sensitivity of the circuit

is given by the equation

Se =2Vdc

Cint

. (A–30)

156

A.4 Noise Analysis for a Capacitive Microphone with a Charge Amplifier

The complete noise model of the circuit with all the noise generators is shown in

Figure A-3. The current and voltage noise power spectral density of the amplifier are denoted by

Sva and Sia respectively. The power spectral density of the current noise of the resistor is denoted

by SiR. It is given by

SiR = 4kT1

Rdc

∆f. (A–31)

The impedance of the parasitic capacitances and sense capacitor which is denoted by Zi is given

by ma

Zi =1

jω (2C0 + Cp + Ci). (A–32)

The impedance of the feedback network denoted by Zf is given by

Zf = Rdc‖ 1

jω Cint

. (A–33)

now use superposition to calculate to the output voltage noise power spectral density. We firstC1 Cp Ci Cint +-RDC VoutCLC2 Zi SiRSva SiaFigure A-3. Noise model of dual backplate microphone connected to charge amplifier.

consider only the noise generator Sva. The noise at the output Svo1 due to Sva noise generator is

given by

Svo1 = Sva

(1 +

Zf

Zi

)2

(A–34)

157

Next we consider only the noise generator Sia. It can be seen that the total impedance seen by

this noise generator is Zf . the noise at the output Svo2 due to Sia noise generator is given by

Svo2 = SiaZ2f . (A–35)

Similarly the output voltage noise due to the resistor current noise, Svo3, is given by the relation

Svo3 = SiaZ2f . (A–36)

Using superposition the power spectral density of the output noise voltage Svo is given by the

sum of Equation A–34, Equation A–35, and Equation A–36 and is given by the expression,

Svo1 = Sva

(Zf

Zi

)2

+ SiaZ2f + SiRZ2

f (A–37)

Since we are interested in the noise PSD after the cut in frequency i.e.,

ω >>1

CintRdc

, (A–38)

Simplifying

SVout = Sva

[1 +

(Ctot

Cint

)]2

+ (Sia + SiR)1

(ωCint)2 . (A–39)

Equation A–39 shows that both the resistor current noise and the amplifier current noise are 1/f 2

shaped.

A.5 Sensitivity for Synchronous Modulation and Demodulation Interface Circuit

In this section the linearized sensitivity of a synchronous modulation and demodulation

based interface circuit is derived. In this technique, the top plate is biased with a a square wave

with 50% duty cycle of amplitude Vac at a frequency of ωc on a dc voltage Vdc. The bottom plate

is biased with signal with the same magnitude as the top plate but 180deg out of phase.

The carrier wave input r(t) to the demodulator also consists of a square wave at a frequency

of ωc but with an amplitude of Vc. The fourier series representation x(t) of a square wave of

amplitude A with 50% duty cycle is given by

x(t) =A

2+

2A

πcos(ωt) +

1

3

2A

πcos(3ωt) +

1

5

2A

πcos(5ωt)... (A–40)

158

To reduce the movement of microphone diaphragm due to the applied AC voltage, Vac is

kept small. Since we are doing a linearized analysis, the higher order harmonics are neglected.

The top plate voltage vtp is given by

vtp(t) = Vdc +Vac

2+

2Vac

πcos(ωct). (A–41)

The carrier wave applied to the demodulator is given by

r(t) =Vc

2+

2Vc

πcos(ωct). (A–42)

The output of the buffer amplifier vmod(t) is given by Equation 3–13 as

vmod(t) =x′

x0

vtp(t). (A–43)

If the input acoustic signal is at a frequency ωm, and the maximum displacement of the

diaphragm is x′0 then

x′ = x′0cos(ωmt). (A–44)

Therefore

vmod(t) =x′0x0

cos(ωmt)vtp(t). (A–45)

Substituting for vtp

vmod(t) =

[x′0x0

cos(ωmt)

]×

[Vdc +

Vac

2+

2Vac

πcos(ωct)

]. (A–46)

Using the trigonometric identity cosAcosB = 1/2(cos(A + B) − cos(A − b)), vmod(t) can be

expressed as

vmod(t) =x′0x0

(Vdc +

Vac

2

)cos(ωmt) (A–47)

+x′0x0

2Vac

πcos(ωm + ωc)t

+x′0x0

2Vac

πcos(ωm − ωc)t

The output of the buffer amplifier vdemod(t) is given by as

vdemod(t) = vmod(t)× r(t). (A–48)

159

Substituting for , vmod(t) and r(t)

vdemod(t) =x′0x0

(Vdc +

Vac

2

)cos(ωmt)×

[Vc

2+

2Vc

πcos(ωct)

](A–49)

+x′0x0

2Vac

πcos(ωm + ωc)t×

[Vc

2+

2Vc

πcos(ωct)

]

+x′0x0

2Vac

πcos(ωm − ωc)t×

[Vc

2+

2Vc

πcos(ωct)

]

(A–50)

Expanding the above equation

vdemod(t) =x′0x0

× (A–51)[(

Vdc +Vac

2

)Vc

2

]cos(ωmt) +

(Vdc +

Vac

2

)cos(ωmt)

2Vc

πcos(ωct) +

2Vac

πcos(ωm + ωc)t

Vc

2+

2Vac

πcos(ωm + ωc)t

2Vc

πcos(ωct)

2Vac

πcos(ωm − ωc)t

Vc

2+

2Vac

πcos(ωm − ωc)t

2Vc

πcos(ωct)

Using trigonometric identity vdemod(t) can be expressed as

vdemod(t) =x′0x0

× (A–52)[(

Vdc + Vac

2

)Vc

2

]cos(ωmt) +

(Vdc + Vac

2

)2Vc

π(((((((((cos(ωm + ωc)t +((((((((

cos(ωm − ωc)t)

+(((((((((((2Vac

πcos(ωm + ωc)t

Vc

2+ 2Vac

π2Vc

π12[cos(ωm)t +((((((((

cos(ωm + 2ωc)t]

+(((((((((((2Vac

πcos(ωm + ωc)t

Vc

2+ 2Vac

π2Vc

π12[((((((((cos(ωm − 2ωc)t + cos(ωm)t]

The low pass filtered signal vout(t) can be expressed as

vout(t) =x′0x0

× (A–53)[(

Vdc + Vac

2

)Vc

2

]cos(ωmt)

+2Vac

π2Vc

π12[cos(ωm)t]

+2Vac

π2Vc

π12[cos(ωm)t]

160

which reduces to

vout(t) =x′0x0

×[(

Vdc +Vac

2

)Vc

2cos(ωmt) +

2Vac

π

2Vc

π[cos(ωm)t]

](A–54)

Substituting for x′0cos(ωm)t as x′ we obtain

vout(t) =x′

x0

×[(

Vdc +Vac

2

)Vc

2+

2Vac

π

2Vc

π

](A–55)

The linearized sensitivity of this interface technique is

vout(t)

x′=

1

x0

×[(

Vdc +Vac

2

)Vc

2+

2Vac

π

2Vc

π

](A–56)

161

APPENDIX B

B.1 Bandwidth Considerations for Amplifiers in Switched Capacitor Amplifiers

This derivation is based on the work presented in Wongkomet’s doctoral dissertation [108].

The time constant τ of a single pole amplifier is related to its closed loop bandwidth fu by the

relation

fu =1

2πτ. (B–1)

Let the number of time constants required for the amplifier to settle be denoted by nτ , sampling

frequency by fs and the fraction of time spent in the amplify phase by m(< 1). The time

available for the switched capacitor amplifier to settle is thus m× 1

fs

. The time required for the

amplifier to settle within a given error criteria is nτ × τ . For example, for 0.1% settling, nτ must

be equal to seven. Equating the time required and time available for settling, we obtain

m× 1

fs

= nτ × τ (B–2)

Substituting for τ and rearranging the equation, we obtain

fu =1

2π

[m

nτfs

]−1

(B–3)

B.2 Analysis of Noise in a Switched Capacitor Amplifier

This derivation is based on the work presented in Wongkomet’s doctoral dissertation [108].

The noise model of the amplifier during the amplification phase is shown in Figure B-1C1=C0C2=C0 -CgainCreset-CgainCreset+V+

CL Voutv2nCp 4kTRonRonFigure B-1. Noise model of switched capacitor amplifier during amplify phase.

162

The noise of the amplifier is modeled as a wide band white noise v2n at the inverting terminal

of the amplifier. The total capacitance at the input of the amplifier is given by

CT = 2C0 + Cp + Cgain. (B–4)

We shall now derive the total noise at the output due to kT/C noise and due to the wideband

amplifier noise.

B.2.1 Switch Resistance Noise

In this section the total output noise due to the on resistance of the switches is derived.

When the switches are closed, the noise due to on resistance of the switches is low pass filtered

by the total capacitance CT

v2kT/Cinput

=kT

CT

. (B–5)

Referring this noise to the output by multiplying the previous equation by the square of the gain

we obtain the total output kT/C noise The total noise at the output of the amplifier is given by

v2kT/C =

[CT

Cgain

]2kT

CT

. (B–6)

B.2.2 Wideband Amplifier Noise

In this section the total output noise due to the wideband amplifier noise is presented. The

noise at the input of the amplifier is

v2opampinput

= v2n. (B–7)

The total output noise voltage is

v2opamp =

∫ ∞

0

[CT

Cgain

]2

v2ndf. (B–8)

For a single pole system, the equivalent noise bandwidth is π/2 times the bandwidth[79].

Therefore the total output noise for an amplifier with a closed loop bandwidth of fu

v2opamp =

[CT

Cgain

]2

v2nfu

π

2. (B–9)

163

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BIOGRAPHICAL SKETCH

Karthik Kadirvel was in Chennai, Tamil Nadu, India. He moved to the United Arab

Emirates in 1989 and graduated from Our Own English High School in Dubai, United Arab

Emirates in 1996. He went back to India for his Bachelors degree and obtained his Bachelor of

Engineering degree specializing in Electronics and Instrumentation from Annamalai University,

Tamil Nadu, India in May 2000. He obtained his Master’s degree at the University of Florida in

2002. His thesis was on the design and characterization of a MEMS optical microphone. He is

currently pursuing his doctoral degree at Interdisciplinary Microsystem Group at the University

of Florida.

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