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10.1109/TIE.2014.2336601, IEEE Transactions on Industrial ElectronicsIEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A Single-Phase Cascaded Multilevel Inverter

Based on a New Basic Unit with Reduced

Number of Power SwitchesEbrahim Babaei, Member, IEEE , Sara Laali, Student Member, IEEE , and Zahra Bayat

Abstract — In this paper, a new single-phase cascaded

multilevel inverter is proposed. This inverter is comprisedof series connection of the proposed basic unit and is able

to generate only positive levels at the output. Therefore,an H-bridge is added to the proposed inverter. This

inverter is called developed cascaded multilevel inverter.In order to generate all voltage levels (even and odd) atthe output of the developed topology, four different

algorithms are proposed to determine the magnitude ofdc voltage sources. Reduction in the number of power

switches, driver circuits and dc voltage sources areadvantages of the developed single-phase cascadedmultilevel inverter. As a result, the installation space and

cost of the inverter are reduced. These features are

obtained by the comparison of the conventional cascadedmultilevel inverters with the proposed cascaded topology.The ability of the proposed inverter in generation all

voltage levels (even and odd) is reconfirmed by using theexperimental results of a 15-level inverter.

Keywords — Cascaded multilevel inverter; basic unit; H-

bridge; developed cascaded multilevel inverter.

I. INTRODUCTION

The demand for high voltage, high power inverters are

increasing and it is impossible to connect a powersemiconductor switch to high voltage network directly.

Therefore, the multilevel inverters had been introduced

and are developing now. There are different kinds ofarray for power switches, diodes and dc voltage

sources to generate a desired ac output in multilevelinverters. With an increasing the number of dc voltage

sources in input side, the sinusoidal like waveform can

be generated at the output. As a result, the total

harmonic distortion (THD) decreases and the outputwaveform quality of the increases, which are two mainadvantages of the multilevel inverters. In addition,

lower switching losses, lower voltage stress of dv dt

on switches; high efficiency and better electromagnetic

interference are other most important advantages of the

multilevel inverters [1-5]. These kinds of inverters are

generally divided into three main categories; neutral

point (NPC) clamped multilevel inverter, flyingcapacitor (FC) multilevel inverter and cascaded

Manuscript received July 19, 2013; revised November 24, 2013

and February 26, 2014; accepted April 23, 2014.Copyright © 2014 IEEE. Personal use of this material is permitted.

However, permission to use this material for any other purposes must

be obtained from the IEEE by sending a request to pubs- [email protected]

The authors are with the Faculty of Electrical and Computer

Engineering, University of Tabriz, Tabriz, Iran (e-mails: e- babaei@tabr izu.ac.i r; s.laali@tabri zu.ac.ir;

[email protected]).

multilevel inverter [6-9]. There is no diode clamped or

flying capacitors in cascaded multilevel inverters.

Moreover, these inverters consist of modularity, simplicity

of control and reliability and require lowest number of power semiconductor devices to generate a particular level

[1, 10-11]. As a result, the losses and total cost of theseinverters decrease and the efficiency will increase [12].Therefore, the cascaded multilevel inverter has received

more attentions. These inverters are comprised of series

connection of basic units, which consist of different array

of power switches and dc voltage sources. Generally, these

inverters divided into two main groups; symmetriccascaded multilevel inverter with the same amplitude of dc

voltage sources and asymmetric cascaded multilevelinverter. The asymmetric cascaded multilevel inverter

generates higher number of output levels in comparison

with symmetric one by same number of power electronicdevices because of different amplitude of its dc voltage

sources. As a result, the installation space and total cost ofan asymmetric cascaded multilevel inverter is lower than

symmetric one [11-12].Up to now, different basic units and so different cascaded

multilevel inverters have been presented in literature. In

[13-18], different symmetric cascaded multilevel invertershave been presented. It is also presented another topology

with two different algorithms as symmetric and

asymmetric one in [19]. The main disadvantages of the

symmetric cascaded multilevel inverters are the high-required number of power switches, insulated gate bipolartransistors (IGBTs), power diodes and driver circuits

because of the same magnitude of dc voltage sources.These disadvantages will be higher in topologies which

bidirectional power switches from voltage point of view

have been used in them that presented in [15] and [19].

Each unidirectional switch requires an IGBT with an anti parallel diode and a driver circuit while bidirectional one

includes of two numbers of IGBTs, two anti parallel

diodes and one driver circuit if common emitterconfiguration is used. However, both unidirectional and

bidirectional power switches conduct current in bothdirections. In order to increase the number of output

levels, the different asymmetric cascaded multilevelinverters have been presented in [12, 14, 19-20]. The maindisadvantages of these inverters are the high magnitude of

dc voltage sources.Although, different symmetric and asymmetric cascaded

multilevel inverters had been presented in literature but in

order to increase the number of generated output levels byusing lower number of power electronic devices, a new

basic unit is proposed in this paper. By series connection

of several proposed basic units, a new single-phase

cascaded multilevel inverter is proposed. Then, in order togenerate all positive and negative levels at the output, a H-

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bridge will be added to this inverter because the proposed inverter only generates positive levels at the

output. This inverter called developed proposedcascaded multilevel inverter. In order to generate all

voltage levels at the output, four different algorithmsare proposed. Several comparisons are also done

between the developed cascaded multilevel inverter

and its proposed algorithms with the conventional

cascaded multilevel inverters. Based on these

comparisons, the developed cascaded inverter requiresminimum number of power switches, IGBTs, power

diodes, driver circuits and dc voltage sources. Finally,

in order to investigate the capability of the developedcascaded multilevel inverter in generation all voltage

levels, the experimental results of a 15-level inverter

are used.

II. PROPOSED TOPOLOGY

Fig. 1 shows the proposed basic unit. As shown in Fig.

1, the proposed basic unit is comprised of three dcvoltage sources and five unidirectional power switches

from voltage point of view. The used dc voltagesources are insolated ones that are supplied by

renewable sources such as fuel cell, photovoltaic etc. In

the proposed structure, the power switches of2 4

( , )S S ,

1 3 4 5( , , , )S S S S and

1 2 3 5( , , , )S S S S should not be

turned on simultaneously to prevent the short circuit of

dc voltage sources. The turn on and off states of power

switches for the proposed basic unit are shown in TableI. As shown in Table I, the proposed basic unit is able

to generate three different levels of 0,1 3

V V and

1 2 3( )V V V at the output. It is important to note that

the basic unit is only able to generate positive levels at

the output.

Fig. 1. Proposed basic unit

TABLE I.

Permitted turn on and off states for switches in the proposed basic

unit

ov

Switches statestate

5S 4S 3S 2S 1S

0onoffoffoffoff1

1 3V V offononoffon2

1 2 3V V V offoffononon3

In order to increase the number of output voltage

levels, it is possible to connect n number of basic unit

in series. As this inverter is able to generate all voltage

levels except1

V , it is necessary to use of additional dc

voltage source with the amplitude of1

V and two

unidirectional switches from voltage point of view that

are connected in series with the proposed basic units.

The proposed single-phase cascaded multilevel inverterthat is able to generate all levels is shown in Fig. 2(a). In

this inverter, the power switches of1

S and2

S and dc

voltage source of1

V have been used to produce the lowest

output level. The amplitude of this dc voltage source is

considered1 dcV V (equal to minimum output level). The

output voltage level of each unit is indicated by,1o

v ,,2o

v ,

, ,o nv and ov . The output voltage level ( )ov of the

proposed cascaded multilevel inverter is equal to:

,1 ,2 ,( ) ( ) ( ) ( ) ( )o o o o n ov t v t v t v t v t (1)

The generated output voltage levels of the proposed

inverter ( )o

v based on off and on states of switches are

shown in Table II. As mentioned before and according toTable II, the proposed inverter that is shown in Fig. 2(a) is

only able to generate positive levels at the output.

Therefore, in order to produce positive and negative levels

at the output an H-bridge with four switches of1

T to4

T is

added to the proposed topology. This inverter is called

developed cascaded multilevel inverter and shown in Fig.2(b). If the switches of

1T and

4T are turned on, the load

voltage ( ) Lv is equal to ov and if the power switches of

2T and3T are turned on, the load voltage will be

ov .

For the proposed inverter, the number of switches

( ) switch

N and dc voltage sources ( ) source

N are given by

below equations, respectively:

65 n N switch (2)

13 n N source (3)

when n is the number of series connected basic units.

As the unidirectional power switches from voltage point of

view are used in the proposed cascaded multilevel

inverter, the number of power switches is equal to thenumbers of IGBTs, power diodes and driver circuits.

(a) (b)

Fig. 2. The cascaded multilevel inverter; (a) proposed topology; (b)

developed proposed topology

The other main parameter in calculation the total cost of

the inverter is the maximum amount of blocked voltage by

the switches. If the values of the blocked voltage byswitches are reduced, the total cost of the inverter

decreases [12]. In addition, this value has most importanteffect in selection the semiconductor devices because this

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value determines the voltage rating of required powerdevices. Therefore, in order to calculate this index, it is

necessary to consider the amount of the blockedvoltage by each of the switches. According to Fig. 2(b),

the values of the blocked voltage by switch1

S and2

S

are equal to:

1 2 1,1S S V V V (4)

1, 2, 3,

1, 3,2

j j j

S j S j

V V V

V V

(5)

4, 2, 2,S j S j jV V V (6)

5, 1, 2, 3,S j j j jV V V V (7)

1 2 3 4 ,maxT T T T oV V V V V (8)

where,maxo

V is the maximum amplitude of producible

output voltage.

Therefore, the maximum amount of the blockedvoltage in the proposed cascaded multilevel inverter

( )block V is equal to:

,

1

n

block block j block block,H

j

V V V V

(9)

In (9),,block j

V ,block V and

block,H V indicate the blocked

voltage by th j basic unit, additional dc voltage sources

and the use H-bridge, respectively.In the developed inverter, the number and the maximum

amplitude of generated output levels are based on thevalue of used dc voltage sources. In order to generate all

voltage levels in the developed cascaded multilevel

inverter, four different algorithms are proposed to

determine the magnitude of dc voltage sources. These proposed algorithms and all their parameters are calculated

and shown in Table III. According to the facts that the

magnitude of all proposed algorithm except the first oneare different, the proposed cascaded multilevel inverter

based on these algorithms is considered as asymmetriccascaded multilevel inverter. In addition, based on theequations of the maximum output voltage levels and the

maximum amplitude of it, it is clear that these values in

the asymmetric cascaded multilevel inverter are more than

symmetric one with the same number of used dc voltagesources and power switches.

TABLE II.

THE GENERATED OUTPUT VOLTAGE LEVELS ( )ov BASED ON OFF AND ON STATES OF POWER SWITCHES

ov 1S

2S 1,1S

2,1S 3,1S

4,1S 5,1S

1,2S 2,2S

3,2S 4,2S

5,2S 1,nS

2,nS 3,nS

4,nS 5,nS

0 off on off off off off on off off off off on off off off off on

1V on off off off off off on off off off off on off off off off on

1,1 3,1V V off on on off on on off off off off off on off off off off on

1,1 2,1 3,1V V V off on on on on off off off off off off on off off off off on

1,2 3,2V V off on off off off off on on off on on off off off off off on

1,2 2,2 3,2V V V off on off off off off on on on on off off off off off off on

1,1 1,2 1,3

2,1 2,3

V V V

V V

off on on on on off off on off on on off

off off off off on

1,1 1,2 1,3

2,1 2,2 2,3

V V V

V V V

off on on on on off off on on on off off off off off off on

1, 2, 3,1

( )n

j j j j

V V V

off on on on on off off on on on off off off off off off on

1,1 1, 2, 3,

1

( )n

j j j

j

V V V V

on off on on on off off on on on off off off off off off on

TABLE III.

THE PROPOSED ALGORITHMS AND THEIR RELATED PARAMETERS

Proposed algorithm Magnitude of dc voltage sources level N

,maxoV

block V

First proposed algorithm1( ) P

1, 2, 3, j j j dcV V V V

1, 2, , for j n 6 3n (3 1) dcn V (21 6) dcn V

Second proposed algorithm2

( ) P

1,1 2,1 3,1 dcV V V V

1, 2, 3,2

j j j dcV V V V

2, 3, , for j n

12 3n 6 2n (40 13)dc

n V

Third proposed algorithm3( ) P

1,1 2,1 3,1 dcV V V V

2

1, 2, 3,

13

3

j

j j j dcV V V V

2, 3, , for j n

15(3 ) 4

n

15(3 ) 3

2

n

dcV

1[82(3 ) 7]n

dcV

Fourth proposed algorithm4( ) P

1

1, 2, 3,0.5 2 j

j j j dcV V V V

1, 2, , for j n

32 5n 2(2 3)n

dcV 2[7(2 ) 22]n

dcV

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III. COMPARING THE PROPOSED TOPOLOGY

WITH THE CONVENTIONAL TOPOLOGIES

The main aim of introducing the developed cascaded

multilevel inverter is to increase the number of outputvoltage levels by using minimum number of power

electronic devices. Therefore, several comparisons are done between the developed proposed topology with the

conventional cascaded multilevel inverters that have been

presented in literature. Theses comparisons are done from

the number of IGBTs, driver circuits and dc voltage sources points of view. In addition, the maximum amount of blocked voltage by power switches is also compared

between proposed cascaded multilevel inverter and other presented topologies in references because of the effect of

this value in voltage rating of used power devices in

topologies. It is important to note that the voltage rating ofselected power switches is completely depended on the

structure of used basic unit of cascaded multilevel inverters

and the considered algorithm to determine the magnitude of

dc voltage sources. For instance, there are symmetric andasymmetric states for conventional H-bridge multilevelinverters, which in symmetric condition the voltage rating

of all used semiconductor devices in all bridges are same

but in asymmetric condition, these values are directlydepended on the selected algorithm to determine the

magnitude of dc voltage sources. However, in asymmetric

H-bridge cascaded multilevel inverter, the voltage rating ofdevices that are used in each bridge are same to each other

but these values are different to the voltage rating of

devices in other bridges. In this comparison, the proposedcascaded inverter that is shown in Fig. 2(b) with its

proposed algorithms is considered by1

P to4

P ,

respectively. In [13], a symmetric cascaded multilevel

inverter has been presented that is shown by1

R in this

comparison. The conventional cascaded multilevel inverter

has been presented in [14]. This inverter that is known as

symmetric one is considered by2

R . In addition, two other

algorithms have been presented for conventional H-bridgecascaded multilevel inverter in [12] and [20] that are

considered by3

R and4

R , respectively. In [15-17] three

other symmetric cascaded multilevel inverters have been

presented. These inverters are shown by5 7

R R ,

respectively. The other cascaded multilevel inverter withtwo different algorithms has been presented in [19]. This

inverter with its algorithms is presented by8

R and9

R ,

respectively. Another symmetric cascaded multilevelinverter that has been presented in [18] is considered by

10 R in this comparison. Fig. 3 indicates all of the above-

mentioned cascaded multilevel inverters.

(a) (b) (c)

(d) (e)

(f) (g)

Fig. 3. The cascaded multilevel inverters; (a) conventional cascaded

multilevel inverter 2 R for 1 2 n dcV V V V [14], 3 R for

1 2, 2dc n dcV V V V V [12], 4 R for

1 2, 3dc n dcV V V V V [20]; (b) presented topology in [17] 7 R

for 1 2 n dcV V V V ; (c) presented topology in [19] 8 R for

1 2 n dcV V V V , 9 R for 1 2, 2dc n dcV V V V V ; (d)

presented topology in [18] ( 10 R ); (e) presented topology in [16] 6 R for

1 2 n dcV V V V ; (f) presented topology in [15] 5 R for

1 2 n dcV V V V ; (g) presented topology in [13] 1 R for

1 2 n dcV V V V

Fig. 4 compares the number of IGBTs of the proposed

topology with the other above-mentioned cascaded

multilevel inverters. As it is obvious, the proposed inverterneeds lower number of IGBTs to generate a specific level.In addition, the fourth proposed algorithm has the best

performance between all of the proposed algorithms for thedeveloped cascaded inverter. However, in this comparison

the unidirectional power switches have been used in manyof the considered cascaded multilevel inverters. As

mentioned before, the number of used IGBts is equal to thenumber of power diodes. As a result, the number of

required power diodes in the fourth proposed algorithm ofthe developed topology is lower than other above-

mentioned inverters and their proposed algorithms.

Fig. 4. Variation of IGBT N versus level N

Fig. 5 indicates the comparison of the proposed cascaded

inverter with other above-mentioned topologies from thenumber of driver circuit point of view. As each switchrequires a separate driver circuit, the number of driver

circuit is equal to the number of power switches. Therefore,

this comparison is also indicates the number of required

power switches in the cascaded multilevel inverters. Asshown in Fig. 5, the number of driver circuit based on the

fourth proposed algorithm of the developed cascadedinverter is lower than other proposed algorithms for this

0 10 20 30 0 50 0 70 80 0 1 00

2 7 8, , R R R

1 R

9 R3 5 6

, R R R1

P

2 P 4

R

4 P

3 P

200

160

120

80

40

020 60 10040 80

IGBT N

level N

10 R

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inverter and other above-mentioned cascaded multilevel

inverters.

Fig. 5. Variation ofdriver N versus

level N

Fig. 6 compares the number of dc voltage sources of the proposed topology with the other above-mentioned

cascaded multilevel inverters. As it is obvious, the numberof required dc voltage sources in the developed cascaded

multilevel inverter is less than other presented multilevel

inverters in the literature. This difference will be higher

while the fourth proposed algorithm is considered todetermine the magnitude of dc voltage sources of the

proposed topology.

Fig. 6. Variation of source

N versuslevel

N

Fig. 7 compares the maximum amount of blocked voltage by power switches in the proposed topology with the other

above-mentioned cascaded multilevel inverters. It is pointed out that in this comparison

4 1 2, 3dc n dc R for V V V V V indicates other algorithms

for H-bridge cascaded multilevel inverters that is presentedin [20]. As it is obvious, this value in the proposed inverter

is less than other presented cascaded multilevel inverters

except the H-bridge cascaded multilevel inverter and

presented topologies by7

R and10

R . However, this is the

main disadvantage of the proposed cascaded inverter butthis inverter has different advantages in comparison to H-

bridge cascaded inverter and the presented topologies by

7 R and

10 R such as its required lower number of IGBTs,

driver circuits and dc voltage sources. It is point out that all

values are considered in per unit anddcV is used as the base

value in per unit system.

Fig. 7. Variation ofblock V versus

level N

As it is obvious from above comparisons, the proposeddeveloped cascaded multilevel inverter has best

performance between all of the above-mentioned multileveltopologies. Reduction in the number of required IGBts,

power diodes, driver circuit, dc voltage sources and the

amount of blocked voltage by power switches are

remarkable advantages of the proposed inverter that

obtained from comparisons. However, the maximum

amount of blocked voltage in the H-bridge cascaded

inverter and the presented inverter as 7 R is lower than this

value in the proposed cascaded inverter. These advantageslead to reduction in the installation space and total cost of

the inverter. These features will has most influence when

the fourth proposed algorithm is used to determine the

magnitude of dc voltage sources.Therefore, this inverter could be a suitable replacement of

the conventional cascaded multilevel inverters in many

applications such as drive and control of electricalmachines, connection of renewable sources, FACTS

devices etc.

IV. EXPERIMENTAL RESULTS

In order to clarify the correct performance of the developed

proposed inverter in generation a desired output voltagelevels, the experimental results have been used. The

number of required power electronic devices in the

proposed inverter is completely based on the selected

algorithm to determine the magnitude of dc voltage sourcesin generation specific number of output levels. For instance,

in order to generate minimum 49 levels at the output, the

numbers of required power switches and dc voltage sourcesand the maximum value of blocked voltage by switches

based on the first proposed algorithm are equal to

46 switch

N , 25 source

N , and 174block

V pu , while these

values based on the second proposed algorithm are equal to

31 switch

N , 16 source

N , and 187block

V pu . The third

proposed algorithm needs 21 switch

N , 10 source

N , and

731block V pu while the fourth proposed algorithm

requires the same number of power electronic devices but

its value of blocked voltage is 202block

V pu . It is

important to note that the proposed inverter based on thefourth algorithm this inverter is able to generate 59 levels at

the output. In this section, the investigations are done on a

cascaded multilevel inverter that is shown in Fig. 8. Thisinverter consists of two proposed basic units and one

additional series connected dc voltage sources that lead touse of seven numbers of dc voltage sources and twelve

unidirectional power switches. The first proposed algorithm

is considered to determine the magnitude of dc voltage

sources. In addition, the magnitude of dc voltage source is

considered 20dcV V . According to (5), this inverter is

able to generate 15 levels (seven positive levels, seven

negative levels and one zero level) with the maximum

amplitude of 140 V at the output. It is important to note thatthe used IGBTs on the prototype are BUP306D (with an

internal anti-parallel diode). The 89C52 microcontroller by

ATMEL Company has been used to generate all switching pattern. Each switch requires an isolated driver circuit. The

isolation can be provided using either pulse transformers or

opto-isolators. Opto-isolators can work in a wide range ofsignal pulse width, but a separate isolated power supply is

required for each switching device. The opto-isolator based

gate driver circuit has been used in prototype. In order to

switching, a determined data Table is used in offline. Thisswitching Table is supplied in the EPROM memory of the

microcontroller. By addressing the rows of the Table, the

0 10 2 0 30 0 50 0 70 80 90 100-5 0

0

500

0

5 0

0

5 0

0

5 0

0

80604020

3500

2500

1500

500

0 100

8 R6 R

9 R2 4 7, R R R

11 4 ,, P P R2 P

3 P

level N

[ ]block V pu

10 R

20

2 5 6 8 1 01, , , , R R R R R P

1 7, R R

2 P 3 9

, R R4

R3

P 4

P

0 20 8060 100level N 40

60

100

20

Source N

Drive N

level N

120

60 1008020 400

40

200

80

160

5 70

20

0

60

80

2 7, R R

1 R

10 R

3 6 8, , R R R

1 P

4 R

5 R

9 R

2 P

3 P

4 P

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information of the switches states are sent to the

microcontroller port. Therefore, there is no need to

sampling and the sampling frequency is not considered but

the reading frequency of the Table’s rows could be

regulated between 20kHz to 50kHz. As a result, to send theinformation of a period (at the main frequency of 50Hz)

with the time interval such as 40 sec , the rows of the

Table will be equal to 20000/40=500. It is obvious that inorder to send the information of the Table with 500 rows to

the output port, the high numbers of rows will be repeated.

In this condition, there is no problem because of the excitedcapacitance in the microcontroller. In all process of the

experimental performance, the load is assumed as a

resistive-inductive load ( ) R L with 70 R and

55 L mH . It is important to point out that the used control

method in this inverter is the fundamental control method.The main reason to select this control method is its low

switching frequency than other control methods that leads

to reduction in switching losses. Moreover, the calculations

of optimum switching angles to eliminate the selectiveharmonics and decrease the total harmonic distortion arenot the subject of this paper.

Fig. 8. Cascaded 15-level inverter based on the proposed basic unit

Fig. 9 shows the experimental results. As it is obvious fromthese figures, this inverter is only able to generate positive

levels at the output. Fig. 9(a) shows that the added dc

voltage source generates the minimum magnitude of outputlevels that is equal to lower value of used dc voltage

sources. Fig. 9(b) and Fig. 9(c) indicate that each unit

generates the output voltage levels of zero, 40V and 60V.

By adding an H-bridge, this inverter is able to generate all positive and negative levels at the output. Fig. 10 shows the

waveforms of load voltage and current. As shown in Fig.10, this inverter generates a step waveform with 15 levels

and maximum amplitude of 140 V. By comparing the

current and voltage waveforms, it is clear that the currentwaveform is near to ideal sinusoidal waveform and consists

of a phase shift in comparison to the load voltage. These

differences are because of resistive-inductive load featurethat used for proposed inverter. The resistive- inductive

load acts as a low pass filter.As mentioned, the used power switches on the developed

cascaded multilevel inverter are as unidirectional ones fromvoltage points of view, so in order to verify this fact the

voltage on switches1

S ,1,1

S ,2,1

S ,3,1

S and4,1

S of the first

proposed unit are indicated in Fig. 11, respectively. It is

noticeable that the waveforms of voltage across2

S and

5,1S are same asov and

,1ov , respectively. As shown in

these figures, the magnitude of the blocked voltages onswitches are either positive or zero and there is any

negative amount on them. This fact reconfirms the existingof unidirectional power switches in this topology.

The frequency of the final output is not exactly 50Hz

because a little delay is happened for selecting and sending

the information of each row in EPROM memory of the

microcontroller to the output port. The total delays for 500

rows lead to small difference between the output frequencyand the main frequency of 50Hz. It is important to note that

it is possible to get exactly the desired output frequency ifthe delay time of the microcontroller is considered in

calculations.

(a) (b)

(c) (d)

Fig. 9. Output voltage waveforms of each unit; (a)ov ; (b)

,1ov ; (c),2ov ;

(d)ov

Fig. 10 Waveforms of load voltage and current

(a) (b)

(c) (d)

(e)

Fig. 11. The voltage on switches; (a)1S ; (b)

1,1S ; (c)2,1S ; (d)

3,1S ; (e)

4,1S

V. CONCLUSION

In this paper, a new basic unit for cascaded multilevel

inverter is proposed. By series connection of several basic

units, a cascaded multilevel inverter is proposed that only

generates positive levels at the output. Therefore, a H-

2.5ms

10V

2.5ms

10V

2.5ms

10V

2.5ms

10V

10V

2.5 ms

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bridge is added to the proposed inverter to generate all

voltage levels. This inverter is called developed cascaded

multilevel inverter. In order to generate even and odd

voltage levels at the output, four different algorithms are

proposed to determine the magnitude of dc voltage sources.Then, several comparisons are done between the developed

proposed single-phase cascaded inverter and its proposedalgorithms with cascaded multilevel inverters that have

been proposed in literature. According to these

comparisons, the developed proposed cascaded topology

requires less number of IGBTs, power diodes, drivercircuits and dc voltage sources than other presentedcascaded topologies in literature. These features will be

remarkable while the fourth proposed algorithm is used forthe developed cascaded inverter. For instance, in order to

generate minimum 63 levels at the output, the developed

cascaded topology based on the fourth proposed algorithmneeds 19 numbers of power diodes, IGBTs and driver

circuits and 10 numbers of dc voltage sources. However,

the cascaded multilevel inverter that presented in [20]

requires 44 numbers of power diodes, IGBTs and drivercircuits and 11 numbers of dc voltage sources. Therefore,the developed proposed inverter has better performance and

needs minimum number of power electronic devices that

lead to reduction the installation space and total cost of theinverter. Finally, the accuracy performance of the

developed proposed single-phase cascaded multilevel

inverter in generation all voltage levels is verified by usingthe experimental results on a 15-level inverter.

REFERENCES

[1] E. Babaei, S. Alilu, and S. Laali, “A new general topology for

cascaded multilevel inverters with reduced number of components

based on developed H-bridge,” IEEE Trans. Ind. Electron., vol. 61,

no. 8, pp. 3932-3939, Aug. 2014.

[2] M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded

multilevel inverter using series connection of sub-multilevel

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[3] J.H. Kim, S.K. Sul, and P.N. Enjeti, “A carrier-based PWM methodwith optimum switching sequence for a multilevel four-leg voltage-

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methods,” International Review of Electrical Engineering (IREE) ,vol. 6, no. 2, pp. 522-528, March-April. 2011.

[12] E. Babaei and S.H. Hosseini, “Charge balance control methods for

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2007, Seoul, Korea, pp.74-79.

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[14] M. Manjrekar and T.A. Lipo, “A hybrid multilevel inverter

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[15] M. Farhadi Kangarlu, E. Babaei, and S. Laali, “Symmetric

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61.

Ebrahim Babaei (M’2010) was born in Ahar,

Iran, in 1970. He received his B.S. and M.S.

degrees in Electrical Engineering from the

Department of Engineering, University of Tabriz,

Tabriz, Iran, in 1992 and 2001, respectively,

graduating with first class honors. He received his

Ph.D. degree in Electrical Engineering from the

Department of Electrical and Computer

Engineering, University of Tabriz, in 2007. In

2004, he joined the Faculty of Electrical and

Computer Engineering, University of Tabriz. He was an Assistant

Professor from 2007 to 2011 and has been an Associate Professor since

2011. He is the author of more than 280 j ournal and conference papers. He

also holds 17 patents in the area of power electronics and has more

applications pending. Dr. Babaei has been the Editor-in-Chief of the

Journal of Electrical Engineering of the University of Tabriz, since 2013.

In 2013, he was the recipient of the Best Researcher Award from of the

University of Tabirz. His current research interests include the analysisand control of power electronic converters and their applications, power

system transients, and power system dynamics.

Sara Laali (SM’2012) was born in Tehran, Iran,in 1984. She received her B.S. degree in

Electronics Engineering from the Islamic Azad

University, Tabriz Branch, Tabriz, Iran, in 2008,and her M.S. degree in Electrical Engineering

from the Islamic Azad University, South Tehran

Branch, Tehran, Iran, in 2010. In 2010, she

joined the Department of El ectrical Engineering,Adiban Higher Education Institute, Garmsar,

Iran. She is presently pursuing her Ph.D. degree

in Electrical Engineering with the faculty ofElectrical and Computer Engineering, University of Tabriz, Tabriz, Iran.

Her current research interests include the analysis and control of power

electronic converters, multilevel converters, and FACTS devices.

Zahra Bayat was born in Zanjan, Iran, in 1983.

She received her B.S. and M.S. in Electrical

Engineering from the Department of Engineering,University of Zanjan, Iran in 2006 and Islamic

Azad University, Ahar Branch, Ahar, Iran in 2011,

respectively. She has been a Lecturer at Islamic

Azad University, Zanjan Branch, Zanjan, Iran. Her

current research interests include the analysis and

control of power electronic converters.

Documents

Babae i 2014