2.CMOS Transistor Theory -...

Digital IC 2: DeviceIntroduction

CMOS VLSI Design

2.CMOS Transistor Theory

Fu yuzhuo

School of microelectronics,SJTU

Digital IC 2: Device

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static conditions

• Velocity Saturation

• Dynamic Characteristics

• Nonideal I-V effects

Capacitance

• Any two conductors separated by an insulator

have capacitance

• Gate to channel capacitor is very important

• Creates channel charge necessary for

operation

• Source and drain have capacitance to body

• Across reverse-biased diodes

• Called diffusion capacitance because it is

associated with source/drain diffusion

Diffusion Capacitance

• Csb, Cdb

• Undesirable, called parasitic capacitance

• Capacitance depends on area and perimeter

• Use small diffusion nodes

• Comparable to Cg

for contacted diff

• ½ Cg for uncontacted

• Varies with process

Capacitance components

• MOS structure capacitances

• Overlap cap.

• Channel capacitances

• Gate-body cap.

• Gate-source cap.

• Gate-drain cap.

• Junction/diffusion capacitances

• Bottom-plate cap.

• Side-well cap.

CGDCGS

CSB CDBCGB

The Gate Capacitance

WCWxCCC odoxGDOGSO

Cross section

Gate oxide

Polysilicon gate

Top view

Gate-bulkoverlap

Source

Digital IC 2: Device7/41

Gate channel Capacitance

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Gate Capacitance

2WLCox

VDS /(VGS-VT)

CGCS = CGCDCGC B

Capacitance as a function of VGS

(with VDS = 0)Capacitance as a function of

the degree of saturation

Measuring the Gate Cap

2 1.52 1 2 0.5 0

103 102 16

VGS (V)

0.5 1 1.5 22 2

Diffusion Area Capacitance

Bottom

Side wall

Channel

SourceND

Channel-stop implantNA1

Substrate NA

)2( WLCC

PERIMETERCAREACCCC

SjswjLSW

jswjswbottomdiff

An example of Diffusion

Capacitance

• Cgc=WLCox=0.24*0.36*5.7=0.49fF

• Coverlap=2*Co*W=2*0.3*0.36=0.216fF

• Cdiff-s=WDs*Cj+(W+2Ds)Cjsw=

0.36*0.625*2+(0.36+0.625*2)*0.275=0.44fF

NMOS:tox=6nm,L=0.24um,W=0.36um,LD=LS=0.625um, COX=5.7X10-3F/m2,

CO=3X10-10F/m,Cj0=2X10-3F/m2, and Cjsw0=2.75X10-10F/m, determine the

zero-bias value of relevant capacitances

1F=1015fF

Detail Diffusion Capacitance

0jjs )ψ

V+(1C=C )

NNln(0.026=)

kT=ψ 2

j swM-

0jswjsw )ψ

V+(1C=C

Cdiff-s=WDs*Cjs+(W+2Ds)Cjsw

Junction capacitance comes from…

DAsiDj V

DAsiDj

DAsij V

012 Φ

Depletion-region charge

Maximum electric field

Depletion-region width

Zero-bias conditons

0Φ1Φ1

• AD=20unit2=20*0.081=0.162um2

• PD=10+4=14unit=14*0.09=1.26um

• Cdb(0)=0.162*0.98+1.26*0.22=

• Cdb(1.8)=0.162*0.98*(1+1.8/0.75)-0.36

+1.26*0.22*(1+1.8/0.75)-0.10

Another example

Calculate the diffusion parasitic Cdb of the drain of a unit-sized

contacted nMOS transistor in a 0.18um process when the drain is at 0

and at Vdd=1.8V, assume the substrate is grounded, the transistor

characteristic are Cj=0.98fF/um2,Mj=0.36, CJSW=0.22fF/um,MJSW=0.10,

and Ψ0=0.75V at room temperature

More detail Capacity

)()(jeq

lowhigh

lowjhighj

eq CKVV

DAsiDj V

DAsiDj

lowhigh

eq VVmVV

00 )()(

Cdiff-s=KeqWDs*Cjs+Keqsw(W+2Ds)Cjsw

Capacitance model

CGDCGS

CSB CDBCGB

DdiffDB

SdiffSB

GCDGDOGD

GCSGSOGS

The Transistor as a Switch

VGS VT

VGS = VDD

VDD/2 VDD

0.5 1 1.5 2 2.50

The resistance is inversely proportional to

the W/L ratio of the device

For Vdd>>Vt+Vdsat/2, the resistance

becomes independent of the supply voltage

Once the supply voltage approaches Vt,

the resistance dramatically increases

Draincontact

Polysilicon gate

VGS,eff

Source-Drain Resistance

DS RRW

,•Low-resisitivity material

•Careful layout

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static conditions

• Velocity Saturation

• Dynamic Characteristics

• Nonideal I-V effects

Nonideal characteristics

• Velocity saturation

• Channel length modulation

• Body effect

• Threshold Variations

• Parasitic Resistances

• Subthreshold Conduction

• Hot-carrier effects

• Latchup

• Process variations

Channel length modulation

• Increasing VDS decreases the effective channel length

• Λ is an empirical channel length, should not be confuse

with the symbol used in layout design rules

• Channel length modulation is very important to analog

designers because it reduces the gain of amplifiers, it is

generally unimportant for qualitatively understanding the

behavior of digital circuit

DSDD VII

• Body effect

• Latchup

Body effect

)Φ2-+V+Φ2-γ(+V=V FSBF0tt

Nln(60.02=)

kT±=Φ

qε2=qε2

An example of Body effect

)Φ2-V+Φ2-γ(+V=V FSBF0tt

Nln(60.02=)

kT±=Φ

F ±ox

qε2=qε2

If nominal threshold voltage of 0.4V and doping level of 8*1017cm-3, the

body is tied to ground with a substrate contact. how much does the

threshold change at room temperature if the source is at 1.1V instead of

0,note,ni= 1.45*1010cm-3

V46.0=ΦF

6.0=10*6

10*8*10*8.85*(11.7*)10*6.1(*2

10*8.85*3.9

10*40=γ 6±

1741-19-

68.0=)93.0-1.1+93.0(*6.0+4.0=Vt

• Body effect

• Latchup

Threshold Variations

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

drain-induced barrier lowering-DIBL

Hot-carrier effects

• Device dimensions have been scaled

down continuously, while power

supply and the operating voltages

have not scaled accordingly

• Electron become hot which lead to a

long-term reliability problem

• Body effect

• Latchup

Sub-Threshold Conduction

0.0 1.0 2.0 3.0VGS (V)

Subthreshold exponential region

Linear region

Sub-Threshold Conduction

0 0.5 1 1.5 2 2.510

VGS(V)

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

1 ,~ 0

S is DVGS for ID2/ID1 =10

• Body effect

• Junction Leakage

• Latchup

Junction leakage

• Is depends on doping levels and on the area and

perimeter of the diffusion region

• Vd is the diode voltage(Vsb and Vdb)

• Generally in the 0.1-0.01fA/um2

• With low threshold voltages, subthreshold

conduction far exceeds junction leakage

1)-(eI=I T

• Body effect

• Latchup

Latchup

External voltages can ring below GND or above VDD

Tunneling

• There is a finite probability that carriers will tunnel

through the gate oxide

• Gate leakage current flowing into the gate

• The probability of tunneling drops off exponentially with

oxide thickness

Temperature dependence• Carrier mobility decreases with temperature

• Magnitude of the threshold voltage decrease withtemperature

• Junction leakage increases with temperature

• Body effect

• Latchup

Process variations

• Variations in the process parameters

• Impurity concentration densities,Oxide

thicknesses,Diffusion depths

• Sheet resistances, threshold voltage

diverging.

• Variations in the dimensions of the

devices

• Deviations in the W/L ratios

• Tradeoff between economic and yield

Some questions

• Vt trend

• Low Vt? High Vt?

• Low for high speed, high for low leakage

• VDD

• High voltage result in fast transistor?

• velocity saturation limit

• Delay

• Two nMOS in series deliver half the current of a

single nMOS of the same width?

• Velocity saturation benefit

Summary of general MOSFET scaling trends

Is there life after CMOS?

outlook

• Copper has replaced aluminum as interconnect material

• Low-permittivity interlevel dielectrics are replacing

silicon dioxide

• High-permittivity gate dielectrics to replace silicon

dioxide

• Strained silicon and SiGe technology

• Metal gates bound to come back

• Silicon-on-insulator (SOI) technology

• The search for new device topologies

Copper has replaced aluminum

as interconnect material

The search for a lower-resistivity conductor and a lower-

permittivity interlevel dielectric has prompted industry to

replace Al and SiO2 with new materials

Copper has replaced aluminum

as interconnect material

measurements indicated that the effective resistance of Cu interconnect

was 30% to 45% lower than that of traditional Al alloys. Cu also supports

significantly higher current densities. In electromigration tests conducted by

IBM, reliability was found to improve by more than two orders of magnitude.

Low-permittivity interlevel dielectrics are

replacing silicon dioxide

Intel’s 65 nm process combined up to eight levels of copper interconnect

with a low-permittivity carbon-doped oxide (CDO) ILD (r = 2.9). Tungsten

plugs are used for contacts to poly and diffusion. Metal pitches increase

gradually from bottom to top for optimum density vs. performance.

High-permittivity gate dielectrics

to replace silicon dioxide• Intel reports that 45 nm MOSFETs with a Hafnium-

based oxide provide either a 25% increase in driveability

at the same subthreshold conduction or more than

fivefold reduction in leakage for the same drive current

when compared to 65 nm transistors with their

traditional gate stacks . At the same time, gate oxide

tunneling has been reduced by more than a factor of ten

A material of low permittivity is desirable for interlevel dielectrics where the lowest

possible parasitic capacitances are being sought. Exactly the opposite is true for the

gate dielectric in order to minimize gate leakage while maximizing MOSFET drivability

and, hence, the switching speed of logic circuits.

Strained silicon and SiGe

technology

Electron mobility in Si augments when the crystal lattice is subjected to tensile stress,

whereas compressive stress tends to improve hole mobility

Metal gates bound to come back

A number of undesirable phenomena are associated with polysilicon as a

gate material

Silicon-on-insulator (SOI)

technology• The inherent electrical insulation of MOSFETs does

away with the need for wells.

• No parasitic BJTs and, no exposure to latch-up.

• No need for body ties and, superior layout density.

• Reduced sensitivity to radiation effects and higher

operating temperatures.

• The poor thermal conductivity of the insulating layer

impedes heat removal.

New devicesIn a planar double-gate device (DG-MOSFET), a horizontal inversion channel is

sandwiched between a pair of electrically connected gate electrodes in such a way as

to steer the channel from both sides at the same time

• The search for better semiconductor

materials

• Vertical integration

The search for new device

topologies• Non-CMOS data storage

• Phase-change RAM (PRAM)

• Ferroelectric RAM (FeRAM)

• Magnetic RAM (MRAM)

The search for new device topologies

____Non-CMOS data processing• Carbon nanotubes

• Philip G. Collins and Phaedon Avouris. Nanotubes for

Electronics. Scientific American, 283(48):38–45, December

• Nanojunctions

• Yu Huang et al. Logic Gates and Computation from Assembled

Nanowire Building Blocks. Science, 294(5545):1313–1317,

November 9, 2001.

• Molecular electronics

• A. J. Heinrich, C. P. Lutz, J. A. Gupta, and D. M. Eigler.

Molecule Cascades. Science,298(5597):1381–1387, November

2002. Carbon monoxide, two-input sorter, molecular electronics.

• Crossbar logic

• Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams.

Crossbar Nanocomputers. Scientific American, 293(5):50–55,

November 2005.54/41

The search for new device topologies

____Non-CMOS data processing

• Magnetic flux quantum device

• Darren K. Brock, Elie K. Track, and John M. Rowell.

Superconductor ICs: the 100-GHz second generation. IEEE

Spectrum, 37(12):40–46, September 2000.

• Quantum cellular arrays

• John Baliga. QCA Devices may take over when CMOS is done.

Semiconductor International, 22(12):48, October 1999.

• Quantum devices

• Ralph Cavin and Victor Zhirnov. Generic device abstractions for

information processing technologies. Solid-State Electronics,

50(4):520–526, 2006.

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