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Page 1: Verilog HDL (Behavioral Modeling)

Verilog HDLVerilog HDL(Behavioral Modeling)(Behavioral Modeling)

Bilal Saqib

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Behavioral ModelingBehavioral Modeling

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Structured ProceduresStructured Procedures

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Procedural BlocksProcedural Blocks

Procedural Blocks are constructed from the following components.◦Procedural Assignment Statements◦High-Level Constructs

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Procedural AssignmentsProcedural Assignments

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Procedural Execution ControlProcedural Execution Control

Execution of Procedural Blocks can be specified in different ways◦Simple Delays: #<delay>

Specify delay before and after execution for a number of time steps.

◦Edge-Sensitive Controls: always @ (<edge><signal>) Execution occurs only at a signal edge. Optional

keywords “posedge” or “negedge” can be used to specify signal edge for execution.

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NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments

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NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments

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Conditional Statements: if elseConditional Statements: if else

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Conditional Statements: caseConditional Statements: case

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casex and casezcasex and casez

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Looping Statements: repeat

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Looping Statements: while

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Looping Statements: forever

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Looping Statements: for


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