VLSI ReVisited: From Analog to Digital VLSI ReVisited: From Analog to Digital Online Employability Enhancement
VLSI ReVisited: From Analog to Digital VLSI ReVisited: From Analog to Digital Online Employability Enhancement

VLSI ReVisited: From Analog to Digital VLSI ReVisited: From Analog to Digital Online Employability Enhancement

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  • INDRAPRASTHA INSTITUTE of INFORMATION TECHNOLOGY DELHI (A State University established by Government of NCT of Delhi)

    Okhla Industrial Estate, Phase-III, New Delhi-110020, India. ·T +91 11 2690 7400-7404 ·F +91 11 2690 7405 ·www.iiitd.ac.in

    ֍ Domain Experts ֍

    Prof. G. S. Visweswaran

    Visiting Faculty, IIITD

    PhD, IIT Kanpur (1980)

    Retired Professor,

    EE, IIT Delhi (2015)

    Prof. S. S. Jamuar

    Visiting Faculty, IIITD

    PhD, IIT Kanpur (1977)

    Faculty at IIT Delhi, IIT

    Dhanbad and Malaysia

    (UPM, UM and UNIMAP)

    Dr. Anuj Grover

    Associate Professor, IIITD

    PhD, IIT Delhi (2015)

    20+ years of experience with

    STMicroelectronics

    Dr. Sujay Deb

    Associate Professor, IIITD

    PhD, WSU, USA (2012)

    Faculty at ECE, IIIT Delhi

    since 2012

    Dr. Sumit J. Darak Associate Professor, IIITD

    PhD, NTU Singapore (2013)

    Faculty at ECE, IIIT Delhi,

    since 2015 and 5G Consultant

    at VVDN Technologies

    VLSI ReVisited: From Analog to Digital

    Online Employability Enhancement Program

    4 Weeks (July 20 - Aug. 14)

    60 Online Teaching Hours

    60 Take-home Assignment Hours

    Hands-on Sessions every week

    Experts over 5-40 years of experience

    1-Month free access to recorded lectures

    ⧕⧕ Course Objectives ⧔⧔

    Design operational amplifier using CMOS

    Design low power high speed digital circuits and memory

    Hardware and software optimization using Gem5 Simulator

    Verilog-based end-to-end Image Processing

    Student Faculty Industry

    Early Bird: June 30/First 50 participants INR 3500 + GST INR 6000 + GST INR 12000 + GST

    Regular: After Early Bird Deadline INR 5000 + GST INR 8000 + GST INR 15000 + GST

    One Week Registration Charges INR 1500 + GST INR 3000 + GST INR 5000 + GST

    Group Discount: ֍ 5% (Group size = 3) ֍ 10% (Group size = 4) ֍ 15% (Group size = 5 or more) ֍

    Contact Email: alg2arch@iiitd.ac.in GST: +18%

    ֍ ֍ Registration Link (Last Date: July 15, 2020) ֍ ֍ ONLY 100 Seats

    mailto:alg2arch@iiitd.ac.in?subject=Regarding%20VLSI%20ReVisited%20Program https://forms.gle/uH3r9E9Tot45GNDK6

  • INDRAPRASTHA INSTITUTE of INFORMATION TECHNOLOGY DELHI (A State University established by Government of NCT of Delhi)

    Okhla Industrial Estate, Phase-III, New Delhi-110020, India. ·T +91 11 2690 7400-7404 ·F +91 11 2690 7405 ·www.iiitd.ac.in

    Week and Date Domain Day Topics Learning Outcomes

    Week 1

    July 20-25, 2020

    10am - 1pm

    Analog IC Design

    Prof. G. S. Visweswaran

    Prof. S. S. Jamuar

    Day 1 (July 20) Basics of MOS Transistors • In depth understanding of CMOS circuits.

    • In depth understanding of Current Mirrors

    and their important role.

    • Ability to Design an Operational Amplifier

    to fulfil given specifications

    Day 2 (July 21) Basic amplifier and frequency response

    Day 3 (July 22) Current Mirrors

    Day 4 (July 23) Differential Amplifiers

    Day 5 (July 24) Operational Amplifiers

    Week 2

    July 29-Aug. 3,2020

    10am - 1pm

    Digital VLSI and

    Memory Design

    Dr. Anuj Grover

    Day 6 (July 27) VLSI Technology • Ability to choose design style to meet

    Power-Performance-Area (PPA)

    specification

    • Ability to design low power and high speed

    digital circuits

    • Ability to evaluate Memory Circuits

    Day 7 (July 28) Logic Design Style–Pass Transistor, Static &

    Dynamic Logic

    Day 8 (July 29) Logical Effort

    Day 9 (July 30) Sequential Circuits

    Day 10 (July 31) Memory Circuits

    Week 3

    Aug. 3-7, 2020

    10am - 1pm

    Computer

    Architecture and

    System-on-Chip

    Dr. Sujay Deb

    Day 11 (Aug. 3) Introduction to Computer Architecture • In-depth understanding of superscalar

    architectures and ISA

    • Introduction to Gem5 simulator

    • Evaluation of hardware and software

    optimization techniques using Gem5

    Day 12 (Aug. 4) In-depth study of pipelining and hazards

    Day 13 (Aug. 5) Superscalar architectures

    Day 14 (Aug. 6) Processor memory subsystem

    Day 15 (Aug. 7) Multi-core SoCs and research directions

    Week 4

    Aug. 10-14, 2020

    10am - 1pm

    Digital System Design

    using Verilog

    Dr. Sumit J Darak

    Day 16 (Aug. 10) Finite State Machine (FSM) • In-depth Verilog understanding

    • Complete end-to-end image processing

    • C++ to Verilog via HLS

    Day 17 (Aug. 11) AXI Protocol

    Day 18 (Aug. 12) Image Processing (Sobel Filtering)

    Day 19 (Aug. 13) High Level Synthesis (HLS)

    Day 20 (Aug. 14) Image Processing via HLS

    Online Employability Enhancement Program

    VLSI ReVisited: From Analog to Digital

    ֍ ֍ Registration Link (Last Date: July 15, 2020) ֍ ֍

    https://forms.gle/uH3r9E9Tot45GNDK6

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