Sixth Semester B.E. Degree Examination, Dec.2013 lJan.Z0l4Analog and Mixed Mode VLSI Design
Time: 3 hrs. Max. Marks:100Note: Answer FIVE full questions, selecting atleast TWO questions from eoch part.
PART _ ABriefly explain the ADC specifications. (06 Marks)Draw the waveforms of sample and hold, track and hold and show the typical errorsassociated with S/H in hold mode and sample mode with reasons. (08 Marks)
c. A digitally progralnmable signal generator uses a 14 bit DAC, with a 10V reference togeneiate a DC output voltage. What is the smallest incremental change ilt the output that canoccur? What is the DAC's fullscale value? What is its accuracy? (06 Marks)
and disucss the accuracy(08 Marks)
Explain with neat block diagram th working of 4 bit, two step flash ADC, make a tablelisting the MSB's, Vr, Vz, V: and LSB'S fdr V6 : 9V and 2V. Assume VnEp : 16V. (08 Marks)For a charge scaling DAC, obtain the expression for lINLl.u, and lDNLl,u". (04 Marks)Define nonlinear analog circuits with an example, (02 Marks)Draw the basic block of comparator and explain pre-amplification and decision circuits of
diagram, explain multiplier using(08 Marks)
5 a. Define SNR, effective number of bits and clock jitter in mixed signal circuits qualitatively.
b. Explain" accumulate and dump circuit used for decimation(06 Marks)frequency(08 Marks)(06 Marks)
Define polycide, silicide, salicide and conductivity modulati (08 Marks)Explaintrue signal phase clocking (TSPC). Using TSPC, explaBring out the difference between normal CMOS process flowflow.
. (08 Marks)