VLSI Design Adder DesignAdder Design...  VLSI Design Adder DesignAdder Design ... Inversion Property

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  • VLSI Design

    Adder DesignAdder Design

    ECE 4121 VLSI DEsign.1

    [Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

  • Major Components of a Computer

    Processor D iProcessor

    Control

    Devices

    ControlMemory Input

    Datapath Output

    ECE 4121 VLSI DEsign.2

  • A Generic Digital Processor

    MEMORYMEMORY

    CONTROLOU

    TPU

    T

    CONTROL

    INPU

    T-O

    DATAPATH

    ECE 4121 VLSI DEsign.3

  • Basic Building Blocks

    DatapathExecution units

    - Adder multiplier divider shifter etc- Adder, multiplier, divider, shifter, etc.Register file and pipeline registersMultiplexers, decoders

    ControlFinite state machines (PLA, ROM, random logic)

    InterconnectSwitches, arbiters, buses

    MemoryCaches (SRAMs), TLBs, DRAMs, buffers

    ECE 4121 VLSI DEsign.4

  • Bit-Sliced Design

    Control

    Bit 3

    Bit 2

    ster

    der

    ter

    plex

    er

    ta-I

    n

    a-O

    ut

    Bit 1

    Bit 0

    Reg

    i

    Add

    Shift

    Mul

    tipDat

    Dat

    a

    Til id ti l i l t

    ECE 4121 VLSI DEsign.5

    Tile identical processing elements

  • Bit-Sliced Design

    Control

    Bit 3

    Bit 2

    ster

    der

    ter

    plex

    er

    ta-I

    n

    a-O

    ut

    Bit 1

    Bit 0

    Reg

    i

    Add

    Shift

    Mul

    tipDat

    Dat

    a

    Til id ti l i l t

    ECE 4121 VLSI DEsign.6

    Tile identical processing elements

  • The 1-bit Binary AdderCi A B C C S carry status

    1-bit Full Adder

    AS

    Cin A B Cin Cout S carry status0 0 0 0 0 kill0 0 1 0 1 kill0 1 0 0 1 propagateAdder

    (FA)BS 0 1 0 0 1 propagate

    0 1 1 1 0 propagate1 0 0 0 1 propagate1 0 1 1 0 propagate

    C

    S = A B C

    p p g1 1 0 1 0 generate1 1 1 1 1 generate

    Cout

    G = ABP A B = P CS = A B Cin

    Cout = AB + ACin + BCin (majority function)P = A BK = !A !B

    = P Cin

    = G + PCin

    How can we use it to build a 64-bit adder?

    How can we modify it easily to build an adder/subtractor?

    ECE 4121 VLSI DEsign.7

    How can we make it better (faster, lower power, smaller)?

  • One-Bit Full Adder: Share LogicAn observation

    Almost always, sum = NOT carry

    Cin A B Sum Cout0 0 0 0 0

    i l d

    0 0 1 1 00 1 0 1 0

    includes 111 0 1 1 0 11 0 0 1 01 0 1 0 1Sum A B Cin + 1 0 1 0 11 1 0 0 11 1 1 1 1

    Sum = A.B.Cin +(A+B+Cin).Cout

    excludes 000

    1 1 1 1 1

    ECE 4121 VLSI DEsign.8

  • FA Gate Level Implementations

    A B CinA B Cin

    t1 t0t2 t0

    t1t2

    CoutS

    Cout

    S

    ECE 4121 VLSI DEsign.9

    S

  • Ripple Carry Adder (RCA)

    A0 B0A1 B1A2 B2A3 B3

    C0=CinFAFAFAFACout=C4

    S0S1S2S3

    Tadder TFA(A,BCout) + (N-2)TFA(CinCout) + TFA(CinS)

    t N 1( )t t+

    T = O(N) worst case delayReal Goal: Make the fastest possible carry path

    tadder N 1( )tcarry tsum+

    ECE 4121 VLSI DEsign.10

    Real Goal: Make the fastest possible carry path

  • Complimentary Static CMOS Full Adder

    VDDVDD

    VDD

    A B

    B

    Ci

    A

    BA

    VDDCi

    S

    X

    B

    A

    Ci ACi

    B

    VDD

    SCi A

    BBAA B Ci

    Ci

    A

    Co B

    Cout = AB + BCin + ACin SUM = ABC + !C (A + B + C )

    28 Transistorsout in in

    = AB + Cin(B + A) SUM = ABCin + !COUT(A + B + Cin)

    ECE 4121 VLSI DEsign.11

  • Inversion PropertyInverting all inputs to a FA results in inverted values for

    A BA B

    Inverting all inputs to a FA results in inverted values for all outputs

    CFACFAC C

    S

    CinFACout

    S

    FACout Cin

    SS

    !Cout (A, B, Cin) = Cout (!A, !B, !Cin)

    !S (A, B, Cin) = S(!A, !B, !Cin)

    ECE 4121 VLSI DEsign.12

    !Cout (A, B, Cin) Cout (!A, !B, !Cin)

  • One-Bit Full Adder: Inverted InputsAn observation

    Invert inputs =>outputs invert

    Cin A B Sum Cout0 0 0 0 00 0 1 1 00 0 1 1 00 1 0 1 00 1 1 0 1FA 0 1 1 0 11 0 0 1 01 0 1 0 1

    FA

    Exploit this property:Get rid of the inverter on the carry critical path

    1 1 0 0 11 1 1 1 1

    carry critical path

    ECE 4121 VLSI DEsign.13

  • Exploiting the Inversion Property

    A0 B0A1 B1A2 B2A3 B3

    C0=CinFAFAFAFACout=C4

    S0S1S2S3regular cellinverted cell regular cellinverted cell

    Minimizes the critical path (the carry chain) by eliminating inverters between the FAs (will need toeliminating inverters between the FAs (will need to increase the transistor sizing on the carry chain portion of the mirror adder).

    ECE 4121 VLSI DEsign.14

  • Ripple Carry Adder: Inverting Property

    A1

    B1

    C2

    A0

    B0

    C1

    A2

    B2

    C

    A3

    B3

    C4 C2C0

    C1C3. . . FAC4 FA FAFA

    S1

    S0

    S2

    S3

    FA is similar to FA, but with no inverters on the outputsMuch faster (1-stage)Disadvantage: not regular data path

    ECE 4121 VLSI DEsign.15

  • Mirror Adder 24+4 transistors

    B B BB

    A A ACin

    24+4 transistors

    kill888

    6

    6

    444

    A

    A

    CinCin

    !Cout !S

    kill0-propagate88 6

    6

    4

    B B BA

    A

    A A

    Cin

    Cin

    generate1-propagate

    4 4

    4 4

    4 2 2 23

    32

    B

    C = AB + BC + AC SUM = ABC + !C (A + B + C )

    3

    Cout = AB + BCin + ACin= AB + Cin(B + A)

    SUM = ABCin + !COUT(A + B + Cin)

    Sizing: Each input in the carry circuit has a logical effort of 2 so the optimal fan-out for each is also 2. Since !Cout drives 2 internal and 2

    ECE 4121 VLSI DEsign.16

    optimal fan out for each is also 2. Since !Cout drives 2 internal and 2 inverter transistor gates (to form Cin for the nms bit adder) should oversize the carry circuit. PMOS/NMOS ratio of 2.

  • Mirror Adder FeaturesThe NMOS and PMOS chains are completelyThe NMOS and PMOS chains are completely symmetrical with a maximum of two series transistors in the carry circuitry, guaranteeing identical rise and fall transitions if the NMOS and PMOS devices are properlytransitions if the NMOS and PMOS devices are properly sized.

    When laying out the cell the most critical issue is theWhen laying out the cell, the most critical issue is the minimization of the capacitances at node !Cout (four diffusion capacitances, two internal gate capacitances, and two inverter gate capacitances) Shared diffusionsand two inverter gate capacitances). Shared diffusions can reduce the stack node capacitances.

    The transistors connected to Cin are placed closest to the in poutput.

    Only the transistors in the carry stage have to be

    ECE 4121 VLSI DEsign.17

    optimized for optimal speed. All transistors in the sum stage can be minimal size.

  • A 64-bit Adder/Subtractordd/ bt

    1-bit FA S0

    C0=CinRipple Carry Adder (RCA) built out of 64 FAs A0

    B

    add/subt

    C11-bit FA S1

    Subtraction complement all subtrahend bits (xor gates) and set the low

    B0

    A1

    BC2

    1-bit FA S2

    gates) and set the low order carry-in

    RCA

    B1

    A2

    B C3

    C

    . . .advantage: simple logic, so small (low cost)

    B2

    1-bit FA S63

    C63disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption)

    A63

    B63

    ECE 4121 VLSI DEsign.18

    C64=Coutconsumption) B63

  • Carry-Lookahead Adder: IdeaNew look: carry propagation

    Idea:Try to predict Ck earlier than Tc*kInstead of passing through k stages, compute Ckseparately using 1-stage CMOS logicseparately using 1 stage CMOS logic

    Carry propagation: an example

    Bit position

    Carry

    7 6 5 4 3 2 1 0

    1 0 0 1 1 1 1 A B

    0 1 0 0 1 1 0 1 +0 1 0 0 0 1 1 1

    ECE 4121 VLSI DEsign.19

    Sum 1 0 0 1 0 1 0 0

  • Carry-Lookahead Adder (CLA): One Bit

    (kill)

    What happens to thepropagating carry inbit position k?

    0 0 0A B Cin Cout

    0-propagate kill

    (kill)(propagate)(propagate)

    0 0 - 00 1 C C1 0 C C(propagate)

    (generate)1 0 C C1 1 - 1A B A

    CB

    BCout

    p = A+B (or A B)

    A B AB p = A+B (or A B)

    g = A.B

    ECE 4121 VLSI DEsign.20

    1-propagate generate [Rab96] p391

  • CLA: Propagation Equationsf CIf C4=1, then either:

    g3 generated at bit pos 3g2.p3 generated at bit pos 2, propagated 3g2.p3 generated at bit pos 2, propagated 3g1.p2.p3 generated at bit pos 1, propagated 2,3g0.p1.p2.p3 generated at bit pos 0, propagated 1,2,3C i d 0 1 2 3Cin.p0.p1.p2.p3 input carry, propagated 0,1,2,3

    C4 = g3+ g2.p3 + g1.p2.p3 + g0.p1.p2.p3 + Cin.p0.p1.p2.p3

    Implement Implement CC44 as a oneas a one--stage CMOS logicstage CMOS logicdelay=1 (or is it?)delay=1 (or is it?)

    ECE 4121 VLSI DEsign.21

  • CLA: Static Logic Implementation

    p1.g2.g3 C4

    gg3d

    e qo

    gg1g2e

    fh s

    rq

    C

    g0

    C4

    hj

    s

    tp0p

    Cink

    l

    tu

    p g C

    p1p2p3

    lm

    n

    vwx

    ECE 4121 VLSI DEsign.22

    p3.g2 C4p3 nx