EE466: VLSI Design Lecture 13: Adders. CMOS VLSI Design11: AddersSlide 2 Outline ï± Single-bit Addition ï± Carry-Ripple Adder ï± Carry-Skip Adder ï± Carry-Lookahead

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Text of EE466: VLSI Design Lecture 13: Adders. CMOS VLSI Design11: AddersSlide 2 Outline ï±...

PowerPoint PresentationGenerate: Cout = 1 independent of C
G =
K =
Generate: Cout = 1 independent of C
G = A • B
Propagate: Cout = C
P = A B
K = ~A • ~B
11: Adders
Critical path is usually C to Cout in ripple adder
11: Adders
Use wide transistors on critical path
Eliminate output inverters
11: Adders
Used in very fast multipliers
11: Adders
11: Adders
Critical path goes from Cin to Cout
Design full adder to have fast carry delay
11: Adders
Built from minority + inverter
11: Adders
Base case
Base case
Carry-skip allows carry to skip over groups of n bits
Decision based on n-bit propagate signal
11: Adders
11: Adders
11: Adders
Uses higher-valency cells with more than two inputs.
11: Adders
Precompute two possible outputs for X = 0, 1
Select proper output when X arrives
Carry-select adder precomputes n-bit sums
For both possible carries into n-bit group
11: Adders
11: Adders
11: Adders
Recursive lookahead gives O(log N) delay
Many variations on tree adders
11: Adders
L = log N logic levels
Fanout never exceeding 2
Logic levels: L + l
l + f + t = L-1
11: Adders
Architecture
Classification