Verilog HDL (Behavioral Modeling)

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Verilog HDL (Behavioral Modeling). Bilal Saqib. Behavioral Modeling. Structured Procedures. A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0. In One Module. - PowerPoint PPT Presentation

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  • Verilog HDL(Behavioral Modeling)Bilal Saqib

  • Behavioral Modeling

  • Structured Procedures

  • In One Module

    A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0.

  • Initial statementAn initial statement executes only once and begins its execution at start of simulation which is at time 0.

    Syntax :initial[timing_control] procedural_statement

  • Always statementAn always statement executes repeatedly and also begins its execution at start of simulation which is at time 0.Syntax :always [timing_control] procedural_statement

  • where a procedural_statement is one of :procedural_assignment ( blocking or non_blocking)procedural_continuous _assignment conditional_statementcase_statementloop_statementwait_statementdisable_statementevent_triggersequential_blockparallel_blocktask_enable (user

  • Procedural BlocksProcedural Blocks are constructed from the following components.Procedural Assignment StatementsHigh-Level Constructs

  • Procedural Assignments

  • Procedural Execution ControlExecution of Procedural Blocks can be specified in different waysSimple Delays: #Specify delay before and after execution for a number of time steps.Edge-Sensitive Controls: always @ ()Execution occurs only at a signal edge. Optional keywords posedge or negedge can be used to specify signal edge for execution.

  • NonBlocking v Blocking Assignments

  • NonBlocking v Blocking Assignments

  • Continuous assignment vs Procedural assignmentProcedural assignment Occurs inside an always statement or an initial statement.Execution is with respect to other statements surrounding it.Drives registers.Uses = or < = assignment symbol.No assign keyword Continuous assignment Occurs within a module.Executes concurrently with other statements ; executes whenever there is a exchange of value in an operand on its right-hand side.Drives nets.Uses = assignment symbol.Uses assign keyword

  • Block statementsA block statement provides a mechanism to group two or more statements to act syntactically like a single statement. There are two kinds of blocks in Verilog HDL. These are :Sequential block ( beginend ) : Statements are executed sequentially in the given order.Parallel block ( fork join ) : Statements in this block execute concurrently.

  • Sequential blockStatements in a sequential block execute in sequence.Syntax : begin [ : block_id { declarations} ] procedural_statement (s)end

  • Parallel blockStatements in a parallel block execute in concurrently.Syntax : fork [ : block_id { declarations} ] procedural_statement (s)join

  • Conditional Statements: if else

  • Conditional Statements: case

  • casex and casez

  • Looping Statements: repeat

  • Looping Statements: while

  • Looping Statements: forever

  • Looping Statements: for

  • Examplemodule FA_Seq (A , B , Cin , Sum, Cout) ; input A , B, Cin ; output Sum, Cout ; reg Sum, Cout ; reg T1, T2, T3 ; always@ ( A or B or Cin ) beginSum = ( A ^ B ) ^ Cin ;T1 = A & Cin ;T2 = B & Cin ;T3 = A & B;Cout = ( T1 | T2 ) | T3 ;endendmodule