Lab #2:

Transistor, Gate and IC level CMOS Design with Mentor Graphics

Date: 02/25/2013 - 03/04/2013

Bicky Shakya

Hokchhay Tann

Introduction

In this lab exercise, our ultimate goal is to design and implement a full adder device using Mentor Graphics software. This lab is divided into three sections, one for each week. For the first week, we master the basic commands for Linux Operating System and get familiar with industrial software Mentor Graphics. To achieve this goal, we design transistors for an inverter at Gate level and then simulate and verify the output signal with the input signal. In the second part of this lab, we are introduced to Mentor Graphics Design Architect and IC Station. Here, we implement logic gates, NOR, NAND, and Inverter at the gate level. In addition, we observe different layers of the chip and locate the locations of components such as metal wire, p-well and n-well. Using our designs from the second lab, we implement a 2-bit full-adder for the third part. In addition to gate level implementation, we add pad-frame with various inputs and outputs, which are then wired to pins on a MOSIS 40-pin chip.

Part I: Basics commands for Linux and getting familiar with Mentor Graphics

In this part, we are asked to practice some basic commands on the terminal windows and answer some practice questions. Below is our answer for the practice problem.

• Practice: working directories

1. Display currently directory [bshakya@mocha6 ~]$ pwd /home/bshakya 2. Change to the /etc directory [bshakya@mocha6 ~]$ cd /etc [bshakya@mocha6 etc]$ pwd /etc 3. Change to home directory using only three key presses [bshakya@mocha6 etc]$ cd [bshakya@mocha6 ~]$ pwd /home/bshakya 4. Change to the /boot/grub directory using only eleven key presses [bshakya@mocha6 ~]$ cd /boot/grub [bshakya@mocha6 grub]$ pwd /boot/grub 5. Go to the parent directory of the current directory [bshakya@mocha6 grub]$ cd .. [bshakya@mocha6 boot]$ pwd /boot 6. Go to the root directory [bshakya@mocha6 ~]$ cd [bshakya@mocha6 ~]$ pwd /home/bshakya 7. List the content of the root directory [bshakya@mocha6 ~]$ cd [bshakya@mocha6 ~]$ pwd /home/bshakya

[bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop mgc my_inverter 8. List a long listing of the root directory [bshakya@mocha6 ~]$ ls -l total 24 -rwxr-xr-x 1 bshakya 119056 282 Dec 10 14:09 acc.sh -rwxr-xr-x 1 bshakya 119056 712 Dec 10 14:09 adk_daic.sh -rwxr-xr-x 1 bshakya 119056 274 Dec 10 14:09 da.sh drwxr-xr-x 2 bshakya 119056 4096 Dec 10 14:42 Desktop drwxr-xr-x 5 bshakya 119056 4096 Dec 10 14:12 mgc drwxr-xr-x 3 bshakya 119056 4096 Dec 10 14:12 my_inverter 9. Stay where you are, and list the content of /etc [bshakya@mocha6 ~]$ ls /etc a2ps.cfg initlog.conf quotagrpadmins a2ps-site.cfg inittab quotatab acpi inputrc racoon adjtime iproute2 rc alchemist isdn rc0.d aliases issue rc1.d aliases.db issue.net rc2.d alsa java rc3.d alternatives jvm rc4.d anacrontab jvm-commmon rc5.d asound.state jwhois.conf rc6.d at.deny kde rc.d audisp kderc rc.local audit kdump.conf rc.sysinit NOTE: FOR SPACE SAVING PURPOSE, NOT ALL FILES ARE SHOWN HERE [bshakya@mocha6 ~]$ pwd /home/bshakya 10. Stay where you are, and list the contents of /bin and /sbin [bshakya@mocha6 ~]$ ls /bin; ls /sbin alsacard egrep mailx sort alsaunmute env mkdir stty arch ex mknod su awk false mktemp sync basename fgrep more tar bash fipscheck mount taskset cat fipshmac mountpoint tcptraceroute chgrp gawk mv tcsh chmod gettext netstat touch chown grep nice tracepath NOTE: FOR SPACE SAVING PURPOSE, NOT ALL FILES ARE SHOWN HERE [bshakya@mocha6 ~]$ pwd /home/bshakya 12. List all the files (including hidden files) in your home directory [bshakya@mocha6 ~]$ ls ~ acc.sh adk_daic.sh da.sh Desktop mgc my_inverter [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop mgc my_inverter [bshakya@mocha6 ~]$ ls -a

. da.sh .gnome .metacity .recently-used.xbel .. Desktop .gnome2 mgc .redhat acc.sh .dmrc .gnome2_private .mozilla .thumbnails adk_daic.sh .eggcups .gstreamer-0.10 .mstools .Trash .bash_logout .emacs .gtkrc my_inverter .xemacs .bash_profile .ezwave .gtkrc-1.2-gnome2 .nautilus .xsession-errors .bashrc .gconf .ICEauthority .qt .config .gconfd .kde .recently-used 13. List the files in /boot in a human readable format [bshakya@mocha6 ~]$ ls -h /boot config-2.6.18-128.7.1.el5 System.map config-2.6.18-128.el5 System.map-2.6.18-128.7.1.el5 config-2.6.18-164.2.1.el5 System.map-2.6.18-128.el5 grub System.map-2.6.18-164.2.1.el5 initrd-2.6.18-128.7.1.el5.img System.map-2.6.31.3 initrd-2.6.18-128.el5.img System.map-2.6.31.3.old initrd-2.6.18-164.2.1.el5.img vmlinuz initrd-2.6.31.3.img vmlinuz-2.6.18-128.7.1.el5 lost+found vmlinuz-2.6.18-128.el5 symvers-2.6.18-128.7.1.el5.gz vmlinuz-2.6.18-164.2.1.el5 symvers-2.6.18-128.el5.gz vmlinuz-2.6.31.3 symvers-2.6.18-164.2.1.el5.gz vmlinuz-2.6.31.3.old 14. Create a directory testdir in your home directory [bshakya@mocha6 ~]$ cd testdir [bshakya@mocha6 testdir]$ pwd /home/bshakya/testdir 15. Change to the /etc directory, stay here and create a directory newdir in your home directory [bshakya@mocha6 ~]$ cd /etc [bshakya@mocha6 etc]$ pwd /etc [bshakya@mocha6 etc]$ mkdir ~/newdir [bshakya@mocha6 /]$ cd ~ [bshakya@mocha6 ~]$ pwd /home/bshakya [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop mgc my_inverter newdir testdir 16. Create in one command the directories ~dir1/dir2/dir3 (dir3 is a subdirectory from dir2, and dir2 is a subdirectory from dir1) [bshakya@mocha6 ~]$ mkdir -p dir1/dir2/dir3 [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop dir1 mgc my_inverter newdir testdir [bshakya@mocha6 ~]$ cd dir1 [bshakya@mocha6 dir1]$ pwd /home/bshakya/dir1 [bshakya@mocha6 dir1]$ ls dir2 [bshakya@mocha6 dir1]$ cd dir2 [bshakya@mocha6 dir2]$ ls dir3

17. Remove the directory testdir [bshakya@mocha6 ~]$ rmdir testdir [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop dir1 mgc my_inverter newdir

• Practice: working with files

1) List the files in the /bin directory [bshakya@mocha6 ~]$ ls /bin alsacard dnsdomainname keyctl pgawk taskset alsaunmute doexec kill ping tcptraceroute arch domainname ksh ping6 tcsh awk dumpkeys ksh93 ps touch basename echo link pwd tracepath bash ed ln raw NOTE: FOR SPACE SAVING PURPOSE, NOT ALL FILES ARE SHOWN HERE 2) Display the type of file of /bin/cat, /etc/passwd and /usr/bin/passwd [[bshakya@mocha6 etc]$ cd /bin [bshakya@mocha6 bin]$ file cat cat: ELF 64-bit LSB executable, AMD x86-64, version 1 (SYSV), for GNU/Linux 2.6.9, dynamically linked (uses shared libs), for GNU/Linux 2.6.9, stripped [bshakya@mocha6 etc]$ cd /etc [bshakya@mocha6 etc]$ file passwd passwd: ASCII English text [bshakya@mocha6 etc]$ cd /usr/bin [bshakya@mocha6 bin]$ file passwd passwd: setuid ELF 64-bit LSB executable, AMD x86-64, version 1 (SYSV), for GNU/Linux 2.6.9, dynamically linked (uses shared libs), for GNU/Linux 2.6.9, stripped 3.a.) Download wolf.jpg and LinuxFun.pdf from http://linux-training.be (wget http://linux-training.be/files/studentfiles/wolf.jpg and wget http://linux-training.be/files/books/LinuxFun.pdf) [bshakya@mocha6 ~]$ wget http://linux-training.be/files/studentfiles/wolf.jpg http://linux-training.be/files/studentfiles/wolf.jpg Resolving linux-training.be... 188.93.155.87 Connecting to linux-training.be|188.93.155.87|:80... connected. HTTP request sent, awaiting response... 200 OK Length: 394589 (385K) [image/jpeg] Saving to: `wolf.jpg' 100%[===================================================>] 394,589 406K/s in 0.9s (406 KB/s) - `wolf.jpg' saved [394589/394589] [bshakya@mocha6 ~]$ wget http://linux-training.be/files/books/LinuxFun.pdf --2013-02-18 15:07:07-- http://linux-training.be/files/books/LinuxFun.pdf

Resolving linux-training.be... 188.93.155.87 Connecting to linux-training.be|188.93.155.87|:80... connected. HTTP request sent, awaiting response... 200 OK Length: 2475150 (2.4M) [application/pdf] Saving to: `LinuxFun.pdf' 100%[===================================================>] 2,475,150 569K/s in 4.5s (535 KB/s) - `LinuxFun.pdf' saved [2475150/2475150] 3.b.) Display the type of file of wolf.jpg and LinuxFun.pdf [bshakya@mocha6 ~]$ file wolf.jpg wolf.jpg: JPEG image data, JFIF standard 1.01 [bshakya@mocha6 ~]$ file LinuxFun.pdf LinuxFun.pdf: PDF document, version 1.4 3.c.) Rename wolf.jpg to wolf.pdf (use mv) [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop dir1 LinuxFun.pdf mgc my_inverter newdir wolf.jpg [bshakya@mocha6 ~]$ mv wolf.jpg wolf.pdf [bshakya@mocha6 ~]$ ls acc.sh adk_daic.sh da.sh Desktop dir1 LinuxFun.pdf mgc my_inverter newdir wolf.pdf 3.d.) Display the type of file of wolf.pdf and LinuxFun.pdf [bshakya@mocha6 ~]$ file wolf.pdf wolf.pdf: JPEG image data, JFIF standard 1.01 [bshakya@mocha6 ~]$ file LinuxFun.pdf LinuxFun.pdf: PDF document, version 1.4 4 and 5. Create a directory ~/touched and enter it. Create the files today.txt and yester.txt in touched [bshakya@mocha6 ~]$ pwd /home/bshakya [bshakya@mocha6 ~]$ mkdir ~/touched [bshakya@mocha6 ~]$ ls acc.sh da.sh dir1 mgc newdir wolf.pdf adk_daic.sh Desktop LinuxFun.pdf my_inverter touched [bshakya@mocha6 ~]$ cd touched [bshakya@mocha6 touched]$ pwd /home/bshakya/touched [bshakya@mocha6 touched]$ touch today.txt; touch yesterday.txt [bshakya@mocha6 touched]$ ls today.txt yesterday.txt 6. Change the date on yesterday.txt to match yesterday’s date [bshakya@mocha6 touched]$ ls -l total 0 -rw-r--r-- 1 bshakya 119056 0 Feb 18 15:15 today.txt -rw-r--r-- 1 bshakya 119056 0 Feb 18 15:15 yesterday.txt [bshakya@mocha6 touched]$ touch -t 201302170000 yesterday.txt [bshakya@mocha6 touched]$ ls -l total 0 -rw-r--r-- 1 bshakya 119056 0 Feb 18 15:15 today.txt

-rw-r--r-- 1 bshakya 119056 0 Feb 17 00:00 yesterday.txt 7. Copy yesterday.txt to copy.yesterday.txt [bshakya@mocha6 touched]$ cp yesterday.txt copy.yesterday.txt [bshakya@mocha6 touched]$ ls copy.yesterday.txt today.txt yesterday.txt 8. Rename copy.yesterday.txt to kim [bshakya@mocha6 touched]$ mv copy.yesterday.txt kim [bshakya@mocha6 touched]$ ls kim today.txt yesterday.txt 9. Create a directory called ~/testbackup and copy all files from ~/touched into it [bshakya@mocha6 ~]$ ls acc.sh da.sh dir1 mgc newdir touched adk_daic.sh Desktop LinuxFun.pdf my_inverter testbackup wolf.pdf [bshakya@mocha6 ~]$ cp touched/* testbackup [bshakya@mocha6 ~]$ cd testbackup [bshakya@mocha6 testbackup]$ ls kim today.txt yesterday.txt 10. Use one command to remove the directory ~/testbackup and all files in it [bshakya@mocha6 ~]$ rm -rf testbackup [bshakya@mocha6 ~]$ ls acc.sh da.sh dir1 mgc newdir wolf.pdf adk_daic.sh Desktop LinuxFun.pdf my_inverter touched

• Linux Basics and work with Mentor Graphics software

Procedure for designing and simulating an inverter:

1) Type pwd in the Terminal window to show the current working directory (make sure it shows the user’s home directory.

2) Type cp /home/lcheng/da.sh /home/htann to copy da.sh data into htann home directory. Type cp /home/lcheng/acc.sh /home/htann to copy acc.sh data into htann home directory. Type cp /home/lcheng/adk_daic.sh /home/htann to copy adk_daic.sh data into htann home directory.

3) To double check the content of the home directory, type ls in the terminal window. Make sure all the .sh files are in there.

4) Type mkdir my_inverter to create a new subdirectory in the home directory that stores all the data for inverter design.

5) Navigate to my_inverter directory by typing cd my_inverter. 6) Type mgcsetwd to set the working directory of Mentor Graphics to the current directory

(my_inverter). 7) Open the Design Architect software of Mentor Graphics by typing /home/htann/adk_daic.sh.

8) Click on the schematic icon on the session palette that resides within the right hand menu. Type

/home/htann/my_inverter/my_inverter in Component and click OK.

9) Click ADK IC Library icon on the session palette. Place 1 pmos, 1 nmos, 2 VDD, 1 in and 1 out terminals, 2 GND, 1 DC(V), and 1 capacitor in the schematic window

10) Wire the components are shown in figure 1.

Figure 1: Schematic of an inverter gate design using mentor graphic

11) Using key press shift + F7 to change the name of each pins to the corresponding name as shown in figure 1.

12) Using right click and property to change the value of the capacitance to 100fF, DC voltage source to 5V, and make sure the length and width of the pmos and nmos are the same as in figure 1.

13) Now go to File – Check Schematic to verify whether the design has any errors. If no error, the

proceed to the next step.

14) Now moving on to the simulation part of the design. Click on the green triangle on the left menu to go into simulation mode. In the pop-up window, select Analog/Mixed Signal as simulation type. Then click New Configuration. In the pop-up window, choose SPICE_Netlister for the configuration type, and enter a configuration name, such as my_inv. OK out of both windows.

15) Go to the Default Sim Palette on the right and choose Session – Netlister under setup. In the pop-up window, change default setting to GROUND to GND.

16) Go to the Default Sim Palette and choose Session – Environment under setup. Click on Run Simulation Only, then OK.

17) Go to the Default Sim Palette on the right and choose Lib/Temp/Inc under setup and enter the library path:

/usr/MentorGraphics/adk3_1/technology/ic/models/ami05.mod then click OK. 18) Go to the Default Sim Palette on the right and choose Analysis under setup. In the pop-up

window, choose Transient. Click setup and enter the values: Start time: 0N, end time: 200N, print time: 10N, max step: 5N. Click OK.

19) Click on the input net to select. Go to the Default Sim Palette on the right and choose Forces – Manager under setup. In the pop-up window, under Type, click on Independent – PULSE. Enter parameters for the pulse (Initial Value = 0, Pulsed Value = 5V, rise time, fall time = 1ns, pulse width = 50 ns, period = 100ns). Click N:VIN under Signals, and then click the enter force button (middle icon, upper right).

20) Click the green ADK Sim Palette button on the right. Use ctrl + left mouse click to select both input and output nodes. Click Probes. OK out.

21) Go to the ADK Sim Palette on the right and click Write under Netlist. On the bottom left, there should be a note showing Netlist has been written successfully.

22) Go to Default Sim Palette, look under Results – ASCII files – View Commands to determine whether the .PROBE statements are included or not. If they are not included, return to the ADK Sim Palette, select Commands, Edit and manually enter the following commands .PROBE Vin .PROBE Vout

23) Close and save the edited command file. 24) Go to the ADK Sim Palette on the right and click Run under Simulation. 25) Select the input and output nodes. Go to the ADK Sim Palette on the right and click X Probe –

Voltages – Default under Result. The simulation window will pop up as shown in figure 2. 26) Click End Sim button to end the simulation. 27) Change the capacitance to 1000fF, and restart the simulation. The new result is shown in figure 3.

• Simulation Results:

Figure 2: Simulation Result for the inverting circuit with 100fF capacitance

Figure 3: Simulation Result for inverting circuit with 1000fF capacitance • Discussion

From figure 2 and 3, we observe a significant difference in the response of the output signal to the change in the input signal. The rise time for the inverting circuit with 100fF capacitance has a output signal rise time of approximately 3ns whereas it is about 12ns for inverting circuit with 1000fF capacitance. The output fall times for the 100fF and 1000fF capacitance circuits are approximately 1ns and 4ns respectively. The difference in the result could be explained from the amount of charge in the capacitors that need to be discharge at each switching cycle. At every voltage level, the 1000fF capacitor could store up more charge than the 100fF capacitor from the equation: Q = CV, where Q is the amount of charge. Thus, with same strength transistors, it makes sense that the 1000fF takes longer to charge up and discharge at each switching cycle.

Part II: Linux and Transistor Level Design

In the second part of the lab, we explore the Mentor Graphics ADK package for investigation of the basic layout of several CMOS logic gate circuits. Three logic gate layouts were synthesized: the NOR gate (2 inputs), the NAND (3 inputs), and the NOT gate. The layouts were designed with the main aim of exploring the relationship between the logic gates and the geometry of the layout.

Step-by-Step Guide to Making a Layout in Mentor Graphics

1) Using the Terminal inside Red Hat Linux and the mkdir command, a new directory/folder ‘mydesignNOR2’ was created for the project. We then navigated to the newly created folder using the ‘cd’ command and then set it as the default working directory for Mentor using the mgcsetwd (complete path for design directory: /home/username/mydesignNOR2

2) ADK Design Architect was then invoked through the terminal (type in mentor adk_daic). 3) Inside DAIC, a new sheet (schematic) was created using File > Open > Schematic and was saved

as myNOR2 in the created directory ‘mydesignNOR2’. - The ‘ADK IC Library’ icon was selected in the session palette from which the ‘Standard

Cells’ option was selected. From there, the ‘Basic Logic Gates’ option was selected, under which ‘NOR02’ was selected in order to insert a 2-input NOR gate.

- From the same schematic window, two input ports and one output ports were added to the NOR gate schematic using the ‘Add Port In/Out’ option on the right. The individual components were then wired up together (right click => wire).

- Using the Shift+F7 hotkey (with the pointer above the label), the individual parts such as the gate and the ports were relabeled (2 inputs as A and B, and the output as Y).

- The created schematic was then checked for consistency using the File -> Check Schematic option and then saved.

- After creating the schematic, ADK_DAIC was closed off. Note: When reopening the schematic from DAIC (from File -> Open), the folder containing the schematic needs to be selected and not the file itself (causes directory problems later on).

Figure 4: Finished Schematic of a 2-Input Nor Gate in Mentor Graphics Design Architect

4) Creating a Viewpoint - To create a viewpoint, the command ‘mentor adk_dve mydesignNOR2’ was typed into the

terminal. A viewpoint has to be mandatorily made for each design (once per design). 5) Creating a layout

a. IC Station was then invoked by typing in ‘adk_ic.sh’ at the terminal. [IMAGE]

b. By going to MGC > Setup > Session, the Up-Down Tiling option was selected (all other settings left to default value).

c. To create a new cell, we clicked on Cell > Create on the palette menu on the left. In the Create Cell dialog box, the following parameters were entered. - Cell name: myNOR2

- Attach Library: $ADK/technology/ic/process/ami05

- Process: $ADK/technology/ic/process/ami05

- Connectivity : With connectivity (SDL, ICPlan, IC blocks)

- EDDM Schematic Viewpoint: /home/username/mydesign/myNOR2/layout

- Logic Loading Options: checked flat, leaving everything else as default

d. After that, the previously created logic/ schematic was opened using File > Logic > Menu (Browse to Folder with Schematic). The resulting window was seen to have a cell window on top of a separate window where the logic schematic would be visible.

e. Autofloorplanning the IC cell - In the upper layout window, the option ADK Edit > P&R was selected from the right

palette (right click). Then, ‘Autofp’ in the ‘Place and Route’ palette was selected (options left to default value and in the resulting dialog box, OK was clicked).

- A floor plan appeared in the cell window, where there were a series of boxes enclosed by solid bars along each edge. The boxes were an indication of where the cells would be organized. The solid edges indicated the edges of the cell where the physical ports would be placed.

Figure 5: Auto Floor Planning of the IC Cell

f. Autoplacing the Standard Cells - The option ‘StdCell’ under ‘Autoplace’ (in the Place and Route palette) was selected.

This brought up a dialog box whose values were all left to default. We then clicked on ‘OK’ to proceed.

- The cells were then place in the floor plan boxes previously generated. The auto placing algorithm places together the cells with shared connections.

Figure 6: Auto placing the Standard Cells in the Layout

g. Autoplacing Ports - This was achieved by selecting ‘Ports’ under ‘Autoplace’ in the ‘Place and Route’

palette (‘OK’ the resulting form).

6) Figure 7: Auto Placing the Ports

- The auto placed ports are mostly haphazard and need to be rerouted.

o From the palette menu, ‘All’ was selected from the ‘Auto route’ subsection. A submenu appeared where the following options were selected: Expert Options>Channel Over Cell Routing and OCR Options > (Step Size > 0.50) and (Operation Mode Type > Center Weighted). All the resulting forms were Ok’ed and auto routing began. The resulting cell looked as follows:

Figure 8: Auto routed Ports in Cell ‘myNOR2’

b. Overflows

Occasionally, when the design is too big, the ports might not be routed properly and overflows might occur in the design. To deal with overflows, we clicked on an empty space in the cell and in the resulting form, typed in ‘check over’. In the resulting dialog box, the options ‘All’ and then ‘OK’ were selected. All the overflow objects were then automatically selected (if any). From the ‘Place and Route’ palette’, ‘Overflow’ was then selected. If the response of ‘An object of type Overflow must be selected’ appeared, it meant that our design did not have any overflows (this was the case for our design). Otherwise, the overflows need to be routed in a similar way as mentioned above for auto routing the ports.

c. Finally, the resulting layout (cell) was saved using File > Cell > Save Cell > Current Context.

d. Viewing layers in IC Station To see the different IC layers, the following options were selected. - Choose ‘Select’ > ‘All’ > ‘Context Hierarchy Peek’. From the pop up menu, set the

level to ‘3’ and click on OK. Now, click on ‘Unselect All’. To view particular layers, go to ‘View Visible Layers’ from the upper menu bar and in the ‘Set Visible Layers’, click on the desired layers (here, for example, layers 41-51 were selected).

Figure 9: Layers 41-51 of the IC Design for myNOR2

e. To open IC Station, the design architect (da_ic.sh) was opened. From the right hand

palette, we clicked on ‘Open’ > ‘Cell’. In the cell name, the target folder was selected by browsing to open the layout. It was noted that the file (here, myNOR2) should never be selected for opening (just the directory), as it would mess up the directories.

6) Creating the Symbol If the cell is to be incorporated into some other design (suppose, a pad frame), a symbol needs to be created. The following steps were implemented:

i. Start the ADK Design Architect (adk_daic.sh) and open the cell’s schematic. ii. Click on ‘Miscellaneous’>’Generate Symbol’. In the resulting dialog box, leave

all the parameters to their default value and click on OK. iii. The resulting symbol appears to be a simple rectangle with input and output pins.

To place the name of the gates, click on ‘Edit’>’Add Graphics’>’Text’ and use the name of the file as the text. The name then needs to be placed in the symbol.

iv. By clicking on the ‘Check and Save’ option on the palette, the symbol is then finalized (errors about the properties not being on the interface can be ignored for now).

All of the steps mentioned above were then repeated to make the schematic and cell layout of a 3 input NAND gate and a NOT gate (inverter). The results are presented below in images.

Figure 10: Schematic of a 3-input NAND Gate

Figure 11: Cell Layout of the NAND Gate (2nd Picture with Layers 41-51 of the Layout)

Figure 12: Schematic of a NOT Gate

Figure 13: Cell Layout of the NOT Gate (2nd Picture with Layers 41-51 of the Layout)

To observe different levels of the design, we use the function View – Visible Layers to view different layers such as metal, p-well, and n-well. Below are some snapshots of different layers:

• NOR (2 inputs)

(a) (b) Figure 14. (a). Metal 1 Layer for NOR Gate (b). Metal 2 Layer for NAND Gate

(a) (b) Figure 15: (a). N Well and N Plus Select region (Non – Dashed) for NOR Gate (b). P Well and P Plus Select region (Non-Dashed) for NOR Gate

P Well

N W

ell

Active Layers

Active Layer

Polysilicon

Polysilicon

VIA VIA

VIA

P_Plus Select

N_Plus Select

P_Plus Select

N_Plus Select

Contact to Polysilicon Contact to Polysilicon

Active Layer

Active Layer

Active Layer

Figure 16. View

ing Layers of the 2 Input NO

R G

ate (Zoomed in)

Figure 17: Viewing Layers of the 2 Input NOR Gate

Legends:

A => layer: METAL2, net = A (INPUT) B => layer: METAL2, net = B (INPUT)

Y => layer: METAL2, net = Y (OUTPUT)

rule = METAL2, net = VDD rule = METAL2, net = VDD

B Y A

rule = METAL1, net = VDD

rule = METAL2, net = GND rule = METAL2, net = GND

rule = METAL2, net = GND

Polysilicon

• NAND (3 inputs)

(a) (b) Figure 18: (a) Metal 1 Layer for NAND Gate (b) P Well and P Plus Select for NAND Gate

(a) (b) Figure 19: (a) Metal 2 Layer for NAND Gate (b) N Well and N Plus Select for NAND Gate

Figure 20: View

ing Layers of the 3 Input NA

ND

Gate (Zoom

ed in)

N W

ell

P Well

Active Layer

N_Plus Select

P_Plus Select

Active Layer

Polysilicon Polysilicon

VIA VIA

VIA VIA

Contact Contact to Polysilicon

Contact to Polysilicon

Legends:

A => layer: METAL2, net = A (INPUT) B => layer: METAL2, net = B (INPUT)

C => layer: METAL2, net = C (INPUT) Y => layer: METAL2, net = Y (OUTPUT)

rule = METAL2, net = VDD rule = METAL2, net = VDD A Y C

B rule = METAL1, net = VDD

B

rule = METAL2, net = GND

rule = METAL2, net = GND rule = METAL2, net = GND

Figure 21: Viewing Layers of the 3 Input NAND Gate (Zoomed in)

• NOT gate

(a) (b) Figure 22: (a) Metal 1 Layer for NOT Gate (b) Metal 2 Layer Plus Select for NOT Gate

(a) (b) Figure 23: (a) N Well and P Well (b) N Well and P Well with N and P Plus Select for NOT Gate

Figure 24: Viewing Layers of the NOT Gate (Zoomed in)

Figure 25: Overview of the NOT Gate

Part III. Complete Full-Adder IC Chip Design :

Using the instructions used for the design of the inverter and gates in previous parts, we create a cell

through the terminal window. In the home directory, using command mkdir mydesign, a directory called

‘mydesign’ was created and it was set as a working directory using command mgcsetwd.

After setting the working directory to ‘mydesign’, the Design Architect software of Mentor Graphics was

opened using command mentor adk_daic. The schematic of a full-adder design was then created using

two XOR, two AND and one OR gate. For this Adder, we have three inputs A and B, with a carry in (Ci),

while the output is taken from S (sum) and carry out (Co). Inputs A and B are operands while Cin is a bit

carried in from the next less significant stage. Thus, output sum(S) is represented by logic S =(A ⊕ B)

⊕C, while the carry out (Cout) is represented by COUT = (A ● B ) +(CIN . ( A ⊕ B )). The design of the

full adder is given in figure below:

Figure 26: Full Adder Schematic in Design Architect

A symbol of above design was then generated using the instructions: miscellaneous >generate symbol.

The symbol was checked using command file>Check Symbol and it was saved using file>Save Symbol.

It was made sure that there was no error in the generated symbol.

The design viewpoint of the full-adder was then created through the terminal window using command

mentor adk_dve myFULLADDER. The IC station was then opened through the terminal using command

mentor adk_ic, where a new cell was created following the instructions used in the gate design. In order to

create a layout of the design, menu was updated through MGC>SETUP>SESSION by selecting Up

Down Tilling and leaving everything else at the default. A new cell was then created by going to

CELL>CREATE. In the create cell dialog box, following information was added:

1. Cell name: myFULLADDER 2. Attach Library: $ADK/technology/ic/process/ami05 3. Process: $ADK/technology/ic/process/ami05 4. Connectivity? : With connectivity (SDL, ICPlan, ICbloacks) 5. EDDM Schematic Viewpoint: /home/vbharam/mydesign/myFULLADDER/layout 6. Logic Loading Options: checked flat, leaving everything else as default

After clicking OK in the dialog box, the cell window with the schematic was popped out. The logic for the schematic was then loaded through FILE>LOGIC>OPEN.

The AutoFloorplan for the IC cell was then created by editing Autofloorplan Options through the right palette. In the Autofloorplan options, ‘Aspect Ratio Limis: Lower’ was set to 0.5 and ‘Compute Route Area Ratio’ was set to be computed automatically. The floorplan for the full-adder was placed in the cell window as shown below. In this floorplan, the boxes indicate the rows into which cells will be organized; while, the solid bars indicate edges of the cells along which physical ports will be placed.

Figure 27: Floorplan for the full-adder

To auto-place the standard cells, StdCel from Autoplace in the Place & Route palette was chosen.

Individual cells will be placed in the floorplan boxes. The cell locations are determined by their

interconnectivity, where cells that share connections are placed near one another. As shown in the figure

below, the gates in the full-adder are organized in the following order: AND-XOR-XOR-AND-OR. Then,

the cells are connected to the appropriate connections using Autoplace>Ports, and following result is

obtained:

Figure 28: Connections using Autoplace>Ports

After auto placing the correct connection using Ports, other options are needed to be selected from

Autoroute-All Options. In this section, channel over cell routing is selected from the Router Expert

Options, with Alignment Mode: No. From the OCR options menu, the step size is set to 0.5 and

Operation Mode Type is set to Center Weighted, leaving all other options as default. After hitting OK for

all the forms, following layout was obtained:

Figure 29: Final layout of full-adder

Sometimes when the design is too big, everything might not be routed and overflows might occur in the

layout. In order to select all the overflows in the design, check over is typed anywhere on the upper

window. Then, from place and route palette, overflow is selected. Following response ‘An object of type

Overflow must be selected’ appeared in the status block, indicating that there was no overflow to route.

The current progress was then saved to the current context.

To see the layers within a design in IC Station, Context Hierarchy Peek was selected after selecting all.

Then, after unselecting everything, in order to view specific layers from the upper menu bar, View Visible

Layers was selected from the toolbar. Then the layers were set using Set Visible Layers, where layers

from 41 through 51 were selected. Among these layers selected, there are layers for different purposes as

indicated below:

Nmos: Arsenic dope for n-channel source and drain (41),

Pmos: Boron dope for p-channel source and drain (42-46),

Oxide layer: LPCVD Oxide (Liquid Phase Chemical Vapor Deposition Oxide) (47), and

Contacts between different layers: Contact Definition (48-51)

The complete layout of the full-adder was obtained as shown in the figure below:

Figure 30: Final Full-adder with the added layers

After completing the final layout, we were supposed to create a complete IC chip suitable to manufacture.

In order to open the symbol of the whole full-adder, Design Architect was opened using the command

mentor ask_daic through terminal window. After opening the symbol of myFULLADDER, phy_comp

properties were added through Add Multiple Properties, where three inputs were selected with property

value of 1 for each input.

In order to create full design with pad frame, new project was started in the working directory called

design_name_chip. A new symbol was added to the cell by following Add>Instance>Choose Symbol.

The symbol for the full adder is shown below:

Figure 31: Symbol for the full adder

Using the pad frame inputs as well as pins from ADK Sim Palette, following was obtained from in the

Design Architect, where PIN01, PIN02 AND PIN03 represents inputs, while PIN04 AND PIN05

represents the outputs. Ground (GND) and Vdd pins are also added, which are represented as PIN06 and

PIN07 respectively, as shown in the schematic below:

Figure 32: Padframe Layout

Then the steps for creating a layout were followed from the above mentioned full-adder design. The core

logic were then selected and Inst on DLA Logic Palette was then selected to place these cells into layout

window. Once the core logic blocks are placed, Padframe can be generated using ADK>Generate

Padframe>AMI 0.5, which gives the result as shown in figure below.

Figure 33: Block instance of full-adder

Finally, after finalizing the placement of the core logic, the symbol is to be routed. To AutoRoute, All

from Autorou was selected. Then, on the prompt-bar appeared, Options was chosen and Expand Channel

from menu was unselected. After Clicking OK on the editing menu, the final layout of the chip was

obtained as shown as in the figure below. As shown in the figure, pins 1-7 are selected among the total of

40 pins, where 5 pin are representing the input and output channel, while one is for GND and other is for

Vdd.

Figure 34: Final Layout of the full-adder

Figure 35: The com

plete layout of the IC full-adder w

ith appropriate headings

Net: G

ND

, metal 1

Net: G

ND

, metal 2

Input A

Input Cin

Output C

out

Input B

Output S

Via

Net: V

DD

, metal 2

Net: G

ND

, metal 2

Net: V

DD

, metal 1

Net: V

DD

, metal 2

NE

T: G

ND

NE

T: G

ND

Net: V

DD

Net: V

DD

1

1: P-Well represented as the w

hole yellow box

2

2: n-Well represented as the w

hole green box

3

3: Active layers w

ithin both n-Well and p-w

ell

4

4: P-plus represented as the whole yellow

box

5

5: n-plus represented as the whole green box

6

RE

D thick w

ire: Poly-silicon layer

MA

TE

IAL

USE

D:

PUR

PLE

stripped box: metal 2

BL

UE

stripped box: metal 1 layer

6: contact to active layer indicated as green

check box with w

hite border

7: contact to poly-silicon layer indicated as red

check box with w

hite border

Conclusion

We have looked into different commands in Linux and become familiar with the industrial software, Mentor Graphics. In the first part of the lab, we have implemented and simulated an inverting gate with different output capacitances. Our result shows a slower response for the higher value (1000fF) capacitance. The difference between the rise times of the two capacitances value is approximately 9ns and 3 ns for the fall times. For the second part, we have implemented three logic gates at gate level: 2-input NOR, 3-input NAND, and NOT. We have explored into different layer and the overall layout of each design and identified each terminal. In the last part of the lab, we have implemented a full-adder at gate-level and padded the design into a chip. We have delved into different layers of the design and located both buffering and final inputs and outputs. Using the autoroute function, we obtain a final layer of the chip.