The Multicycle ProcessorCPSC 321

Andreas Klappenecker

Administrative Issues

• Midterm is on October 12• Allen Parish’s help session Friday 10:15-

12:15• Project 1 has been release – work in a

team

Questions? Problems?

Today’s Menu

The Multicycle Processor

Recall: Marrying two Datapaths

What kind of instructions can be realized by these datapaths?

Datapaths for Instruction Fetch, Memory and R-type Instructions

Note the added multiplexor switching between register 2 and sign-extended immediate value

Datapath for MIPS instructions

Control

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [15– 11]

ALUcontrol

ALUAddress

We get the control signals from bits 31-26 and 5-0

• Single memory unit for instructions and data

• Single arithmetic-logical unit• Registers after every major unit (some visible to the programmer, some not)

• hold output of that unit until value is used in next clock cycle

• data used in subsequent instructions must be stored in programmer visible registers

Multicycle Approach

Multicycle Datapath

PC

Memory

Address

Instructionor data

Data

Instructionregister

Registers

Register #

Data

Register #

Register #

ALU

Memorydata

register

A

B

ALUOut

Additional ‘Internal’ Registers

• Instruction and memory data register• both memory and instruction registers

are used because both values are needed

• A and B registers• hold register operands

• ALUout register • holds output of ALU

• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or

Branch Completion• Memory Access or R-type instruction

completion• Write-back step

INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

Five Execution Steps

• Use PC to get instruction and put it in the Instruction Register.

• PC = PC + 4• RTL "Register-Transfer Language"

IR = Memory[PC];PC = PC + 4;

What is the advantage of updating the PC now?

Step 1: Instruction Fetch

• Read registers rs and rt in case we need them• Compute the branch address in case the instruction is

a branch• RTL A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC+(sign-extended(IR[15-0])<<2);

• No control lines based on the instruction type are set b/c control logic busy "decoding".

Step 2: Instruction Decode and Register Fetch

• ALU performs one of three functions, based on instruction type• Memory Reference

ALUOut=A+sign-extend(IR[15-0]);• R-type

ALUOut = A op B;• Branch

if (A==B) PC = ALUOut;

Step 3 (Instruction Dependent)

• Loads and stores access memory MDR = Memory[ALUOut];

or Memory[ALUOut] = B;

• R-type instructions finishReg[IR[15-11]] = ALUOut;

The write actually takes place at the end of the cycle on the edge

Step 4 (R-type or memory-access)

• Load operationsReg[IR[20-16]]= MDR;

What about all the other instructions?

Step 5: Write-back step

Summary

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction for branches

Action for jumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)

Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

Clock Cycles per Instruction

• R-type• 4 clock cycles

• Memory reference instructions• 5 clock cycles

• Branches• 3 clock cycles

• Jumps• 3 clock cycles

• How many cycles will it take to execute this code? lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)

Label: ...• What is going on during the 8th cycle of execution?• In what cycle does the actual addition of $t2 and $t3

takes place?

Questions

MIPS Multicycle Datapath

Incomplete (branch and jumps…)

Control

• What are the control signals?• Finite state machine control

• Instruction fetch• instruction decode

• memory reference• R-type• branch• jump

Multicycle Datapath and Control Lines

Outlook

• What happens precisely during each step of fetch/decode/execute cycles

• Construct the finite state control machine• High-level view

Instruction Fetch/Decode/Execute

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction for branches

Action for jumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)

Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

Finite State Machines

Instruction Fetch & Decode FSM

Memory-Reference FSM

• Address calculation

• Load sequence

• read from memory

• store to register

• Access memory

• Store sequence write

R-type Instruction

• Execution of instruction

• Completion of instruction

Branch Instruction

Implementation of FSM

A FSM can be implemented by a register holding the state and a block of combinatorial logic

Task of the combinatorial logic:

• Assert appropriate signals

• Generate the new state to be stored in the register