Datapath and Control:MultiCycle Implementation

Performance of Single Cycle Machines

° Assume following operation times:• Memory units : 200 ps

• ALU and adders : 100 ps

• Register File (read or write): 50 ps

• Mux, control unit, PC access, sign extension unit, wires : 0 ps

Instr. Class Functional units used Total time

R-type Instr. Fetch (200 ps)

Reg access (50 ps)

ALU (100 ps)

Reg access (50 ps)

400ps

Load word Instr. Fetch (200 ps)

Reg access(50 ps)

ALU (100 ps)

Mem. Access (200 ps)

Register access (50 ps)

600 ps

Store Word Instr. Fetch (200 ps)

Reg access (50 ps)

ALU (100 ps)

Mem. Access (200 ps)

550 ps

Branch Instr. Fetch (200 ps)

Reg access(50 ps)

ALU (100 ps)

350 ps

Jump Instr. Fetch (200 ps)

200 ps

Clock cycle must cover longest instruction cycle period = 600ps (inefficient!)

Clocking: single-cycle vs. multicycle

Single-cycle Implementation

add $t0,$t1,$t2 beq $t0,$t1,Lwaste waste

clock

Multicycle Implementation

° Instruction execution divided into steps

°Each step will take one clock cycle (not each instruction) [CPI > 1]

shorter clock cycle: cycle time constrained by longest step, not longest instruction

°simpler instructions take fewer cycles

higher overall performance

Clocking: single-cycle vs. multicycle

add $t0,$t1,$t2 beq $t0,$t1,L

Single-cycle Implementation

Multicycle Implementation

add $t0,$t1,$t2 beq $t0,$t1,L

• Multicycle Implementation: less waste=higher performance

waste waste

clock

clock

How fast can we run the clock?

° Depends on how much we want done per clock cycle

• Can do: several “inexpensive” datapath operations per clock

- simple gates (AND, OR, …)

- single datapath registers (PC)

- sign extender, left shifter, multiplexor

• PLUS: exactly one “expensive” datapath operation per clock

- ALU operation

- Register File access (2 reads, or 1 write)

- Memory access (read or write)

Multicycle Instruction Execution1: fetch instruction, PC=PC+4

2: decode, fetch registers, branch target

3: execute/compute data address/branch

4: access memory/complete R-type

5: store memory content to register

Recall: Single Cycle Datapath and Control

StepsCycle R-format Load Word

(lw)Store Word (sw)

beq

1 Fetch instr,

PC = PC+4

Fetch instr.

PC = PC+4

Fetch instr,

PC = PC+4

Fetch instr,

PC = PC+42 Read registers,

calculate branch target address

Read registers, calc branch target address

Read registers, calc branch target address

Read registers, calc branch target address

3 Do computation Calc data address

Calc data address

Compare reg values, set PC

4 Write result to register

Read data memory

Write to data memory

5 Write data to register

Multicycle Datapath (overview)

Registers

ReadReg1

ALU

ReadReg2

WriteReg

Data

PC

Address

Instructionor Data

Memory

MIPS-liteMulticycle Version

A

B

ALU-Out

InstructionRegister

Data MemoryData

Register

Readdata 1

Readdata 2

• One ALU (no extra adders)• One Memory (no separate Imem, Dmem)• New Temporary Registers

Multicycle Implementation

°Datapath changes• one memory: both instructions and data (because can access on separate steps)

• one ALU (eliminate extra adders)

• extra “invisible” registers to capture intermediate (per-step) datapath results

Multicycle Datapath: Add Multiplexors

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

zero

15:11

Note inputs to multiplexors

Multicycle Datapath: Add Multiplexors

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

zero

15:11

Note inputs to multiplexors

Datapath + Control Points

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorDMemRead

MemWriteIRWrite

RegDstRegWrite

ALUSrcA

ALUSrcB

MemtoReg

ALUControl

ALUOp

22

4

(funct) 5:0

Mux

PCSrcPCWrite

PCWrite-Cond

Cycle 1 Datapath: IR=Mem[PC]; PC=PC+4

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

ALUControl

2

4

(funct) 5:0

Mux

IR=Mem[PC];PC=PC+4

IorD=0MemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=0

ALUSrcB=01

MemtoReg=x ALUOp=00

2

PCSrc=0PCWrite

PCWrite-Cond

Cycle 2: A=Reg[IR25:21]; B=Reg[IR20:16]; ALUOut= PC + sgn-ext(IR15:0) << 2

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

ALUControl

22

4

(funct) 5:0

Mux

A=Reg[IR25:21];B=Reg[IR20:16];ALUOut= PC +

sgn-ext(IR15:0) << 2

IorD=xMemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=0

ALUSrcB=11

MemtoReg=x ALUOp=00

2

PCSrc=xPCWrite

PCWrite-Cond

Cycle 3: R-format: ALUOut = A op B

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

ALUControl

2

4

(funct) 5:0

Mux

ALUOut=A op B

IorD=xMemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=1

ALUSrcB=00

MemtoReg=x ALUOp=10

2

PCSrc=xPCWrite

PCWrite-Cond

Cycle 4 R-format: Reg[IR15:11] = ALUOut

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

ALUControl

2

4

(funct) 5:0

Mux

Reg[IR15:11] = ALUOut

IorD=xMemRead

MemWriteIRWrite

RegDst=1RegWrite

ALUSrcA=x

ALUSrcB=x

MemtoReg=0 ALUOp=x

2

PCSrc=xPCWrite

PCWrite-Cond

Cycle 3 beq: if (A==B) PC =ALUOut

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

ALUControl

2

4

(funct) 5:0

Mux

if (A==B) PC =ALUOut

IorD=xMemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=1

ALUSrcB=00

MemtoReg=x ALUOp=01

2

PCSrc=01PCWrite

PCWrite-Cond

Cycle 3 lw/sw: ALUOut = A + sgn-ext(IR15:0)

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorD=xMemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=1

ALUSrcB=10

MemtoReg=x

ALUControl

ALUOp=00

22

4

(funct) 5:0

Mux

PCSrc=xPCWrite

PCWrite-Cond

ALUOut = A + sgn-ext(IR15:0)

Cycle 4 lw:MDR = Mem[ALUout]

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorD=1MemRead

MemWriteIRWrite

RegDst=xRegWrite

ALUSrcA=x

ALUSrcB=x

MemtoReg=x

ALUControl

ALUOp=x

22

4

(funct) 5:0

Mux

PCSrc=xPCWrite

PCWrite-Cond

MDR = Mem[ALUout]

Cycle 5 lw: Reg[IR15:11] = MDR

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorD=xMemRead

MemWriteIRWrite

RegDst=0RegWrite

ALUSrcA=x

ALUSrcB=x

MemtoReg=1

ALUControl

ALUOp=x

22

4

(funct) 5:0

Mux

PCSrc=xPCWrite

PCWrite-Cond

Reg[IR15:11] = MDR

Cycle 4 (sw): Mem[ALUOut] = B

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorD=1MemRead

MemWriteIRWrite

RegDstRegWrite

ALUSrcA

ALUSrc

MemtoReg

ALUControl

ALUOp

22

4

(funct) 5:0

Mux

PCSrcPCWrite

PCWrite-Cond

Mem[ALUOut] = B

Datapath + Control Points

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorDMemRead

MemWriteIRWrite

RegDstRegWrite

ALUSrcA

ALUSrcB

MemtoReg

ALUControl

ALUOp

22

4

(funct) 5:0

Mux

PCSrcPCWrite

PCWrite-Cond

Complete datapath

Fig. 5.30 Summary of steps taken

•All write control signals not asserted explicitly are deasserted

•All Multiplexer controls not specified explicitly are don’t care •asserted if name only

•otherwise exact value

1

FSM for Main Control Unit

0

Main Control Unit