Stld Lesson Plan

7/23/2019 Stld Lesson Plan

http://slidepdf.com/reader/full/stld-lesson-plan 1/43

DATE LESSON PLAN1 UNIT 1 Review of Number systems PART 1

2 CHAPTER Representation of numbers of different radix, conversion

3 INTRODUCTION, NEED AND BENEFITS OF THIS SESSION

Need and benefts o Nube!"n# s$stes o d"%e!ent !ad"&

Con'e!s"on (!o)edu!e o nube!"n# s$ste

* +E CONCEPTS

A Representation in B"na!$ nube! s$ste

B Representation in O)ta- nube! s$ste

C Representation in .e&ade)"a-

D

E

F/ CONTENT

PREPARED$es 0ISUAAID

PREPARED$es PPT PREPARED $es

BOO+ EADSSwitching Theory & Logic Design

( By A. Anand Kumar )

PAENO

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Switching Theory & Logic Design ( By D.A.Godse A.P.Godse )

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HO=E >OR+ 9 UNIT ASSIN=ENTS

Conversion of radix representation

1? CASS ROO= @UI

A "'e an e&a(-e o !e(!esentat"on !ad"& "n B"na!$ )ode

B "'e an e&a(-e o !e(!esentat"on !ad"& "n B"na!$ B"na!$ -o#")

C "'e an e&a(-e o !e(!esentat"on !ad"& "n B"na!$ He& )ode

D "'e an e&a(-e o !e(!esentat"on !ad"& "n B"na!$ O)ta- )ode

E

F

DATE LESSON PLAN

http://www.electronics-tutorials.ws/

http://www.nptel.ac.in/





1 UNIT 1 Review of Number systems PART 2

2 CHAPTER radix, r-1’s complement and r’s complement of unsigned numbers subtraction,problem solving.


P!ob-e o so-'"n# uns"#ned nube!s

* +E CONCEPTS

A D""n"s.ed !ad"& )o(-eent

B Subt!a)t"on :"t. )o(-eents

C S"#ned b"na!$ nube!s

D

E

F

/ CONTENTPREPARED

$es 0ISUAAIDPREPARED

$es PPT PREPARED $es



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E&a(-e (!ob-e so-'"n#

1? CASS ROO= @UI

A >.at "s !ad"&

B >.at "s Rs )o(-"ent

C >.at "s Uns"#ned

D

E

F

DATE LESSON PLAN





1 UNIT 1 Review of Number systems PART 3

2 CHAPTER -bit codes! "C#, $%C$&& ', alphanumeric codes,(’s complement, ))1, *)1


Int!odu)t"on "C#, $%C$&& ', ,(’s Complement,

Int!odu)t"on +lphanumeric Codes

Int!odu)t"on ))1, *)1

* +E CONCEPTS

A 2*21

B 7*21

C B"na!$ )oded de)"a-

D s 3 )ode

E

F

/ CONTENTPREPARED $es 0ISUAAIDPREPARED $es PPT PREPARED $es



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2*21, 7*21

s 3 )ode

B"na!$ )oded de)"a-

1? CASS ROO= @UI

A >.at "s 2*21

B >.at "s e&)ess 3

C >.at "s u-- o! o BCD

D

E

F

DATE LESSON PLAN1 UNIT 1 Review of Number systems PART *







2 CHAPTER ogic operation! "asic logic operations N,R,+N#,"oolean theorems,Complement and dual of logical expressions, N+N# and NR/ates, $%-R, $%-

NR /ates


O(e!at"on -o#")s

N,R,+N#,"oolean theorems

dual of logical expressions

* +E CONCEPTS

A AND,NAND

B OR, NOR

C NOT

D DUAIT

E )o(-eent

F E;OR,E;NOR

/ CONTENTPREPARED





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AND,NAND OR, NOR

NOT DUAIT

DUAIT

1? CASS ROO= @UI

A >.at "s #ate

B >.at "s -o#")

C >.at "s deo!#ans -a:

D >.at "s dua-"t$

E

F

DATE LESSON PLAN1 UNIT 1 Review of Number systems PART /







2 CHAPTER standard &0 and 0&, /ray code


Need And Benefts O &tandard &op +nd 0os, /ray Code

* +E CONCEPTS

A ;a(

B Tota- )o(-eent !ea-"at"on

C Su o (!odu)ts

D P!odu)t o sus

E !a$ )ode

F

/ CONTENTPREPARED




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standard &0 and 0&, /ray code notes preparation

1? CASS ROO= @UI

A >.at "s ;a(

B >.at "s Tota- )o(-eent !ea-"at"on

C >.at "s Su o (!odu)ts

D >.at "s P!odu)t o sus

E >.at "s !a$ )ode

F

DATE LESSON PLAN1 UNIT 1 Review of Number systems PART

2 CHAPTER $rror detection and error correction codes, parity checing, 2amming code








Int!odu)t"on, Need And Benefts O 2amming code

Int!odu)t"on, Need And Benefts O $rror detection and error correction codes, parity checing, 2amming

code

Int!odu)t"on, Need And Benefts O parity checing,

* +E CONCEPTS

A E!!o! dete)t"onB E!!o! )o!!e)t"on

C Pa!"t$ ).e)

D Ha"n# )ode

E

F

/ CONTENTPREPARED



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Switching Theory & Logic Design


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( By D.A.Godse A.P.Godse )

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$rror detection and error correction codes examples

1? CASS ROO= @UI

A >.at "s E'en (a!"t$

B >.at "s Odd (a!"t$

C >.at "s ).e)su

D

E

F

DATE LESSON PLAN1 UNIT 1 Review of Number systems PART 5

2 CHAPTER wo level N+N#-N+N# and NR-NR reali3ations








Benefts O wo level N+N#-N+N# and NR-NR reali3ations

* +E CONCEPTS

A =u-t" -e'e- #ate

B NAND;NAND !ea-"at"on

C NORGNOR !ea-"at"on

D

E

F

/ CONTENTPREPARED



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Switching Theory & Logic Design( By A. Anand Kumar )

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NAND;NAND !ea-"at"on ate!"a- #at.e!"n#

NORGNOR !ea-"at"on notes

1? CASS ROO= @UI

A Defne Su o (!odu)ts

B Defne P!odu)t o sus

C Defne Nand

D Defne No!

E

F

DATE LESSON PLAN1 UNIT 2 4inimisation of switching functions PART 1

2 CHAPTER "oolean theorems,principle of complementation,duality








Int!odu)t"on to "oolean theorems,principle of complementation,duality

* +E CONCEPTS

A T.eo!es

B Co(-eentat"on

C Dua-"t$ )on)e(t

D

E

F

/ CONTENTPREPARED





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T.eo!es (!a)t")e

1? CASS ROO= @UI

A Deo!#ans t.eo!e

B >.at "s Asso)"at"'e -a:

C >.at "s D"st!"but"'e -a:

D >.at "s Coutat"'e -a:

E

F


2 CHAPTER #emorgans theorems,minimi3ation of logic functions using -map








5sing -map for minimi3ation of logic functions

* +E CONCEPTS

A So-'"n# un)t"on

B Redu)"n# u)t"on

C

D

E

F

/ CONTENTPREPARED



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Switching Theory & Logic Design( By A. Anand Kumar )

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So-'"n# un)t"on

1? CASS ROO= @UI

A E&a(-e so-'e

B >.at "s deo!#an t.eo!e

C

D

E

F

DATE LESSON PLAN1 UNIT 2 4inimi3ation of switching functions PART 3







2 CHAPTER 4inimi3ation using "oolean theorem


Int!odu)t"on to "oolean theorem

* +E CONCEPTS

A Boo-ean t.eo!e

B

C

D

E

F

/ CONTENTPREPARED




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Boo-ean t.eo!e

1? CASS ROO= @UI

A >.at "s "n"""n# te).n"ues

B

C

D

E

F

DATE LESSON PLAN







1 UNIT 2 4inimisation of switching functions PART *

2 CHAPTER 4inimisation of switching functions


Int!odu)t"on to 4inimisation of switching functions

* +E CONCEPTS

A T:o 'a!"ab-e a(

B T.!ee 'a!"ab-e a(

C Fou! 'a!"ab-e a(

D Dont )a!e

E ="nte!

F =a&te!




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Dont )a!e4

>.at "s ="nte! and =a&te!

T:o t.!ee ou! 'a!"ab-e a(

1? CASS ROO= @UI

A >.at "s a(("n# o SOP e&(!ess"on

B >.at "s a(("n# o POS e&(!ess"on

C P!"e "(-")ant

D

E

F







DATE LESSON PLAN



1 UNIT 2 4inimisation of switching functions PART /

2 CHAPTER 4inimi3ation of switching functions using -map 6 variables


Need And Benefts O 4inimi3ation of switching functions using -map 6 variables

* +E CONCEPTS

A S"& 'a!"ab-e a(

B P!"e "(-")ants

C Dont )a!es

D H$b!"d -o#")

E ""tat"ons o a(

F




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S"& 'a!"ab-e a(

P!"e "(-")ants

H$b!"d -o#")

1? CASS ROO= @UI

A >.at a!e essent"a- (!"e "(-")ants

B >.at "s .$b!"d -o#")

C >.at "s s"& 'a!"ab-e a(

D

E

F







DATE LESSON PLAN1 UNIT 2 4inimisation of switching functions PART

2 CHAPTER abular minimi3ation


Int!odu)t"on to abular minimi3ation

* +E CONCEPTS

A abular minimi3ation procedure

B

C

D

E

F

/ CONTENTPREPARED





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abular minimi3ation

1? CASS ROO= @UI

A $xplain the procedure for abular minimi3ation7

B

C

D

E

F








2 CHAPTER 0roblem solving


* +E CONCEPTS

A 0rocedure for 0roblem solving7

B

C

D

E

F

/ CONTENTPREPARED





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0roblem solving

1? CASS ROO= @UI

A $xplain the procedure of 0roblem solving7

B

C

D

E

F








2 CHAPTER code converters using map


Int!odu)t"on to code converters using map

* +E CONCEPTS

A

B

C

D

E

F

/ CONTENTPREPARED





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code converters using map

1? CASS ROO= @UI

A code converting procedure using map7

B

C

D

E

F







DATE LESSON PLAN1 UNIT 3 Combinational logic circuits PART 1

2 CHAPTER #esign of 2alf adder, full adder, half subtractor, fullsubtractor, applications of full adders


#esign of 2alf adder, full adder, applications of full adders

half subtractor, full subtractor,

applications of full adders

* +E CONCEPTS

A Ha- adde!

B Fu-- adde!

C Ha- subt!a)to!

D Fu-- subt!a)to!

E

F

/ CONTENTPREPARED





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applications of full adders

1? CASS ROO= @UIA E&(!ess"on o! HA

B E&(!ess"on o! FA

C E&(!ess"on o! HS

D E&(!ess"on o! FS

E

F








2 CHAPTER -bit binary adder, -bit binary subtractor, adder-subtractor circuit, "C# adder circuit


adder-subtractor circuit,benefits

* +E CONCEPTS

A BCD add"t"on

B BCD subt!a)t"on

C

D

E

F

/ CONTENTPREPARED





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BCD add"t"on )"!)u"t d"a#!as

BCD add"t"on )"!)u"t d"a#!as

1? CASS ROO= @UIA "'e an e&a(-e o BCD add"t"on )"!)u"t

B "'e an e&a(-e o BCD subt!a)t"on )"!)u"t

C "'e an e&a(-e o * b"t b"na!$ add"t"on )"!)u"t

D "'e an e&a(-e o * b"t b"na!$ add"t"on )"!)u"t

E

F








2 CHAPTER $xcess' adder circuit, loo-a-head adder circuit, #esign of decoder


8ntroduction to #esign of decoder

* +E CONCEPTS

A s3 add"t"on

B s3 subt!a)t"on

C de)ode!

D oo a.ead

E

F

/ CONTENTPREPARED





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s3 add"t"on (!a)t")e

s3 subt!a)t"on (!a)t")e

1? CASS ROO= @UI

A E&(-a"n s3 add"t"on

B E&(-a"n s3 subt!a)t"on

C E&(-a"n de)ode!

D

E

F







DATE LESSON PLAN1 UNIT 3 Combinational logic circuits PART *

2 CHAPTER #emultiplexer, higher order demultiplexing, 9 segment decoder


8ntroduction to #emultiplexer,

8ntroduction to 9 segment decoder

* +E CONCEPTS

A Data d"st!"buto!s

B Deu-t"(-e&"n# t!ee

C De)ode!

D 5 se#ent

E

F

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Deu-t"(-e&"n# t!ee4

1? CASS ROO= @UI

A >.at a!e Data d"st!"buto!s

B >.at "s Deu-t"(-e&"n# t!ee

C >!"te 5 se#ent )ode

D

E

F







DATE LESSON PLAN1 UNIT 3 Combinational logic circuits PART /

2 CHAPTER encoder, multiplexer, higher order multiplexer


8ntroduction to encoder

* +E CONCEPTS

A 2 "n(ut u&

B * "n(ut u&

C 1 "n(ut u& !o t:o 7 "n(ut u&

D

E

F

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1 "n(ut u& !o t:o 7 "n(ut u&

1? CASS ROO= @UI

A E&(-a"n 2 "n(ut u&

B E&(-a"n * "n(ut u&

C E&(-a"n 1 "n(ut u& !o t:o 7 "n(ut u&

D

E

F







DATE LESSON PLAN1 UNIT 3 Combinational logic circuits PART

2 CHAPTER reali3ation of "oolean functions using decoders and multiplexers


"oolean functions introduction

* +E CONCEPTS

A De)ode!

B u-t"(-e&e!

C Boo-ean un)t"on

D

E

F

/ CONTENTPREPARED





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De)ode!

u-t"(-e&e!

Boo-ean un)t"on

1? CASS ROO= @UI

A Defne De)ode!

B Defne u-t"(-e&e!

C Defne Boo-ean un)t"on

D

E

F








2 CHAPTER priority encoder, bit digital comparator


priority encoder introduction

bit digital comparator benifits

* +E CONCEPTS

A * "n(ut (!"o!"t$ en)ode!

B De)"a- to b)d (e

C O)ta- to b"na!$ (e

D

E

F

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* "n(ut (!"o!"t$ en)ode!

De)"a- to b)d (e

O)ta- to b"na!$ (e

1? CASS ROO= @UI

A Defne * "n(ut (!"o!"t$ en)ode!

B Defne De)"a- to b)d (!"o!"t$ en)ode!

C Defne O)ta- to b"na!$ (!"o!"t$ en)ode!

D

E

F







DATE LESSON PLAN1 UNIT * Combinational logic circuits PART 1

2 CHAPTER 0R4,0+,0+, basic structures


8ntroduction to basic structures

* +E CONCEPTS

A RO= o!#an"at"on

B Cob"nat"ona- )"!)u"t "(-eentat"on

C T$(es o RO=s

D P!o#!aab-e RO=

E

F

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RO= o!#an"at"on

T$(!es o RO=s

1? CASS ROO= @UI

A RO= o!#an"at"on .o:

B =ent"on T$(es o RO=s

C Cob"nat"ona- )"!)u"t "(-eentat"on .o:

D

E

F








2 CHAPTER Reali3ation of "oolean function with pld’s


8ntroduction to "oolean function with pld’s

* +E CONCEPTS

A o#") de'")e

B P!o#!aab-e -o#") de'")e

C

D

E

F

/ CONTENTPREPARED





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o#") de'")e

1? CASS ROO= @UI

A Defne o#") de'")e

B Defne P!o#!aab-e -o#") de'")e

C Co(a!e o#") de'")e and P!o#!aab-e -o#") de'")e

D

E

F








2 CHAPTER 0rogramming tables of 0#’s


8ntroduction to 0rogramming tables of 0#’s

* +E CONCEPTS

A P!o#!a tab-e

B PD

C

D

E

F

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P!o#!a tab-e

PD

1? CASS ROO= @UI

A Ho: to )onst!u)t a P!o#!a tab-e

B

C

D

E

F







DATE LESSON PLAN1 UNIT * Combinational logic circuits PART *

2 CHAPTER 4erits and demerits, comparison of 0R4,0+,and 0+reali3ation of booleanfunctions using 0R4,0+ and 0+


Int!odu)t"on to 0R4,0+,and 0+reali3ation of boolean functions

* +E CONCEPTS

A Co(a!"s"on of 0R4,0+

B PRO=

C PA,PA

D =e!"ts

E dee!"ts

F

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Co(a!"s"on

=e!"ts

dee!"ts

1? CASS ROO= @UIA =e!"ts and de e!"ts o 0R4, 0+, and 0+ reali3ation7

B

C

D

E

F







DATE LESSON PLAN1 UNIT * Combinational logic circuits PART /

2 CHAPTER Reali3ation of "oolean functions using 0R4,0+,0+


Int!odu)t"on to 0R4,0+,0+

* +E CONCEPTS

A Rea-"at"ons

B

C

D

E

F

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Rea-"at"ons ate!"a-

1? CASS ROO= @UI

A

B Reali3ation of "oolean functions : procedure 7

C

D

E

F







DATE LESSON PLAN1 UNIT * Combinational logic circuits PART

2 CHAPTER 0rogramming tables of 0R4,0+,0+


Int!odu)t"on to 0R4,0+,0+

* +E CONCEPTS

A P!o#!a tab-e o PA

B P!o#!a tab-e o PA

C P!o#!a tab-e o PRO=

D

E

F

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P!o#!a tab-e o PA

P!o#!a tab-e o PA

P!o#!a tab-e o PRO=

1? CASS ROO= @UI

A E&(-a"n P!o#!a tab-e o PA

B E&(-a"n P!o#!a tab-e o PA

C E&(-a"n P!o#!a tab-e o PRO=

D

E

F







DATE LESSON PLAN1 UNIT / &e;uential circuits PART 1

2 CHAPTER Classification of se;uential circuits <synchronous and asynchronous=


Int!odu)t"on to se;uential circuits

* +E CONCEPTS

A Seuent"a- )"!)u"t

B S$n).!onous )"!)u"t

C As$n).!onous )"!)u"t

D

E

F

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Seuent"a- )"!)u"t d"a#!as

S$n).!onous )"!)u"t d"a#!as

As$n).!onous )"!)u"t d"a#!as

1? CASS ROO= @UIA D!a: Seuent"a- )"!)u"t d"a#!as

B D!a: S$n).!onous )"!)u"t d"a#!as

C D!a: As$n).!onous )"!)u"t d"a#!as

D

E

F








2 CHAPTER basic flip-flops, truth tables and excitation tables


Int!odu)t"on to basic flip-flops, truth tables and excitation tables

* +E CONCEPTS

A F-"( o(

B T!ut. tab-e

C E&)"tat"on tab-e

D

E

F

/ CONTENTPREPARED





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F-"( o( notes

T!ut. tab-e

E&)"tat"on tab-e

1? CASS ROO= @UI

A E&(-a"n T!ut. tab-e

B E&(-a"n E&)"tat"on tab-e

C E&(-a"n d"%e!ent t$(es o "( o(s

D

E

F








2 CHAPTER Conversion of flip-flop to f lip-flop


8ntroduction to flip-flop

* +E CONCEPTS

A Conversion of flip-flop to flip-flop

B

C

D

E

F

/ CONTENTPREPARED





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Conversion of flip-flop to flip-flop

1? CASS ROO= @UI

A Conversion of &R to >?7

B Conversion of >? to &R7

C Conversion of &R to #7

D Conversion of >? to #7

E Conversion of # to >? 7

F







DATE LESSON PLAN1 UNIT / &e;uential circuits PART *

2 CHAPTER #esign of ripple counters, design of synchronous counters


ripple counters introduction

* +E CONCEPTS

A R"((-e )ounte! des"#n

B design of synchronous counters

C

D

E

F

/ CONTENTPREPARED





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R"((-e )ounte! des"#n

design of synchronous counters

1? CASS ROO= @UI

A R"((-e )ounte! des"#n (!o)edu!e

B design of synchronous counters procedure 7

C

D

E

F







DATE LESSON PLAN1 UNIT / &e;uential circuits PART /

2 CHAPTER >ohnson counters, ring counters


Int!odu)t"on to counters

* +E CONCEPTS

A 6o.nson )ounte!

B R"n# )ounte!

C

D

E

F

/ CONTENTPREPARED





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5 6OURNA EADS


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6o.nson )ounte! des)!"(t"on

R"n# )ounte! des)!"(t"on

1? CASS ROO= @UI

A >.at a!e t.e T$(es o )ounte!s

B 6o.nson )ounte! des)!"(t"on

C R"n# )ounte! des)!"(t"on

D

E

F







DATE LESSON PLAN1 UNIT / &e;uential circuits PART

2 CHAPTER #esign of registers, "uffer register, control buffer register


Int!odu)t"on to register

* +E CONCEPTS

A Re#"ste!

B Bu%e! !e#"ste!

C Cont!o- bu%e! !e#"ste!

D

E

F

/ CONTENTPREPARED





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Re#"ste! des"#n

Bu%e! !e#"ste! des"#n

Cont!o- bu%e! !e#"ste! des"#n

1? CASS ROO= @UI

A Re#"ste! des"#n (!o)edu!e

B Bu%e! !e#"ste! des"#n (!o)edu!e

C Cont!o- bu%e! !e#"ste! des"#n (!o)edu!e

D T$(es o !e#"ste!s

E

F








2 CHAPTER shift register, bidirectional shift register, universal shift register


Int!odu)t"on to register

* +E CONCEPTS

A universal shift register

B shift register

C B"d"!e)t"ona- shift register

D

E

F

/ CONTENTPREPARED





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universal shift register

shift register

B"d"!e)t"ona- shift register

1? CASS ROO= @UI

A $xplain universal shift register7

B $xplain shift register7

C $xplain B"d"!e)t"ona- shift register7

D

E

F







DATE LESSON PLAN1 UNIT &e;uential circuits PART 1

2 CHAPTER @inite state machine


State a)."ne "nt!odu)t"on

State tab-e "nt!odu)t"on

* +E CONCEPTS

A State a)."ne

B State tab-e

C @inite state machine

D

E

F

/ CONTENTPREPARED





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5 6OURNA EADS


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State a)."ne

State tab-e

@inite state machine

1? CASS ROO= @UI

A $xplain State a)."ne

B $xplain State tab-e

C $xplain @inite state machine7

D

E

F








2 CHAPTER analysis of cloced se;uential circuits


cloced se;uential circuits introduction

* +E CONCEPTS

A C-o)ed )"!)u"ts

B Seuent"a- )"!)u"ts

C

D

E

F

/ CONTENTPREPARED





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C-o)ed )"!)u"ts

Seuent"a- )"!)u"ts

1? CASS ROO= @UI

A S.o: a C-o)ed )"!)u"ts d"a#!a

B S.o: a Seuent"a- )"!)u"ts d"a#!a

C

D

E

F








2 CHAPTER state diagrams and state tables


state diagrams and state tables introduction

* +E CONCEPTS

A State tab-e

B State d"a#!a

C State !edu)t"on

D State ass"#nent

E

F

/ CONTENTPREPARED





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State d"a#!a

1? CASS ROO= @UI

A E&(-a"n State tab-e

B D!a: a State d"a#!a

C State !edu)t"on (!o)edu!e

D State ass"#nent need

E

F







DATE LESSON PLAN1 UNIT &e;uential circuits PART *

2 CHAPTER Reduction of state tables and state assignment.


state tables and state assignment introduction

* +E CONCEPTS

A State !edu)t"on

B State ass"#nent

C

D

E

F

/ CONTENTPREPARED





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PAENO

5 6OURNA EADS


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State ass"#nent

1? CASS ROO= @UI

A State !edu)t"on te).n"ues

B State ass"#nent needs

C

D

E

F







DATE LESSON PLAN1 UNIT &e;uential circuits PART /

2 CHAPTER #esign procedures


#esign procedures needs

* +E CONCEPTS

A #esign procedures

B

C

D

E

F

/ CONTENTPREPARED





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#esign procedures

1? CASS ROO= @UI

A #esign procedures7

B

C

D

E

F







DATE LESSON PLAN1 UNIT &e;uential circuits PART

2 CHAPTER Reali3ation of circuits using various flip-flops


flip-flops introduction

* +E CONCEPTS

A Reali3ation of circuits

B various flip-flops

C

D

E

F

/ CONTENTPREPARED





PAENO

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5 6OURNA EADS



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Reali3ation of circuits using various flip-flops

1? CASS ROO= @UI

A Reali3ation of circuits7

B various flip-flops7

C

D

E

F








2 CHAPTER 4eelay to 4oore conversion and vice-versa


Int!odu)t"on to 4eelay and 4oore models

* +E CONCEPTS

A =ee-a$ ode-

B =oo!e ode-

C )on'e!s"on

D

E

F

/ CONTENTPREPARED





PAENO


PAENO

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5 6OURNA EADS


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=ee-a$ ode-

=oo!e ode-

)on'e!s"on

1? CASS ROO= @UI

A E&(-a"n =ee-a$ ode-

B E&(-a"n =oo!e ode-

C E&(-a"n )on'e!s"on o abo'e ode-s

D

Documents

Stld Lesson Plan