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Chapter 6 -- Introduction to Sequential Devices

The Sequential Circuit Model

x1 xn

Combinational logic (a)

z1 zm

x1 xnCombinational logic

z1 zm

y1 yr

Yr Y1

Memory

(b)

Figure 6.1

Models for Sequential Circuits

Block diagram representation: Figure 6.1 State Tables and Diagrams: the functional relationship that exists among the input, output, present state, and next state is illustrated by either the state table or the state diagram. The state diagram is a graphical representation of a sequential circuit in which the states are represented by circles and the state transitions (the transfer from the present state y to the next state Y) are shown by arrows. The state table lists the inputs across the top, the outputs along the left side, with the entries in the table being the next state and output for each input and present state.

State Tables and State Diagrams

Input Present state x

Next state x/z Y Input/output Present state y Next state/output (a) (b) y Y/z

Figure 6.2

Example 6.1 State tables and DiagramsConsider a sequential circuit having one input variable x, two state variables y1 and y2, and one output variable z. Inputs: x=0 x=1 States: [y1,y2] = [00] [y1,y2] = [01] [y1,y2] = [10] [y1,y2] = [11]

A B C D

Outputs: z = 0 z=1 The state diagram for this circuit is shown in Fig. 6.3

Example 6.1 (continued)

Now assume the circuit is initially in state A. If an input of x = 0 is applied the next state is D and the output is 0. Consider the application of the following input sequence to the circuit x = 0110101100The circuit will behave as follows: present state: A D B A D B input: 0 1 1 0 1 0 next state: D B A D B B output: 0 1 0 0 1 1

B 1 B 0

A 1 A 1

C 0 C 1

C C 0 C C 1

Example sequential circuit

Input x A B C D 0 D/0 B/1 C/1 A/0 1 C/1 A/0 D/0 B/1A 1/1

Present state

0/1

(a) State table

C

0/0 1/0 0/0

1/0

B 1/1 0/1

D x/z (b)

Figure 6.3

State diagram

Memory Devices

Memory elements exist indefinitely in one of two possible states, 0 and 1. Binary data are stored in a memory element by placing the element into the 0 state to store a 0 and into the 1 state to store a 1. The output Q of the circuit indicates the present state of the memory. The two memory element types most commonly used in switching circuits are latches and flip-flops. Latches are devices whose excitation inputs control the state of the device. A flip-flop differs from a latch in that it has a control switch called a clock. This means a flip-flop waits for its clock signal before changing states. The final state of a flip-flop is determined by its excitation values at the time the clock signal occurs.

Table 6.1 TTL Memory Elements [1]Number of Elements Element Description 2 Negative-edge triggered flip-flop with clear 2 Positive-edge triggered D flip-flop with preset and clear 4 D latch with enable 2 Pulse-triggered JK flip-flop with preset and clear 2 Master-slave JK flip-flop with preset, clear, data lockout 2 4-Bit hazard-free D latch with clear and dual enable 4 Positive-edge triggered D flip-flop with clear 8 Positive-edge triggered D flip-flop with clear 4 Negative-edge triggered JK flip-flop with preset, clear 4 SR latch with active-low inputs

Device 74LS73A 7474 74LS75 7476 74111 74116 74175 74273 74276 74279

Set-reset latch

S

N1 N1

Q N2 Q S R (a) S latch redrawn N1

Q N2 (b) SR latch Q

S

N1

Q

S

Q

R

N2

Q

R

Q

(c) Traditional view of SR latch

(d)

Logic symbol of SR latch

Figure 6.7

NAND SR LatchS S N1 Q S=0 S=1 Q

R

R

N2

Q

R=0

R=1 (b)

Q

(a)

Logic diagram

Storage mode

S Q

S

Q

S

Q

RQ R

Q

R (e)

Q

(d)(c)

Reduced logic

Logic symbol 1

Logic symbol 2

Figure 6.8

SR Latch Timing Diagrams

The operation of any latch circuit may be described using a timing diagram. The diagram shown in Fig. 6.9 shows that placing logic 1 signals on both the R and S inputs forces both outputs, Q and Q, to logic 0. When the two inputs are returned to logic 0, a race condition is created, and which state the device will assume can not be determined. Consequently, the use of the SR latch is restricted to exclude the input combination S = R = 1. If the R signal is returned to logic 0 before S, the final state of Q will be a logic 1. If S is returned to logic 0 first, the device will be reset to logic 0.

Set-Reset Latch Timing DiagramS R Q Q

Set (a)

Reset

Set

Illegal inputs Unknown values

Ideal (zero-gate delay)

S R Q Q

Set

Reset

Set

Illegal inputs Unknown values

Figure 6.9

(b)

Actual timing with non-zero delalys

Delay Parameters

Every circuit output requires a nonzero amount of time to respond to changes on its input, as specified by delay parameters tPLH and tPHL . Recall that tPLH designates the delay time between an input change and a corresponding low-to-high transition of an output. tPHL is the delay between an input change and a corresponding highto-low transition. For a latch circuit the delay parameters represent the sum of the propagation delays through the gates between a given latch input and output, with separate delay parameters usually specified for each input/output pair.

Delay Parameters (continued)

For example, Fig. 6.10 illustrates the timing behavior of the SR latch of Fig. 6.7c. Following a change in S from 0 to 1, note that output Q changes from 1 to 0 after propagation delay tPHL through N1. Then the feedback signal causes the Q output to change from 0 to 1 after propagation time tPLH through N2. Thus, output Q always changes before output Q when setting an SR latch built from cross-coupled NOR gates. Therefore, tPHL from input S to output Q involves a single gate delay, whereas tPLH from input S to output Q includes two gate delays.

SR Latch Propagation Delays

S R Q Q

tPLH (S to Q) tPLH (N 2) tPHL (R to Q) tPHL (N 2) tPHL (N 1) tPLH (N 1)

Figure 6.10

SR Latch Excitation Table and Characteristic Equation

The logical operation of the SR latch is summarized in the excitation table of Fig. 6.11a. The excitation table is simply the state table of the latch, showing the state transitions for each combination of excitation inputs. The information from the table can be represented as a state diagram, as shown in Fig. 6.11b, and plotted in K-map form, as shown in Fig. 6.11c, where the value of the next state Q* is plotted as a function of the inputs, S and R, and the present state Q. From the K-map the characteristic equation of the SR latch can be derived: Q* = S + RQ.

SR Latch: Characteristic Equation (continued)

The characteristic equation is so called because it characterizes the operation of the latch. We can classify the latch operation into three cases:

1. S = R = 0 the state does not change 2. S = 1, R = 0 represents the set operation 3. S = 0, R = 1 represents the reset operation

SR latch characteristicsSRExcitation inputs S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Present state Q 0 1 0 1 0 1 0 1 (a) Next state Q* 0 1 0 0 1 1 No change Reset Set Not allowed

0d 10 0 01 1

d0

(b) State diagram

SR Q 00 0 Q 1 0 1 01 0 0 11 -

S 10 1 1

Excitation table

R (c)

Figure 6.11

K-map of latch output Q*

Gated SR Latch

Often it is desirable to use a special control signal to inhibit state changes in an SR latch while S and R are changing. This device is commonly referred to as a gated SR latch, since the control signal can be thought of as opening a gate through which signals on the S and R inputs propagate to the output. Circuit Structure: In Fig. 6.13a, a control signal C, is added to an SR latch to apply the inputs S and R. The two AND gates apply the control signal S and R during time intervals when the enable signal C is logic 1. When C is logic 0, the inputs are held in the S = R = 0 state.

Gated SR Latch (continued)

So the operation of the latch is as follows: when C = 0, no change occurs when C = 1, the SR excitation table of Fig. 6.11a and the characteristic equation describe its function. If the AND gates are changed to NAND gates and cross-coupled NAND gates are used for the SR latch, the circuit of Fig. 6.13b results. The NAND gate implementation of the gated SR latch is shown in Fig. 613.c. The generic logic symbol for the gated SR latch is shown in Fig. 6.13d.

Gated SR LatchS

Figure 6.13

SS Q

S

Q

C R (a) Q

C R (b) Q

R

R

With NOR SR latch

With NAND SR latch

S C S C Q R (c) C R(d)

SQ

Q

C R Q

logic symbol

NAND logic diagram

Gated SR Latch (continued)

Characteristic Equation: The complete excitation table and state diagram of the gated SR latch are given in Figs. 6.14a and b. From the excitation table the characteristic equation is derived: Q* = SC + RQ + CQ Note that when C = 0 this equation reduces to Q* = Q which means that the present state is held. When C = 1 the equation becomes: Q* = S + RQ, the characteristic equation of the simple SR latch, and thus the latch is enabled.

Gated SR Latch Characteristics

Enable inputs C 0 0 1 1 1 1 1 1 1 1 (a)