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7/28/2019 Jntu Anan Ece 2 2 Stld Set 3
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S.25Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Code No: 9A04401/R09
II B.Tech. II Semester, Regular & Supplementary Examinations
April/May - 2012SWITCHING THEORY & LOGIC DESIGN
( Common to EEE, EIE, E.Con.E, ECE & ECC )
Time: 3 Hours Max. Marks: 70
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) List the binary, octal and hexa numbers for decimal 16 to 31. (Unit-I, Topic No. 1.1)
(b) Perform the following operations using 2s complement method:
(i) 48 23(ii) 23 48 (Unit-I, Topic No. 1.2)
2. (a) State and prove Boolean laws related to OR, AND, NOT gates. (Unit-II, Topic No. 2.1)
(b) Give Boolean expression AB' + A'B = C. Show that AC' + A'C = B. (Unit-II, Topic No. 2.2)
(c) Prove that OR-AND network is equivalent to NOR-NOR network. (Unit-II, Topic No. 2.3)
3. (a) Simplify the following Boolean function for minimal SOP form using K-map F(W, X, Y, Z) =(0, 1, 2, 3, 4, 6, 8, 9, 10, 11).
(Unit-III, Topic No. 3.1)
(b) Simplify the following Boolean functions using K-map,
(i) F(A, B, C) = A'B + B'C + A'B'C'
(ii) F(A, B, C) = A'B' + AC' + B'C + A'B'C'. (Unit-III, Topic No. 3.1)
4. (a) Implement full adder using 4*1 multiplexer. (Unit-IV, Topic No. 4.2)
(b) Design 4*16 decoder using two 3*8 decoders with block diagram. (Unit-IV, Topic No. 4.2)
5. (a) Explain the general combinational PLD configuration with suitable block diagram. (Unit-V, Topic No. 5.1)
(b) Give the logic implementation of a 32 4-bit and 8 4-bit ROM using suitable decoder. (Unit-V, Topic No. 5.1)
6. (a) Draw the circuit diagram of 4-bit ring counter using D flip flops and explain its operation with the help of bit
pattern. (Unit-VI, Topic No. 6.3)
(b) Distinguish between transition table and excitation table. (Unit-VI, Topic No. 6.1)
7. A clocked sequential circuit with simple input x and single output Z produce an output Z = 1 whenever the input x
completes the sequence 1 0 1 1 and overlapping is allowed.
(a) Obtain its state-diagram.(b) Obtain its minimal state-table and design the circuit with D-Flip-Flops. (Unit-VII, Topic No. 7.3)
8. (a) For the given control state diagram obtain its equivalent ASM chart. (Unit-VIII, Topic No. 8.2)
(b) Design control logic circuit using multiplexers for the given state diagram. (Unit-VIII, Topic No. 8.2)
T0 T1 T2S'S A3A4
A3A4
A3
X
T0 T1 T2S'S A3A4
A3A4
A3
X
S e t - 3S o l u t i o n s
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S.26 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Q1. (a) List the binary, octal and hexa numbersfor decimal 16 to 31
Answer : April/May-12, Set-3, Q1(a)
The list of binary, octal and hexadecimal numbers for
decimal numbers 16 to 31 are shown in table,
DecimalBinary Octal Hexa
(base - 2) (base - 8) (base - 16)
16 10000 20 10
17 10001 21 11
18 10010 22 1219 10011 23 13
20 10100 24 14
21 10101 25 15
22 10110 26 16
23 10111 27 17
24 11000 30 18
25 11001 31 19
26 11010 32 1A
27 11011 33 1B
28 11100 34 1C
29 11101 35 1D
30 11110 36 1E
31 11111 37 1F
(b) Perform the following operations using2s complement method:
(i) 48 23
(ii) 23 48.
Answer : April/May-12, Set-3, Q1(b)
(i) (48 23) in 2s Complement Form
Binary equivalent of 48 = (110000)2
Binary equivalent of 23 = (010111)2
In decimal form,
48 23 = 25
The subtraction operation of 48 23 using 2s
complement form is the addition of binary equivalent of 48
to the 2s complement of binary equivalent of 23.
i.e., 48 23 = (110000)2 (010111)
2= (110000)
2+ (2s
complement of (010111)2)
SOLUTIONS TO APRIL/MAY-2012, SET-3, QP
The 2s complement of 010111 is obtained, as
2s complement of 010111 = 1s complement of 010111 + 1
= 101000 + 1
= 101001
Then, (110000)2 (010111)
2= (110000)
2+ (101001)
2
1 1 0 0 0 0
1 0 1 0 0 1
1 0 1 1 0 0 1
Discard the carry
1 1 0 0 0 0
1 0 1 0 0 1
1 0 1 1 0 0 1
Discard the carry
10222 )25()011001()010111()110000(2348 ===
(ii) (23 48) in 2s Complement Form
Binary equivalent of 23 = (010111)2
Binary equivalent of 48 = (110000)2
23 48 = (010111)2
(110000)2
= (010111)2
+ (2s
complement of (110000)2)
2s complement of (110000)2
= 1s complement of
(110000)2+ 1
= (001111)2+ 1
0 0 1 1 1 1
1
0 1 0 0 0 0
0 0 1 1 1 1
1
0 1 0 0 0 0
Now,
(010111)2 (110000)
2= (010111)
2+ (010000)
2
0 1 0 1 1 1
0 1 0 0 0 0
1 0 0 1 1 1
0 1 0 1 1 1
0 1 0 0 0 0
1 0 0 1 1 1
= 100111
Since, there is no carry, the result is in 2s complement form.
To obtain the actual result, again performing 2s
complement on the result, we get,
[1s complement of (100111) + 1] = [011000 + 1]
= (011001)2
= 25
The actual result is,
10222 )25()011001()110000()010111(4823 ===
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S.27Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Q2. (a) State and prove Boolean laws relatedto OR, AND, NOT gates.
Answer : April/May-12, Set-3, Q2(a)
For answer refer Unit-II, Q3.
(b) Give Boolean expression AB' + A'B = C.Show that AC' + A'C = B.
Answer : April/May-12, Set-3, Q2(b)
For answer refer Unit-II, Q12.
(c) Prove that OR-AND network is equivalentto NOR-NOR network.
Answer : April/May-12, Set-3, Q2(c)
For answer refer Unit-II, Q22.
Q3. (a) Simplify the following Boolean function
for minimal SOP form using K-map F(W,X, Y, Z) = (0, 1, 2, 3, 4, 6, 8, 9, 10, 11).
Answer : April/May-12, Set-3, Q3(a)
The given Boolean function is,
F(W,X,Y,Z)=(0, 1, 2, 3, 4, 6, 8, 9, 10, 11)
The above Boolean expression can be simplified by
loading it into the four variable K-map as shown in figure
below,
1 1 1 1
1 1
1 1 1 1
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
WXYZ X
WZ
00 01 11 10
10
11
01
00 1 1 1 1
1 1
1 1 1 1
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
WXYZ X
WZ
00 01 11 10
10
11
01
00
Figure: 4-variable K-map
Therefore, the simplified minimal SOP expression is,
ZWXF +=
(b) Simplify the following Boolean functionsusing K-map.
(i) F(A, B, C) = A'B + B'C + A'B'C'
(ii) F(A, B, C) = A'B' + AC' + B'C + A'B'C'
Answer : April/May-12, Set-3, Q3(b)
(i) F(A, B, C) = A'B + B'C + A'B'C'
The given Boolean expression is,
F(A,B, C)=A'B +B'C+A'B'C'
By converting the given expression into a standard
sum of products form, we get,
F(A,B, C)=A'B(C+ C')+ (A +A')B'C+A'B'C'
=A'BC+A'BC' +AB'C+A'B'C+A'B'C'
= 011 + 010 + 101 + 001 + 000
= 3 + 2 + 5 + 1 + 0
F(A,B, C) =(0, 1, 2, 3, 5)
Loading the above expression into a 3-variable
K-map as shown in figure (1),
1 1 1 1
1
0 1 3 2
4 5 7 6
ABC
00 01 11 10
1
0 A
CB
1 1 1 1
1
0 1 3 2
4 5 7 6
ABC
00 01 11 10
1
0 A
CB
Figure (1): 3-variable K-map
Therefore, the required simplified expression is,
CBACBAF +=),,(
(ii) F(A, B, C) = A'B' + AC' + B'C + A'BC'
The given Boolean expression is,
F(A,B, C)=A'B' +AC' +B'C+A'BC'
By converting the above expression into a standardSOP form, we get,
F(A,B, C) =A'B'(C+ C') +A(B +B')C' + (A +A')B'C
+A'BC'
=A'B'C+A'B'C' +ABC' +AB'C' +AB'C
+A'B'C+A'BC'
= 001 + 000 + 110 + 100 + 101 + 001 + 010
= 1 + 0 + 6 + 4 + 5 + 1 + 2
F(A,B, C) =(0, 1, 2, 4, 5, 6)
Loading the above expression into a 3-variable
K-map as shown in figure (2),
1 1 1
1 1 1
0 1 3 2
4 5 7 6
ABC
00 01 11 10
1
0C
B
1 1 1
1 1 1
0 1 3 2
4 5 7 6
ABC
00 01 11 10
1
0C
B
Figure (2): 3-variable K-map
Therefore, the required simplified expression is,
CBCBAF +=),,(
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S.28 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Q4. (a) Implement full adder using 4*1 multiplexer.
Answer : April/May-12, Set-3, Q4(a)
Full Adder Operation using 4 to 1 Multiplexer
The block schematic representation of full adder is as shown in figure (1).
Full
Adder
S
Cout
A
B
Cin
Full
Adder
S
Cout
A
B
Cin
Figure (1)
The truth table of full adder is as shown in table (1),
11111
10011
10101
01001
10110
01010
01100
OutputInput
00000
CoutSCinBA
11111
10011
10101
01001
10110
01010
01100
OutputInput
00000
CoutSCinBA
Table (1): Truth Table of Full Adder
From the above table, the boolean functions of sum (S) and output carry (Cout
) can be obtained as,
S= {1, 2, 4, 7}
Cout
= {3, 5, 6, 7}
In order to implement a full adder, a 8 1 multiplexer is required. To implement the same full adder using 4 1
multiplexers, one input is considered as common to both 4 1 MUXs.
By consideringA as input,B and Cas selection lines, the implementation table of S and Cout
is given as,
For S = {1, 2, 4, 7}
I3I2I1I0
7654
3210
I3I2I1I0
7654
3210A'
A
A A' A' AMUX 1
Inputs
For Cout
= {3, 5, 6, 7}
I7I6I5I4
7654
3210
I7I6I5I4
7654
3210A'
A
0 A A 1MUX 2
Inputs
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S.29Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Then, the circuit arrangement of full adder using 4 1 mux is as shown in figure (2),
I0
I1
I2
I3
4 1
MUX
1
S
I4
I5
I6
I7
4 1
MUX
2
Cout
0
1
B Cin
A I0
I1
I2
I3
4 1
MUX
1
S
I4
I5
I6
I7
4 1
MUX
2
Cout
0
1
B Cin
A
Figure (2): Full Adder using 4 1 MUX
(b) Design 4*16 decoder using two 3*8 decoders with block diagram.
Answer : April/May-12, Set-3, Q4(b)
Realization of 4 16 Decoder with Two 3 8 Decoders
A 4 16 decoder can be constructed using two 3 8 decoders with enable input. This enable input acts as 4th input
to a 4 16 decoder which is directly given as enable signal to the decoder that generates higher order bits and is inverted
and given as an input to the other decoder.
D0
D1
D2
D3
D4
D5
D6
D7
3 8
Decoder
Enable
3 8
Decoder
I
D8
D9
D10
D11
D12
D13
D14
D15
I0
I3
I2
I1
Four inputslines
Lower
orderbits
16
outputlines
Higher
Orderbits
Enable
0
E0
E1
D0
D1
D2
D3
D4
D5
D6
D7
3 8
Decoder
Enable
3 8
Decoder
I
D8
D9
D10
D11
D12
D13
D14
D15
I0
I3
I2
I1
Four inputslines
Lower
orderbits
16
outputlines
Higher
Orderbits
Enable
0
E0
E1
Figure (2): Implementation of a 4 16 Decoder using Two 3 8 Decoders
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000
0
00
0
01
1
11
1
11
1
00
00
1
11
1
00
0
01
111
00
11
0
01
1
00
1
10
011
01
01
0
10
1
01
0
10
101
10
00
0
00
0
00
0
00
000
01
00
0
00
0
00
0
00
000
00
10
0
00
0
00
0
00
000
00
01
0
00
0
00
0
00
000
00
00
1
00
0
00
0
00
000
00
00
0
10
0
00
0
00
000
00
00
0
01
0
00
0
00
000
00
00
0
00
1
00
0
00
000
00
00
0
00
0
10
0
00
000
00
00
0
00
0
01
0
00
000
00
00
0
00
0
00
1
00
000
00
00
0
00
0
00
0
10
000
00
00
0
00
0
00
0
01
000
00
00
0
00
0
00
0
00
100
00
00
0
00
0
00
0
00
001
I0
I1
I2
I3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13 D15
Inputs Outputs
00
00
0
00
0
00
0
00
010
D14
000
0
00
0
01
1
11
1
11
1
00
00
1
11
1
00
0
01
111
00
11
0
01
1
00
1
10
011
01
01
0
10
1
01
0
10
101
10
00
0
00
0
00
0
00
000
01
00
0
00
0
00
0
00
000
00
10
0
00
0
00
0
00
000
00
01
0
00
0
00
0
00
000
00
00
1
00
0
00
0
00
000
00
00
0
10
0
00
0
00
000
00
00
0
01
0
00
0
00
000
00
00
0
00
1
00
0
00
000
00
00
0
00
0
10
0
00
000
00
00
0
00
0
01
0
00
000
00
00
0
00
0
00
1
00
000
00
00
0
00
0
00
0
10
000
00
00
0
00
0
00
0
01
000
00
00
0
00
0
00
0
00
100
00
00
0
00
0
00
0
00
001
I0
I1
I2
I3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13 D15
Inputs Outputs
00
00
0
00
0
00
0
00
010
D14
Table: Truth Table of 4 16 Decoder
When the inputI0
= 0, first 3 8 decoder is enabled that generates 8 outputsD0-D
7and the other decoder is disabled.
When the inputI0
= 1 first 3 8 decoder is disabled whose outputs are all zero and the other decoder is enabled that
generates the 8 outputs.D8-D
15.
Q5. (a) Explain the general combinational PLD configuration with suitable block diagram.
Answer : April/May-12, Set-3, Q5(a)
General PLD
PLDs are logic devices, which can be programmed by the user. Some PLDS are reprogrammable. The general
programmable devices depend on the disjunctive normal form i.e., sum of products form. The general structure of the
combinational PLD consists of AND and OR gates to represent any individual function. The combinational PLD structure
for a device with 2 inputs and 2 outputs is shown in figure.
+ +
A B
f1 f2
+ +
A B
f1 f2
Figure (i): General Combinational PLD
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S.31Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
In the above figure, left part of the circuit containing
only AND gates called as the AND matrix and a matrix of
OR gates only is called as OR matrix.
Depending on the architecture PLDs are classifiedinto three basic structures. they are,
(i) Programmable Read-only Memory (PROM)
(ii) Programmable Logic Array (PLA)
(iii) Programmable Array Logic (PAL).
For remaining answer refer Unit-V, Q3, Topics: (i), (ii),
and (iii).
(b) Give the logic implementation of a 32 4-bit and 8 4-bit ROM using suitabledecoder.
Answer : April/May-12, Set-3, Q5(b)
The 32 4-bit ROM and 8 4-bit ROM can be
implemented using 5 32 decoder and 2 4 decoder
respectively.
Logic Implementation of a 32 4-bit ROM using 5 32
Decoder
For answer refer Unit-V, Q2.
Logic Implementation of an 8 4-bit ROM using 2 to 4
Decoder
An 8 4 ROM or 23 4 ROM consists of 3 inputs and
4 outputs. The basic structure of 8 4 ROM is as shown in
figure (1).
A ddres sinputs
D ataoutputs2 3 4 R O M
A 0
A 1
A 2
X 0
X 1
X 2
X 3
A ddres sinputs
D ataoutputs2 3 4 R O M
A 0
A 1
A 2
X 0
X 1
X 2
X 3
Figure (1): Basic Structure of 8 4 ROM
The truth table of 23 4 ROM is as shown in table (1).
Inputs Outputs
A2 A1 A0 X3 X2 X1 X00 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Table (1)
The truth table for 2-to-4 decoder with an output
polarity control is same as that in table (1). Implementation
of this decoder using discrete logic gates is as shown in
figure (2),
Q0(X0)
Q1
(X1)
Q2
(X2)
Q3(X3)
I0(A0)
I1(A1)
POL(A2)
Q0(X0)
Q1
(X1)
Q2
(X2)
Q3(X3)
I0(A0)
I1(A1)
POL(A2)
Figure (2): 2-to-4 Decoder with Output-Polarity Control
Hence, a 2-to-4 decoder can be implemented in
following two ways,
(i) Using discrete logic gates and
(ii) Using 8 4 ROM.
The connections required to implement the 2-to-4
decoder using 8 4 ROM is as shown in figure (3).
8 4 ROM
A0
A1
A2
X0
X1
X2
X3
I0
I1
POL
Y0
Y1
Y2
Y3
8 4 ROM
A0
A1
A2
X0
X1
X2
X3
I0
I1
POL
Y0
Y1
Y2
Y3
Figure (3): Connections required to Implement the 2-to-4
Decoder Using 8 4 ROM
By altering the order of either rows or columns of thetruth table (provided in table (1)), different physical ROMs
are obtained. These new ROMs can be used to perform the
similar logic function. This can be accomplished by assigning
the signals of decoder to the inputs and outputs of different
ROM. Alternately, it can also be achieved by changing the
names of each address inputs and data outputs of ROM.
For instance, consider the swapping of the bits in the
columns X0 and X3 in table (1). This results in a different
physical ROM. The new ROM obtained still can be used in
implementing 2-to-4 decoder by just swapping the outputs
X0 and X3 labels in figure (3).
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S.32 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Anantapur )
Also, the ROM can be still used to implement 2-to-4 decoder if the data rows are shuffled completely as shown in
table (2).
The operation of this 3-input, 4-output combinational logic function (ROM) can be easily understood by truth table
as shown in below table.
Inputs Outputs
X Y Z A B C D
A2 A1 A0 X3 X2 X1 X0
0 0 0 1 1 1 0
0 0 1 0 0 0 1
0 1 0 1 1 0 1
0 1 1 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 1 0 0 1 1 1
1 1 1 1 0 0 0
Table (2)
It just requires the rearrangement of the address inputs such as,
(i) A0 = POL
(i) A1 = I0
(iii) A2 = I1.
Q6. (a) Draw the circuit diagram of 4-bit ring counter using D-flip-flops and explain its operation withthe help of bit pattern.
Answer : April/May-12, Set-3, Q6(a)
For answer refer Unit-VI, Q18.
(b) Distinguish between transition table and excitation table.
Answer : April/May-12, Set-3, Q6(b)
Difference between transition table and excitation table.
Transition Table Excitation Table
1. Transition table is a tabular representation of the 1. Excitation table is a tabular representation of the
transition and ouptut equations. excitation and output equations.
2. It consists of three sections, 2. It consists of three sections,
(i) Present-state section (i) Present state section
(ii) Next-state section (ii) Excitation section
(iii) Output section. (iii) Output section.
3. Present state of transition table consists of all the 3. Present state of excitation table provides all the
possible combinations of values for the state variables. possible combinations for the state variables.
4. Transition expressions are used to form the 4. Excitation expressions are used to form the excitation
next-state section of the transition table. section of the excitation table.
5. The entries in this section are p-tuples for each 5. The entries in this section are r-tuples for the
combination of present state and external input. respective combination evaluate the r-excitation
equations.
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At C
When the input is 0, the sequence will be 100 which is not a part of the required sequence. Hence, it shifts to state
A by producing 0 output to start a new detection. On the other hand, when the input is 1, the sequence will be 101
which is a part of the required sequence. Hence, it shifts to the stateD, by producing output 0.
At D
When the input is 0, the sequence will be 1010 which is not a required sequence. Hence, it shifts to state C, by
producing 0 output as overlapping is allowed. At state C, it uses the bits 10. On the other hand, when the input is
1, the sequence is 1011, which is a valid sequence. As the sequence is getting completed here, it produces the output
as 1 and shifts to state B to make use of last bit i.e., 1.
(b) The minimal state table of the state diagram is shown in table (1).
Present State Next State, Z
- X = 0 X = 1
A A, 0 B, 0
B C,0 B, 0
C A, 0 D, 0
D C, 0 B, 1
Table (1): State Table
Let, A = 00,B = 01, C= 10,D = 11
Then the transition table is obtained as shown in table (2).
Present State Next State (Y1, Y
2) Output (Z)
y1 y2 X = 0 X = 1 X = 0 X = 1
A 0 0 0 0 0 1 0 0
B0 1 1 0 0 1 0 0
C1 0 0 0 1 1 0 0
D
1 1 1 0 0 1 0 1Table (2): Transition Table
The truth table of aD-flipflop is shown in table (3).
Qn
Qn+1
D
0 0 0
0 1 1
1 0 0
1 1 1
Table (3)
The excitation table with the memory elements as D-flip flops is shown in table (4).
Present State Input Next State Flip-flop Inputs Output
Y1 Y2 X Y1 Y2 D1 D2 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0
1 1 0 1 0 1 0 0
1 1 1 0 1 0 1 1
Table (4)
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Simplification of D flip-flop inputs and output using K-map is shown in figure (2).
K-map for D1
0 1 3 21
115 7
y1
y2x00 01 11 10
0
1
xyxyyD 2211 +=
4 6
0 1 3 21
115 7
y1
y2x00 01 11 10
0
1
xyxyyD 2211 +=
4 6
K-map for D2
0 1 3 2
5 7
y1
y2x00 01 11 10
0
1
1
1
1
1
D2 = x
4 6
0 1 3 2
5 7
y1
y2x00 01 11 10
0
1
1
1
1
1
D2 = x
4 6
K-map for Z
0 1 3 2
15 7
y1y2x
00 01 11 10
0
1 6
Z = y1y2x
4
0 1 3 2
15 7
y1y2x
00 01 11 10
0
1 6
Z = y1y2x
4
Figure (2)
The implementation of the above expressions using D-flip-flops is shown in figure (2).
D1
y1y3x
CLK
y1
1y
D2
CLK
y2
2y
1
2
Z
x
CLK
x
D1
y1y3x
CLK
y1
1y
D2
CLK
y2
2y
1
2
Z
x
CLK
x
Figure (3): Circuit using D-Flip-flop
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S.36 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
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Q8. (a) For the given control state diagram obtain its equivalent ASM chart.
(b) Design control logic circuit using multiplexers for the given state diagram.
T0
T1
T2
S'S A3A4
A3A
4
A3
X
T0
T1
T2
S'S A3A4
A3A
4
A3
X
Answer : April/May-12, Set-3, Q8
The given state diagram of a control unit is shown in figure (1).
T0
T1
T2
S' S A3A4
A3A
4
A3
X
T0
T1
T2
S' S A3A4
A3A
4
A3
X
Figure (1): State Diagram
(a) Equivalent ASM Chart
There are three states in the above state diagram. They are T0, T
1and T
2.
Let these states be represented in binary code as follows,
T0
= 00
T1
= 01
T2
= 10
The equivalent ASM chart for the given state diagram is obtained as shown in figure (2).
T0 00
S
A3
A4
X
0
01T1
0
0
110T2
1
1
1
T0 00
S
A3
A4
X
0
01T1
0
0
110T2
1
1
1
Figure (2): ASM Chart
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(b) Design of Control Logic Circuit using Multiplexers
The state table of the given state diagram is shown in table (1).
X(1)T000T2102
A3A
4(10)
A3(0)
A3A
4(11)
T1
T1
T2
01
01
10
T1
011
S(0)
S(1)
T0
T1
00
01
T0
000
NameBinary
Assignment
NameBinary
Assignment
Condition
for
Transition
Present State Next State
S.No
X(1)T000T2102
A3A
4(10)
A3(0)
A3A
4(11)
T1
T1
T2
01
01
10
T1
011
S(0)
S(1)
T0
T1
00
01
T0
000
NameBinary
Assignment
NameBinary
Assignment
Condition
for
Transition
Present State Next State
S.No
Table (1): State Table
To design the control logic circuit for the given state diagram, two flip-flops say A and B and two 4 1 multiplexers
say 1 and 2 are required. The bit positions of the next state are considered as the inputs for multiplexers which generates
the flip-flop inputs as shown in table (2).
0 0
0
0 0
0
0 0
1 (S)
Condition oftransition
S
0 0
1 (S)
Condition oftransition
S
1 0
0
1 (A3 A4)
Condition of transition
A3 A4
1 0
0
1 (A3 A4)
Condition of transition
A3 A4
1
0
Condition of transition
A3 A4 + A3
1 (A3 A4)
1 (A3)
1
0
Condition of transition
A3 A4 + A3
1 (A3 A4)
1 (A3)
MUX 2 (Next state 2nd bits)MUX 1 (Next state 1st bits) MUX 2 (Next state 2nd bits)MUX 1 (Next state 1st bits)
2 02 0 2 02 0
Table (2)
00
A3A4 + A3A3A4
S0
MUX 2MUX 1
00
A3A4 + A3A3A4
S0
MUX 2MUX 1
0
1
2
3
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The realization of ASM chart using multiplexers D-flip-flops and 2 4 decoder is shown in figure (3).
0
1
2
3A B
0
1
2
3
A BS
Y
4 1MUX 1
DA
clkFF-A
QA
QA
A
A
DB
clkFF-B
QB
QB
BY
2 4
Decoder
B
T0
T1T2T3
4 1MUX 20
0
0A3A4
A3A4
A3
Clock
0
1
2
3A B
0
1
2
3
A BS
Y
4 1MUX 1
DA
clkFF-A
QA
QA
A
A
DB
clkFF-B
QB
QB
BY
2 4
Decoder
B
T0
T1T2T3
4 1MUX 20
0
0A3A4
A3A4
A3
Clock
Figure (3): Circuit Realization of ASM Chart