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EE M216A .:. Fall 2010Lecture 2

Scaling, MOS Transistor Models

Prof. Dejan Markovićee216a@gmail.com

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Today’s lectureTechnology scaling

D. Markovic / Slide 2

– Technology scaling– MOS transistor modeling

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 2

2

Technology Scaling is Power Driven

1970 1985 2000

Bipolar NMOS CMOS ???power wall power wall power wall

System performance has benefited from higher integrationSystem performance has benefited from higher integrationIn the mid 80’s, CMOS displaced NMOS technologies to address power dissipation– CMOS delivered better cost performance since it was more

energy efficient and improved the integration level– At that time CMOS was on the horizon

Replacing CMOS by another more energy efficient technology is a

D. Markovic / Slide 3

Replacing CMOS by another more energy efficient technology is a distant prospect now– Low‐power high‐speed CMOS technology is becoming an

indispensable, rather than desirable, technology– Power is the main challenge we need to address

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 3

The Limits

Theoretical PracticalSystem

Ci itCircuit

Device

Material

Theoretical limits: physicsPractical limits: + manufacturing cost

D. Markovic / Slide 4

Fundamental

[J. Meindl, Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 4

3

Circuit Limits

#1: logic levels (gain)

#2: energy/transition

#3: delay

#4: global interconnect

D. Markovic / Slide 5EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 5

Circuit Limit #1: Logic Levels (Gain)

Distinguish logic 0’s from 1’s (restore logic levels |gain| >1)

D. Markovic / Slide 6

[J. Meindl, Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 6

4

Circuit Limits (Cont.)

#2: Energy/transition– Neglecting static current

#3: Delay– Limited by

#4 Gl b l i t t

D. Markovic / Slide 7

#4: Global interconnect– Interconnect delay should not exceed gate delay

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 7

Practical Limits

Scaling towards fundamental limits

~130nm is the most cost‐effective technology (the last generation for whichdeep UV microlithographywill suffice)

D. Markovic / Slide 8

[J. Meindl, Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 8

5

Practical Limits (Cont.)

Metric: chip size

D = 40mmD = 50mm(16” wafer)

D = 40mm(12” wafer)

D = 25mm(8” wafer)

D. Markovic / Slide 9

[J. Meindl, Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 9

Practical Limits (Cont.)

Packing efficiency = # transistors / min feature area

3D / vertical integration

Layout density ↑

↑ # mask levels

D. Markovic / Slide 10

[J. Meindl, Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 10

6

Basic Scaling Trends

10000

Const VDD Const E General

Pentium ProPentium ®

4863862868086808510

100

1000

10000re

quen

cy (M

hz)

Doubles every2 years Pentium 4

D. Markovic / Slide 11EEM216A .:. Fall 2010

8080800840040.1

1

1970 1980 1990 2000 2010Year

F Source:S. Borkar(Intel)

Lecture 2: Scaling, MOS Transistor Models | 11

Constant Electric Field Scaling

Dimensions and voltages scale by the same factor (speed!)– Scaling voltage OK up to the point of leakage ↑↑↑ (exp−VTH)

D. Markovic / Slide 12

[B. Davari et al., Proc. IEEE, 1995]EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 12

7

Scaling Overview (Fixed V, Fixed E, General)

Parameter Relation Fixed V Sc. Fixed E Sc. General Sc.

W, L, tox 1/S 1/S 1/S

VDD, VT 1 1/S 1/U

Area/Device WL 1/S2 1/S2 1/S2

Cox 1/tox S S S

Cgate Cox WL 1/S 1/S 1/S

kn, kp Cox W/L S S S

Isat Cox WV 1 1/S 1/U

Current Density Isat / Area S2 S S2/U

D. Markovic / Slide 13EEM216A .:. Fall 2010

y sat / /

Ron V / Isat 1 1 1

Intr. Delay Ron Cgate 1/S 1/S 1/S

Power Isat V 1 1/S2 1/U2

P Density Power/Area S2 1 S2/U2

Lecture 2: Scaling, MOS Transistor Models | 13

High‐Performance and Low‐Power Flavors

D. Markovic / Slide 14

[B. Davari et al., Proc. IEEE, 1995][Source: T. Kuroda]EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 14

8

Reaching the Power Density Limit

HS: out of the gameIssues with LP– Soft‐errors getting worse

with low V andwith low VDD and reduced cap

– Lower limit on VTH

(leakage)– Multi VTH, multi VDD

running out of gas

D. Markovic / Slide 15

Const E

VT ~ 0.3VVDDmin

Multi-core

[B. Davari et al., Proc. IEEE, 1995]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 15

MOS Transistor Modeling

Many levels– Hand analysis– CAD analysis (e.g. Matlab)

S it h l l l i ( P i Ti )– Switch‐level analysis (e.g. PrimeTime)– Circuit simulation (e.g. Spectre, HSPICE)

These levels have different requirements in complexity, accuracy, and speed of convergence

W i il i d i d l d d li h

D. Markovic / Slide 16

We are primarily interested in delay and energy modeling, rather than current modeling (but have to start from the currents)…

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 16

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MOSFET, Notations

D. Markovic / Slide 17EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 17

General I‐V Characteristic (Qualitative View)

D. Markovic / Slide 18EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 18

10

G

for VGT ≤ 0 (sub-VTH):

define VGT = VGS – VT

Universal MOS I‐V Model

B

DID

SGT ( TH)

for VGT ≥ 0 (Lin, Sat, V-Sat):

D. Markovic / Slide 19

with

LinSat V-Sat

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 19

Important Concepts to Understand

Threshold voltage (review EE115C / lecture 2)Channel length modulation (channel pinch‐off)Velocity saturation

D. Markovic / Slide 20EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 20

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Modeling Channel Length Modulation (CLM)

Many empirical models– Goal: get a simple model that is convenient for hand analysis– Here is a possible modeling approach:

D. Markovic / Slide 21EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 21

CLM Model

D. Markovic / Slide 22EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 22

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Important Concepts to Understand

Threshold voltageChannel length modulation (channel pinch‐off)Velocity saturation

D. Markovic / Slide 23EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 23

Including Velocity Saturation

Approximate velocity:

for ξ ≤ ξc

A more general model:

for ξ ≥ ξc we use n = 1

And integrate current again:

D. Markovic / Slide 24EEM216A .:. Fall 2010

In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation

Lecture 2: Scaling, MOS Transistor Models | 24

13

Including Velocity Sat. in the ID Formula

D. Markovic / Slide 25EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 25

Saturation vs. Velocity Saturation

V‐Sat occurs for lower VDS than Sat

D. Markovic / Slide 26EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 26

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Another Look at Velocity Saturation

V‐Sat happens before Sat (for large VGS)

IDL h l d iLong‐channel device

Short‐channel device

VGS = VDD

D. Markovic / Slide 27EEM216A .:. Fall 2010

VDSVDSAT VGS - VT

Lecture 2: Scaling, MOS Transistor Models | 27

ID vs. VGS (Assume VDS > VGS – VT > 0)

Short channel can be Sat for small VGS

6x 10-4

Long Channel

2

4

5g

(always Sat)

Short Channel( )

Quadratic(Sat)I D

(A)

3

D. Markovic / Slide 28EEM216A .:. Fall 2010

0 0.5 1 1.5 2 2.50

1

2 (Sat or V‐Sat)

Quadratic(Sat)

Linear(V-Sat)

VGS (V)

smallVGS

largeVGS

Lecture 2: Scaling, MOS Transistor Models | 28

15

Long vs. Short Channel (Simulation Data)

90nm device, constant W/L ratio− Long Channel: W/L = 2.4µm/0.5µm− Short Channel: W/L = 480nm/100nm

gpdk090

Observations

VGS=1V

VGS=0.8V

V 0 6V

L=500nmL=100nm

Observations− Short L (100nm) has

larger impact of CLM on ID

− Linear separation of V‐Sat curves (red), quadratic for Sat

D. Markovic / Slide 29

VGS=0.6V

VGS=0.4V

quadratic for Sat (blue)

− ID(V‐Sat) < ID(Sat) at large VGS

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 29

MOS Regions of Operation

Nano‐scale MOS devices operate in velocity saturation– Saturation still possible for low VGS values (up to VDSAT)

D. Markovic / Slide 30EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 30

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Unified Formula for the Drain Current

Many modes of operation can be nicely captured with a single formula:

D. Markovic / Slide 31EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 31

Unified Model: Observations

CLM term (1 + λVDS) also included for linear region– Empirical, not grounded in physical considerations

Five parameters: V γ V k’ λFive parameters: VT0, γ, VDSAT, k , λ– Can determine from physics– Or choose values that best match simulation data

(match the best in regions that matter the most)– Use different model for L >> Lmin

(we assume L = Lmin unless otherwise specified)

D. Markovic / Slide 32

Let’s see how to extract these key parameters from the I‐V curves

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 32

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The Meaning of Model Parameters

D. Markovic / Slide 33EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 33

Alpha‐Power‐Law Model

Alternate approach, useful for hand analysis– Works better for delay than current

Empirical model− Curve fitting (MMSE)− α is between 1 and 2

D. Markovic / Slide 34

[T. Sakurai, R. Newton, JSSC, Apr. 1990]

− In 90nm, it is about 1.4(note: depends on VT)

• Can fit to α = 1, but with what VT?

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 34

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Second Order Effects

Drain Induced Barrier Lowering (DIBL)

Reverse Short Channel Effect (RSCE)

Narrow Width Effects (NWE)

Hot Carriers (HC)

D. Markovic / Slide 35EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 35

Drain Induced Barrier Lowering (DIBL)

D. Markovic / Slide 36EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 36

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VT

Long‐channel threshold

VT

Threshold Variations

Low VDS threshold

L

Threshold as a function ofchannel length (for low VDS)

VDS

Drain induced barrier lowering (DIBL) (for low L)

D. Markovic / Slide 37

g ( DS) ( ) ( )

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 37

DIBL and RSCE

RSCE is typical in today’s processes– Tradeoff between leakage power and performance

D. Markovic / Slide 38EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 38

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The Hot Carrier (HC) Effect

Gets worse with technology scaling (shorter L)

D. Markovic / Slide 39EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 39

HC Effect Shows up Over Time

Current drops over time due to HC

D. Markovic / Slide 40EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 40

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Sub‐threshold Current

This is another topic of crucial importance in digital design– We need to consider sub‐threshold current, because digital

designs have many millions of transistors and when these are inactive we may get some lots wasted powerinactive, we may get some lots wasted power…

D. Markovic / Slide 41EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 41

Sub‐threshold ID versus VGS is Exponential

5

6x 10-4

Long Channel

2

4

Short Channel

quadratic

I D(A

)

3

Sub-threshold

D. Markovic / Slide 42EEM216A .:. Fall 2010

0 0.5 1 1.5 2 2.50

1quadratic

linear

VGS (V)

exp

Lecture 2: Scaling, MOS Transistor Models | 42

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Modeling the Sub‐threshold Behavior

D. Markovic / Slide 43EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 43

The Sub‐threshold Slope Parameter

Meaning: change in VGS that gives 10x change in IDS

D. Markovic / Slide 44EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 44

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Sub‐threshold ID vs. VGS

Physical model

Empirical model DIBL

D. Markovic / Slide 45

[mV/dec]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 45

Example (90nm): Sub‐threshold ID vs. VGS

90mV/dec

V from 0 to 0 4V

NMOSPMOS gpdk090

10

D. Markovic / Slide 46

VDS from 0 to 0.4V

W/L=480nm/100nm W/L=240nm/100nm

10x90mV

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 46

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Example (90nm): Sub‐threshold ID vs. VDS

V from 0 to 0 3V

NMOSPMOS

gpdk090

D. Markovic / Slide 47

VGS from 0 to 0.3V

W/L=480nm/100nm W/L=240nm/100nm

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 47

Stack Effect

Transistor stacks greatly reduce leakage

NAND gate

D. Markovic / Slide 48

Leakagepower

reduction

[IEEE Press, New York, 2000]

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 48

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Simple Model vs. SPICE Simulation

Transition between lin/v‐sat has the largest modeling error

2.5x 10

-4 VDS=VDSAT

i l ti

1

1.5

2VelocitySaturation

Linear

simulationmodel

I D(A

)

D. Markovic / Slide 49EEM216A .:. Fall 2010

0 0.5 1 1.5 2 2.50

0.5

Saturation

VDSAT=VGT

VDS=VGT

VDS (V)

Lecture 2: Scaling, MOS Transistor Models | 49

Weak Inversion (a.k.a. VT + ∆V Region)

Current model– Starts from IS (weak inversion),

22S ox tWI n CL

µ φ= ⋅ ⋅ ⋅ ⋅L

– goes down to Sub‐VT,DD T

t

V Vn

Leakage SI I eσ

φ⋅ −

⋅= ⋅

– and Above‐VT

DS SI I IC= ⋅Inversion Coefficient (IC) indicates proximity to VT

Check: The models are likely off at VT

(i.e. IC < 1 doesn’t model sub‐VT well)

D. Markovic / Slide 50EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 50

T

– IC < 1 (Sub‐VT), IC = 1 (@ VT), IC > 1 (Above‐VT)– Range of IC: up to 100 (strong inv), down to 1/100 (sub‐VT)

( ) 21

2ln 1DD T

t

V VnIC e

σφ

+ ⋅ −⋅ ⋅

= +

( )2 ln 1

1

ICT t

DD

V n eV

φ

σ

+ ⋅ ⋅ ⋅ −=

+

26

Fitting the IC Parameter

You can constrain MMSE‐based curve fit such that IC = 1 @ VT– Convenient expression, no physical reasoning

65nm process65nm process

D. Markovic / Slide 51EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 51

Actual gpdk090 Model (gpdk090_mos.scs)

section TT_s1vparameters + s1v_rs_ne = 0.000000e+000 s1v_vsat_ne = 1.120000e+005 s1v_pldd_surf = 6.000000e+019 + s1v_uc1_ne = 3.700000e‐010 s1v_u0_ne = 2.000000e‐002 s1v_nch_ne = 5.200000e+017 + s1v_rsc_ne = 4.082483e‐014 s1v_cgbo_ne = 1.482000e‐011 s1v_prt_ne = 1.000000e+001 + s1v_rdc_ne = 4.082483e‐014 s1v_vth0_ne = 1.692662e‐001 s1v_k2_ne = 0.000000e+000 + s1v cgdo ne = 2 667600e‐010 s1v ckappa ne =4 605336e+000 s1v wint ne = 6 000000e‐009+ s1v_cgdo_ne = 2.667600e 010 s1v_ckappa_ne =4.605336e+000 s1v_wint_ne = 6.000000e 009 + s1v_k1_ne = 2.825346e‐001 s1v_cgsl_ne = 1.111500e‐010 s1v_nldd_surf = 3.000000e+019 + s1v_js_ne = 3.366667e‐006 s1v_hdif_ne = 1.400000e‐007 s1v_rdsw_ne = 3.900000e‐006 + s1v_jsw_ne = 3.366667e‐010 s1v_tox_ne = 2.330000e‐009 s1v_cj_ne = 7.983537e‐004 + s1v_cjsw_ne = 4.790122e‐011 s1v_ldif_ne = 1.000000e‐008 s1v_xj_ne = 2.500000e‐008 + s1v_rd_ne = 0.000000e+000 s1v_pb_ne = 9.918524e‐001 s1v_cf_ne = 4.594612e‐011 + s1v_lint_ne = 1.500000e‐008 s1v_cjswg_ne = 1.995884e‐011 s1v_rsh_ne = 1.000000e+001 + s1v_u0_pe = 1.200000e‐002 s1v_nch_pe = 4.000000e+017 s1v_rsc_pe = 2.886751e‐014 + s1v_cgbo_pe = 1.392363e‐011 s1v_rdc_pe = 2.886751e‐014 s1v_vth0_pe = ‐1.359511e‐001 + s1v_k2_pe = 0.000000e+000 s1v_cgdo_pe = 2.506253e‐010 s1v_ckappa_pe = 1.043477e+001 + s1v_wint_pe = 5.000000e‐009 s1v_k1_pe = 2.637520e‐001 s1v_cgsl_pe = 1.044272e‐010 + s1v_js_pe = 3.350000e‐006 s1v_hdif_pe = 1.400000e‐007 s1v_rdsw_pe = 7.800000e‐006 + s1v jsw pe = 3 350000e‐010 s1v tox pe = 2 480000e‐009 s1v cj pe = 7 912252e‐004

D. Markovic / Slide 52

+ s1v_jsw_pe = 3.350000e‐010 s1v_tox_pe = 2.480000e‐009 s1v_cj_pe = 7.912252e‐004 + s1v_cjsw_pe = 4.747351e‐011 s1v_ldif_pe = 1.000000e‐008 s1v_xj_pe = 2.500000e‐008 + s1v_rd_pe = 0.000000e+000 s1v_pb_pe = 1.009805e+000 s1v_cf_pe = 4.527118e‐011 + s1v_lint_pe = 1.500000e‐008 s1v_cjswg_pe = 1.978063e‐011 s1v_rsh_pe = 2.000000e+001 + s1v_rs_pe = 0.000000e+000 s1v_vsat_pe = 1.000000e+005 include "gpdk090_mos.scs" section = s1v_mosendsection TT_s1v next slide…

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 52

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GPDK090 Model (section s1v_mos)section s1v_mosmodel gpdk090_nmos1v bsim3v3 type = n + lmin = 0.0 lmax = 1.0 wmin = 0.0 + wmax = 1.0 tnom = 25.0 version = 3.2 + tox = s1v_tox_ne toxm = s1v_tox_ne xj = s1v_xj_ne + nch = s1v_nch_ne lln = 1.0000000 lwn = 1.0000000 + wln = 1.0000000 wwn = ‐1.0000000 lint = s1v_lint_ne + ll = 0.00 lw = 0.00 lwl = 0.00 + wint = s1v_wint_ne wl = 0.00 ww = 0.00 + wwl = 0.00 mobmod = 1 binunit = 2 + xl = 0 xw = 0 dwg = 0.00 + dwb = 0.00 acm = 12 ldif = s1v_ldif_ne + hdif = s1v_hdif_ne rsh = s1v_rsh_ne rd = s1v_rd_ne + rs = s1v_rs_ne rsc = s1v_rsc_ne rdc = s1v_rdc_ne + vth0 = s1v_vth0_ne k1 = s1v_k1_ne k2 = s1v_k2_ne + k3 = ‐2.3000000 dvt0 = 3.86366 dvt1 = 1.2 + dvt2 = 5.0299990E‐02 dvt0w = 0.00 dvt1w = 0.00 + dvt2w = 0.00 nlx = 1.2517999E‐07 w0 = ‐7.1353000E‐09 + k3b = 0.5576769 ngate = 4.0E20 vsat = s1v_vsat_ne

D. Markovic / Slide 53

g _ _+ ua = ‐6.1879500E‐10 ub = 1.8806652E‐18 uc = 1.3823546E‐10 + rdsw = s1v_rdsw_ne prwb = 0.00 prwg = 0.00 + wr = 1.0000000 u0 = s1v_u0_ne a0 = 2.3750000 + keta = ‐3.1429991E‐02 a1 = 0.00 a2 = 0.9900000 + ags = 0.8900000 b0 = 0.00 b1 = 0.00

And many more parameters... (compare to our 5‐parameter model)

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 53

Spectre Netlist (NMOS, PMOS)

section s1v_macsubckt s1v_ckt_nch (n11 n2 n33 n4)parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_ne/factor/w nrs=s1v_hdif_ne/factor/w+ Tox_ratio = 3.0e‐9 / (s1v_tox_ne*s1v_tox_ne*s1v_tox_ne)MAIN (n1 n2 n3 n4) gpdk090_nmos1v w=w l=l nrd=nrd nrs=nrs multi=multiGDF1 (n2 n1) bsource i = w*0.6*s1v_xj_ne*4.97232*Tox_ratio*v(n2,n1)*v(n2,n3)*exp(‐4.85669e11*s1v_tox_ne*…GDF2 (n2 n3) bsource i = w*0 6*s1v xj ne*4 97232*Tox ratio*v(n2 n3)*sqrt( (v(n2 n3) ‐ 0 026*log(4 0e20GDF2 (n2 n3) bsource i = w 0.6 s1v_xj_ne 4.97232 Tox_ratio v(n2,n3) sqrt( (v(n2,n3) 0.026 log(4.0e20 …20 / s1v_nldd_surf)) + 1.0e‐4 )*exp(‐4.85669e11*s1v_tox_ne*(0.43‐0.054*sqrt( (v(n2,n3) ‐ 0.026*log(4.0e20 ….0e20 / s1v_nldd_surf)) + …‐ 0.026*log(4.0e20 / s1v_nldd_surf))*(v(n2,n3) …s1v_nldd_surf)) + 1.0e‐4 )))rdn (n1 n11) resistor r= 6.8 *nrd/multirsn (n3 n33) resistor r= 6.8 *nrs/multiends s1v_ckt_nch

subckt s1v_ckt_pch (p11 p2 p33 p4)parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_pe/factor/w nrs=s1v_hdif_pe/factor/w+ Tox_ratio = 3.0e‐9/(s1v_tox_pe*s1v_tox_pe*s1v_tox_pe)MAIN (p1 p2 p3 p4) gpdk090_pmos1v w=w l=l nrd=nrd nrs=nrs multi=multiGDF1 (p2 p1) bsource i = w*0.6*s1v_xj_pe*3.42537*Tox_ratio*v(p2, p1)*sqrt( (v(p2, p1)‐

0 026*log(9 32E19/s1v pldd surf))*(v(p2 p1)‐0 026*log(9 32E1

D. Markovic / Slide 54

0.026 log(9.32E19/s1v_pldd_surf)) (v(p2, p1) 0.026 log(9.32E19/s1v_pldd_surf)) + 1.0e‐4 )*exp(‐7.0645e11*s1v_tox_pe*(0.31‐0.024*sqrt( (v(p2, p1)‐

0.026*log(9.32E19/s1v_pldd_surf))*(v(p2, p1)‐0.026*log(9.32E19… s1v_pldd_surf)) + 1.0e‐4 ))*(1.0+0.03*sqrt( (v(p2, p1)‐0.026*log(9.32E19/s1v_pldd_surf))*(v(p2, p1)‐0.026*log(9.32E19/s1v_pldd_surf)) + 1.0e‐4 )))

GDF2 (p2 p3) bsource i = w*0.6*s1v_xj_pe*3.42537*Tox_ratio*…sqrt( (v(p2, p3)‐…0.026*log(9.32E19/…)) + 1.0e‐4 )))rdp (p1 p11) resistor r = 7.1 * nrd / multirsp (p3 p33) resistor r = 7.1 * nrs / multiends s1v_ckt_pchendsection s1v_mac

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 54

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MOSFET Behavior: Summary

MOS transistor has 4 terminals (the 4th being the sub/body)– Body does not conduct significant current, but impacts

performance (impacts VT)The current in Saturation depends on VThe current in Saturation depends on VDS

– Especially as length is being scaled down with each generation– CLM: the effective channel L is actually a function of the VDS

– Drain‐induced barrier lowering (DIBL)● High EDS must have an effect: VT reduces as drain voltage increases

Velocity saturationCh l i h i i h hi h E

D. Markovic / Slide 55

– Charge velocity reaches a maximum with high EDS

Subthreshold current– Small amount of current still trickles when VGS < VT

Weak‐inversion– Near‐VT operation, crucial for ultra‐low‐power design

EEM216A .:. Fall 2010 Lecture 2: Scaling, MOS Transistor Models | 55

References (Classwiki)

G. Moore, Cramming More Components Onto Integrated Circuits, vol. 38, no. 8, Electronics, Apr 1965.J. Meindl, Low Power Microelectronics: Retrospect and Prospect, Proceedings of the IEEE, April 1995.B. Davari, R.H. Dennard, G.G. Shahidi, CMOS Scaling for High Performance and Low Power ‐ The Next Ten Years, Proceedings of the IEEE, April 1995.S. Borkar, Design challenges of technology scaling, IEEE Micro, vol.19, no.4, pp. 23‐29, July‐Aug. 1999.S. Chou, Innovation and Integration in the Nanoelectronics Era, Proceedings ISSCC 2005, Feb. 2005.T. Skotnicki, J.A. Hutchby, T‐J. King, H.‐S.P. Wong, and F. Boeuf, The End of CMOS S li T d th I t d ti f N M t i l d St t l

D. Markovic / Slide 56

CMOS Scaling: Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance, IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16‐26, Jan‐Feb. 2005.ITRS Roadmap ‐‐ Process Integration, Devices, and StructuresR. Bryant et al., Limitations and Challenges of Computer‐Aided Design Technology for CMOS VLSI, Proceedings of the IEEE, vol. 89, no. 3, Mar 2001.

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