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School of Electrical Engineering, Seoul National University SMDL Annual ’99
Scaling Characteristics of logic cells: Pass-Transistor logicVersus CMOS logic
Kyoung Hwa Lee ([email protected])
Abstracts-Scaling Characteristics are compared on some basic logic cells that are 2-input multiplexer and 2-input NAND of CMOS logic and Pass-Transistor Logic (PTL). SPICE simulation reveals that PTL is superior toCMOS logic in speed and power dissipation. 2-input multiplexer using PTL has a better power-delay product of20% less than that of the CMOS version. 2-input NAND implemented by PTL, which shows less superiority thanthat of 2-input MUX has a power-delay product of 15% less than that by CMOS logic. A comprehensive simulationis carried out to predict device performance as device size and supply voltage is scaled down. This paper employesmodified scaling method to investigate scaled device performance. With scaled MOS transistor model, thesuperiority of PTL is reduced but maintained the outperformance over CMOS logic, which guarantees PTL ispreferable if low power and high speed, resulting in high performance is necessary in the future device operationregime of deep sub 0.1µm.
I. INTRODUCTION
HE requests of low power and high speed can beaddressed at different design level such as
architecture, circuit, layout, and process technology level.This paper is targeted at the circuit level because manyimportant parameters governing power dissipation, i.e.supply voltage, switching capacitance, transition activity,and short circuit current, are strongly influenced by thelogic style.
A major category of classifying the logic style isdynamic logic and static logic. Dynamic logic is clockedand works in two phase-precharge and evaluation. Thislogic has small input capacitance and fast evaluation time,but the precharge mechanism needs high power due toadditional clock loads. So logic style discussion of thispaper will be confined in static logic especially atcombination logic component.
According to the power dissipation formula [1]
d
ddndelay
n nscddnnclkdddyn
I
VC
iVCfVP
⋅=
∑ ∑+⋅⋅⋅=
τ
α2
low power and high speed are achieved mainly byreducing supply voltage Vdd, the switching nodecapacitance Cn(by the number and size of transistors).
There are following candidates for thesequalifications.
A. Complementary CMOS logic
Conventional or complementary CMOS logic is builtfrom NMOS full-down and PMOS pull-up network. Anylogic gates can be realized by these connection of NMOSand PMOS with a few transistors. The advantages ofCMOS logic are its reliability at the low supply voltagewith the arbitrary transistor sizing. However the bestperformance of CMOS logic device can be achieved withlarge PMOS/NMOS width ratio of about 1.5~2, so largePMOS current results in higher power consumption
compared with that of NMOS network.
B. Pass-Transistor Logic
The major differences of the pass-transistor logic(PTL) compared with CMOS logic is that the source side(or drain) is connected to some input signals instead of thepower lines. The advantage of PTL is that only one PTLnetwork (either NMOS or PMOS) is sufficient to performthe logic operation, which results in smaller number oftransistors and smaller input loads, especially whenNMOS network is used. However, the threshold voltagedrop (Vout=Vdd-Vtn) through the NMOS transistor passinglogic ‘HIGH’ makes swing (level) restoration necessary.Another problem of PTL is its input and output signalcoupling. Therefore in order to decouple the signals and toprovide acceptable output drive capability inverter must beattached to the gate output.
II. SCALING THEORY
As silicon technology continues its downward pathtoward the deep sub micron regime, this dimensionreduction affects on the electrical circuit behavior. In spiteof MOS device dimension reduction, in order to maintainthe desirable properties of the long channel device, someMOS scaling methods were devised [2].
Constant electric field MOS scaling theory (CE) is anideal method only to applying scaling factor λ to all thedevice parameter . For CE, one of the important factors tobe noted is that since the voltage is scaled, electric field inthe device remains constant. It is desirable that manynonlinear factors (for example, mobility) remainunaffected. Alternative scaling method that has been usedpractically over the last few years is constant voltagescaling theory (CV). With CV, electric field increases,which causes mobility to decrease so gate delay does notimprove as much as the expected factor λ2, and the supplyvoltage is maintained, which has led the power density todeteriorate one also. This paper employes modified
T
School of Electrical Engineering, Seoul National University SMDL Annual ’99
scaling method which utilizes another voltage scalingfactor κ to meet the different voltage scaling tendency bychange κ variously with geometric scaling factor λ. Thesescaling theories are summarized in table 2.
III.CIRCUIT ARRANGEMENT AND
SIMULATION CONDITION
Various investigations of logic styles with respect tohigh performance circuits have been recently carried out.In these investigations, complementary pass-transistorlogic (CPL) or related PTL are addressed as low powerlogic styles. SEC middle term project report can bereferred to offer the general comparison of various logiccell implemented by CMOS logic and PTL logicrespectively [3]. This is recalled for convenience in table 2.
The first comparison of this paper is carried out on 2-input multiplexer which is on behalf of the suitable logiccell for PTL. The second is on 2-input NAND that isknown to be suitable for CMOS logic.
Figure 1. illustrates the circuit arrangement forsimulation of 2-input multiplexer and 2-input NAND gate.Circuits were designed in transistor level in the standard0.35µm CMOS device. NMOS transistor that is used as abaseline for the subsequent simulation has 0.17µmeffective channel length, 6nm gate oxide thickness, 0.48Vthreshold voltage and PMOS transistor has 0.16µmeffective channel length, 6.2nm gate oxide thickness,0.43V threshold voltage.
For simulation, geometric linear dimension parameterincluding oxide thickness, channel length, and channelwidth are scaled by the same factor from effective channellength 0.17µm to 0.10µm. The supply voltage is five stepscaled down from 3.5V to 1.5V by 0.5V. The channelwidth of NMOS and PMOS are delicately determinedrespectively to have the same transient rising and fallingtime of 200psec. The logic cells are expected to drive500fF load that is equivalent to 400µm width MOScapacitor. The load is scaled the same level as MOStransistor of the cell circuit. Threshold voltage are scaledthe same amount as supply voltage. HSPICE simulationare carried out in LEVEL=28. HSPICE parameters arespecifically adapted to model short channel effectconsidering mobility reduction and saturation voltagechange due to the gate and drain field in deep sub-microndevices.
VI. ANALYSIS OF SIMULATION RESULTS
The simulation results are given in figure 2. It showsPTL has better power delay product (PDP) due to theefficient structure containing fewer transistors.
2-input multiplexer and 2-input NAND designed byPTL save PDP by 15~20%. However the superiority ofPTL becomes less prominent as effective channel length isreduced near the 0.1µm region, where the carrier drift
velocity in NMOS and PMOS transistor are almost equaldue to the velocity saturation. This makes PTL lose itsadvantage of NMOS only network. But supply voltagescaling down decreases gate and drain field, which defersthe velocity saturation of electron and enables NMOSmaintain good current drive capability over PMOS.
V. CONCLUSION
PTL performance improvement as an alternative lowpower high speed logic over CMOS logic is proved bytwo representative logic cells, 2-input multiplexer and 2-input NAND, using SPICE simulation. The results suggestthat the logic cell or circuits including multiplexerstructured, i.e. full adder or multiplier, can beimplemented using PTL and simple gate usingNAND/NOR can be composed by CMOS logic or PTL.
The superiority of PTL is reduced as scaling down todeep sub-micron area. This can be explained that theelectron velocity saturation causes NMOS performance tobe deteriorate to the level of PMOS and consequently onlyNMOS network is not advantage any longer. But supplyvoltage scaling with proper geometric scaling broadens thepossible scaling down range where NMOS transistorperforms better than PMOS transistor. AND the morestudy of efficient circuit design methodology using PTLwill offer its ease-of-use and by these the characteristics ofPTL remain profitable if low power/high speed, resultingin high performance is necessary in the future deviceregime of deep sub-0.1µm operation..
REFERENCE
[1] R. Eimmermann amd W. Fichtner, “Low Power LogicStyles : CMOS Versus Pass-Transistor logic”, JSSC,vol.32, No. 7, pp. 1079-1090, July, 1997.
[2] N. H. E. Weste and K. Eshranghian, Principles ofCMOS VLSI Design, Addison-Wesley, 1994.
[3] J. D. Lee, Y. J. Yoon and K. H. Lee, SEC middle termProject Report, SMDL of SNU, 1999.
School of Electrical Engineering, Seoul National University SMDL Annual ’99
1/Scaling factorCE CV MS
Lineardimension 1/λ 1/λ 1/λ
Potential 1/λ 1 1/κImpurity conc. λ λ λElectric field 1 λ λ/κCapacitance 1/λ 1/λ 1/λCurrent 1/λ λ λ/κ2
Power 1/ λ3 1/λ 1/ (λκ2)Gate delay λ 1 κPower× delay 1/λ2 1/λ 1/(λκ)
Table 1. Scaling theory
PDP(fJ) MUX2
NAND2 XOR MUX
4AND
4
CMOS 57.8 26.1 56.0 49.8 57.7
CPL 47.4 25.7 25.7 34.9 34.0
Table 2. PDP(fJ) of many simple logic cells@Vdd=3.0V , T=60°C
A
S
S
A
B
S
S
O
O
A
S
S
A
B
S
S
B
O
(a)
S
A
S
B
S
A
S
O
B
O
(c)
A
A
B
B
OA
A
B
B
O
(b) A
B
A
A
A
B
A
O
A
O
(d)
Fig.1.Circuit arrangement (a)CMOS type 2-input multiplexer (b)CMOS type 2-inputNAND (c)PTL type 2-input multiplexer (d)PTL type 2-input NAND
0
200
400
600
800
1000
1200
3.53.0
2.5
2.0
1.50.102
0.1190.136
0.1530.170
Ene
rgy(
fJ)
Supp
ly V
olta
ge(V
)
Effective Channel Length(µm)
0
200
400
600
800
1000
1200
3.53.0
2.5
2.0
1.50.102
0.1190.136
0.1530.170
Ene
rgy(
fJ)
Supp
ly V
olta
ge(V
)
Effective Channel Length(µm)
0.76
0.78
0.80
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
0.98
3.53.0
2.52.0
1.5
0.1020.119
0.1360.153
0.170
Supply Voltage(V) Effe
ctiv
e Cha
nnel
Len
gth(
µm)
0
100
200
300
400
500
600
3.53.0
2.5
2.0
1.50.102
0.1190.136
0.1530.170
Ene
rgy(
fJ)
Supp
ly V
olta
ge(V
)
Effective Channel Length(µm)
0
100
200
300
400
500
600
3.53.0
2.5
2.0
1.50.102
0.1190.136
0.1530.170
Ene
rgy(
fJ)
Supp
ly V
olta
ge(V
)
Effective Channel Length(µm)
(a) (b)
(d) (e) (f)
(c)
0.76
0.78
0.80
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0.84
0.86
0.88
0.90
0.92
0.94
0.96
0.98
3.53.0
2.52.0
1.5
0.1020.119
0.1360.153
0.170
Supply Voltage(V) Effe
ctiv
e Cha
nnel
Len
gth(
µm)
Fig. 2. PDP of (a) CMOS type 2-input multiplexer (b) PTL type 2-inputmultiplexer (c) normalization of (b) by (a) (d) CMOS type 2-inputNAND (e) PTL type 2-input NAND (f) normalization of (e) by (d)
