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Pass Transistor Pass Transistor Logic Logic

Pass transistor logic

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Page 1: Pass transistor logic

Pass Transistor Pass Transistor LogicLogic

Page 2: Pass transistor logic

AgendaAgenda

Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies

Page 3: Pass transistor logic

Pass Transistor Logic Pass Transistor Logic CircuitsCircuits nMOS Pass transistor – transmission

properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 4: Pass transistor logic

nMOS Pass Transistor – Logic ‘1’ nMOS Pass Transistor – Logic ‘1’ TransferTransfer

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nMOS Pass Transistor – Logic nMOS Pass Transistor – Logic ‘0’ Transfer‘0’ Transfer

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Page 7: Pass transistor logic

PASS TRANSISTORS IN SERIES

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PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 9: Pass transistor logic

TRANSMISSION GATESTRANSMISSION GATES

NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

Page 10: Pass transistor logic

TRANSMISSION GATETRANSMISSION GATE

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PROBLEMS WITH PROBLEMS WITH TRANSMISSION GATESTRANSMISSION GATES

No isolation between the input and output. Output progressively deteriorates as it passes through

various stages. However designs get simplified.

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TRANSMISSION GATE - LAYOUTTRANSMISSION GATE - LAYOUT

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PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

Page 14: Pass transistor logic

MultiplexorMultiplexor

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Pass Transistor Logic CircuitsPass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

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XOR gateXOR gate

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PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

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D – Latch D – Latch

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TIMING ISSUESTIMING ISSUES

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D LATCHD LATCH

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D - LATCHD - LATCH

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D LATCH – ALTERNATE CIRCUIT TOPOLOGY

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PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

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Static Flip FlopStatic Flip Flop

0

1

D1

0

Q

ClkClk

Transparent when Clk=0

Transparent when Clk=1

At Clk= 0 → 1, Q = D. Else Q is held.

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D Flip Flop – Circuit D Flip Flop – Circuit DiagramDiagram

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D Flip Flop - OperationD Flip Flop - Operation

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D Flip Flop - WaveformsD Flip Flop - Waveforms

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Pass Transistor Logic CircuitsPass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

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Handling Clock SkewHandling Clock Skew

Clk-in

Clk

Clk'

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Pass Transistor Logic CircuitsPass Transistor Logic Circuits

nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications

Mux XOR D Latch D Flip Flop Clock Skew management

Pass Transistor Logic Families

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Pass Transistor Logic Pass Transistor Logic FamiliesFamilies

Complementary Pass Transistor Logic Family Dual Pass Transistor Logic Family Swing Restored Pass Transistor Logic Family

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ProblemsProblems

Design 4 to 1 multiplexor using transmission-gates. Implement an XOR gate using minimum number of

transistors. Implement a full adder using transmission gates.

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Solution - 1Solution - 1

C'0

C0

C1

C'1

Y

A0

A1

A2

A3

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Solution - 2Solution - 2

C'0

C0 C'1

A0

A1

A2

A3

C1 Y

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XOR GateXOR Gate

A B

A⊕B