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Comparators,FETS,&Logic
OtherUsefulDevices
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Lecture 11: Logic UCSD Physics 122 2
Comparators
•
Itisveryo?enusefultogenerateastrongelectricalsignalassociatedwithsomeevent
•
Ifweframethe“event”intermsofavoltagethreshold,thenweuseacomparatortotelluswhenthethresholdisexceeded–
couldbeatacertaintemperature,lightlevel,etc.:anythingthat
canbeturnedintoavoltage• Coulduseanop-ampwithoutfeedback
– setinverKnginputatthreshold–
feedtestsignalintonon-inverKngoutput–
op-ampwillrail(negaKverailiftest<reference;posiKverailif
test>reference)• Butop-ampshaverelaKvelyslow“slewrate”
– 15V/µsmeans2µstogorail-to-railifpowered±15V
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Lecture 11: Logic UCSD Physics 122 3
Enterthecomparator
•
WhenVin<Vref,Voutispulledhigh(throughthepull-upresistor—usually1kΩormore)–
thisarrangementiscalled“opencollector”output:theoutputisbasically
thecollectorofannpntransistor:insaturaKonitwillbepulledtowardtheemiYer(ground),butifthetransistorisnotdriven(nobasecurrent),thecollectorwillfloatuptothepull-upvoltage
• Theoutputisa“digital”versionofthesignal–
withseYablelowandhighvalues(heregroundand5V)
• Comparatorsalsogoodatturningaslowedgeintoafastone–
forbeYerKmingprecision
+
-Vref
Vin Vout
+5V
R5V
Vref
Vout
Vin
Kme
V
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Lecture 11: Logic UCSD Physics 122 4
Relays
• Relaysprovideawaytoswitchon/offanAClinewithalogicsignal
• Simple:5voltsin→ACswitchflippedon•
O?enwillphasetoAClinesoitturnsonatzero-crossing,so-asnottojarelectronics
+5Vexternalcircuit/load
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Lecture 11: Logic UCSD Physics 122 5
Opto-isolators
•
OptoisolatorsprovideameansofconnecKngsignalswithoutcopper(socanisolategrounds,noise,etc.)–
LEDshineslightonaphototransistor,bringingitinto
saturaKon– intheabovecircuit,theoutputispulledupto5Vwhenthe
inputisinac%ve,anddropsneargroundwhentheinputseesavoltage
5V
Vout
Vin
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Lecture 11: Logic UCSD Physics 122 6
LogicFamilies• TTL:transistor-transistorlogic:BJTbased
– chipshaveL,LS,F,AS,ALS,orHdesignaKon–
output:logichighhasVOH>3.3V;logiclowhasVOL<0.35V–
input:logichighhasVIH>2.0V;logiclowhasVIL<0.8V–
deadzonebetween0.8Vand2.0V
• nominalthreshold:VT=1.5V• CMOS:complimentaryMOSFET
– chipshaveHCorACdesignaKon–
output:logichighhasVOH>4.7V;logiclowhasVOL<0.2V–
input:logichighhasVIH>3.7V;logiclowhasVIL<1.3V–
deadzonebetween1.3Vand3.7V
• nominalthreshold:VT=2.5V–
chipswithHCTareCMOSwithTTL-compaKblethresholds
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Lecture 11: Logic UCSD Physics 122 7
LogicFamilyLevels• CMOSisclosertothe“ideal”that
logiclowiszerovoltsandlogichighis5volts–
andhasabiggerdeadzone
• The?CTlineaccommodatesboththeTTL/CMOSlevels
• Example:ATTLdevicemust:– interpretanyinputbelow0.8Vas
logiclow– interpretanyinputabove2.0Vas
logichigh– putoutatleast3.3Vforlogichigh–
putoutlessthan0.35Vforlogiclow
• Thedifferinginput/outputthresholdsleadtonoiseimmunity
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Lecture 11: Logic UCSD Physics 122 8
Field-EffectTransistors
•
The“standard”npnandpnptransistorsusebase-currenttocontrolthetransistorcurrent
• FETsuseafield(voltage)tocontrolcurrent•
Resultisnocurrentflowsintothecontrol“gate”•
FETsareusedalmostexclusivelyasswitches
–
popafewvoltsonthecontrolgate,andtheeffecKveresistanceisnearlyzero
2N7000FET
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Lecture 11: Logic UCSD Physics 122 9
FETGeneraliKes• EveryFEThasatleastthree
connecKons:– source(S)
• akintoemiYer(E)onBJT– drain(D)
• akintocollector(C)onBJT– gate(G)
• akintobase(B)onBJT• SomehaveabodyconnecKontoo
– thougho?enKedtosource
FET
BJT
notepinoutcorrespondence
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Lecture 11: Logic UCSD Physics 122 10
FETTypes• Twoflavors:nandp• Twotypes:JFET,MOSFET•
MOSFETsmorecommon• JFETsconduct“bydefault”
– whenVgate=Vsource• MOSFETsare“open”bydefault
– mustturnondeliberately• JFETshaveap-njuncKonatthe
gate,somustnotforwardbiasmorethan0.6V
• MOSFETshavetotalisolaKon:dowhatyouwant
0 2 4-2-4
logcurrent
Vgate-Vsource
p-channelMOSFET n-channelMOSFET
n-channelJFET
p-channelJFET
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Lecture 11: Logic 11
MOSFETSwitches•
MOSFETs,asappliedtologicdesigns,actasvoltage-controlledswitches–
n-channelMOSFETisclosed(conducts)whenposiKvevoltage(+5V)isapplied,openwhenzerovoltage
–
p-channelMOSFETisopenwhenposiKvevoltage(+5V)isapplied,closed(conducts)whenzerovoltage•
(MOSFETmeansmetal-oxidesemiconductorfieldeffecttransistor)
source
drain
gate
source
gate
drain5V 5V
0V0V
5V0V
+voltage +voltage
0V 5V
<5V <5V
n-channelMOSFET p-channelMOSFET
“body”connecKono?enKedto“source”
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Lecture 11: Logic UCSD Physics 122 12
DatamanipulaKon• AlldatamanipulaKonisbasedonlogic•
Logicfollowswelldefinedrules,producingpredictabledigitaloutputfromcertaininput
• Examples:
A B C 0 0 0 0 1 0 1 0 0 1 1 1
AND
A B C 0 0 0 0 1 1 1 0 1 1 1 1
OR
A B C 0 0 0 0 1 1 1 0 1 1 1 0
XOR
A B C 0 0 1 0 1 1 1 0 1 1 1 0
NAND
A B C 0 0 1 0 1 0 1 0 0 1 1 0
NOR
A B
A B
A B
A B
A B C
bubblesmeaninverted(e.g.,NOTAND→NAND)
A
A C 0 1 1 0
NOT
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Lecture 11: Logic UCSD Physics 122 13
Aninverter(NOT)fromMOSFETS:5V
0V
input output
5V
5V
0V
0V
5V
5V0V
0V
•
0VinputturnsOFFlower(n-channel)FET,turnsONupper(p-channel),sooutputisconnectedto+5V
•
5VinputturnsONlower(n-channel)FET,turnsOFFupper(p-channel),sooutputisconnectedto0V–
Neteffectislogicinversion:0→5;5→0
• ComplementaryMOSFETpairs→CMOS
A
A C 0 1 1 0
NOT
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Lecture 11: Logic UCSD Physics 122 14
ANANDgatefromscratch:
5V
0V
INA
INB
OUTC
• Bothinputsatzero:– lowertwoFETsOFF,uppertwoON–
resultisoutputHI
• Bothinputsat5V:– lowertwoFETsON,uppertwoOFF–
resultisoutputLOW
• INAat5V,INBat0V:– upperle?OFF,lowestON–
upperrightON,middleOFF– resultisoutputHI
• INAat0V,INBat5V:– oppositeofpreviousentry–
resultisoutputHI
A B C 0 0 1 0 1 1 1 0 1 1 1 0
NAND
A B
0V C
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Lecture 11: Logic UCSD Physics 122 15
ANORgatefromscratch:
5V
0V
INA
INB
OUTC
• Bothinputsatzero:– lowertwoFETsOFF,uppertwoON–
resultisoutputHI
• Bothinputsat5V:– lowertwoFETsON,uppertwoOFF–
resultisoutputLOW
• INAat5V,INBat0V:– lowerle?OFF,lowerrightON–
upperON,middleOFF– resultisoutputLOW
• INAat0V,INBat5V:– oppositeofpreviousentry–
resultisoutputLOW
A B C 0 0 1 0 1 0 1 0 0 1 1 0
NOR
5V
A B
C
justaNANDflippedupside-down…
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Lecture 11: Logic UCSD Physics 122 16
AllLogicfromNANDsAlone
A B C 0 0 1 0 1 1 1 0 1 1 1 0
NAND
A B
A C 0 1 1 0
NOT
A B C 0 0 0 0 1 0 1 0 0 1 1 1
AND
A B C 0 0 0 0 1 1 1 0 1 1 1 1
OR
A B C 0 0 1 0 1 0 1 0 0 1 1 0
NOR
invert output (invert NAND)
invert both inputs invert inputs and output (invert OR)
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Lecture 11: Logic UCSD Physics 122 17
Onelasttype:XOR
• XOR=(ANANDB)AND(AORB)•
AndthisyoualreadyknowyoucanmakefromcompositeNANDgates(thoughrequiring6total)
• Then,obviously,XNORistheinverseofXOR–
sojustsKckaninverterontheoutputofXOR
A B
C
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Lecture 11: Logic UCSD Physics 122 18
RuletheWorld
•
NowyouknowhowtobuildALLlogicgatesoutofn-channelandp-channelMOSFETs–
becauseyoucanbuildaNANDfrom4MOSFETs– andallgatesfromNANDs
• Thatmeansyoucanbuildcomputers
• Sonowyoucanruletheworld!
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Lecture 11: Logic 19
ArithmeKcExample• Let’saddtwobinarynumbers:
00101110=46+01001101=7701111011=123
•
Howdidwedothis?Wehaverules:0+0=0;0+1=1+0=1;1+1=10(2):(0,carry1);1+1+(carried1)=11(3):(1,carry1)
• Rulescanberepresentedbygates–
IftwoinputdigitsareA&B,outputdigitlookslikeXOR
operaKon(butneedtoaccountforcarryoperaKon)
A B C 0 0 0 0 1 1 1 0 1 1 1 0
XOR
A B
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Lecture 11: Logic UCSD Physics 122 20
Canmakeruletable:Cin A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1
0 1 1 1
D Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
•
DigitsA&Bareadded,possiblyaccompaniedbycarryinstrucKonfrompreviousstage
• Outputisnewdigit,D,alongwithcarryvalue–
DlookslikeXORofA&BwhenCinis0–
DlookslikeXNORofA&BwhenCinis1–
Coutis1iftwoormoreofA,B,Cinare1
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Lecture 11: Logic UCSD Physics 122 21
BinaryArithmeKcinGatesA B Cin
D
Cout F
E
H
G
A B Cin E F H G D Cout 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0
1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1 1
0 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1
Input Intermediate Output Each digit requires 6 gates
Each gate has ~6 transistors
~36 transistors per digit
+ A
B
Cin D
Cout
“Integrated” Chip
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Lecture 11: Logic UCSD Physics 122 22
8-bitbinaryarithmeKc(cascaded)
0
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
0
1
1
1
1
0
1
1
0
0
0
1
1
0
0
00101110 = 46 + 01001101 = 77 01111011 = 123
1 1 +
+
+
+
+
+
+
+ 0
MSB
LSB = Least Significant Bit
Carry-out tied to carry-in of next digit.
“Magically” adds two binary numbers
Up to ~300 transistors for this basic function. Also need –, ×,
/, & lots more.
Integrated one-digit binary arithmetic unit (prev. slide)
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Lecture 11: Logic UCSD Physics 122 23
Computertechnologybuiltupfrompieces
•
Theforegoingexampleillustratesthewayinwhichcomputertechnologyisbuilt–
startwithliYlepieces(transistorsacKngasswitches)–
combinepiecesintofuncKonalblocks(gates)–
combinetheseblocksintohigher-levelfuncKon(e.g.,addiKon)–
combinethesenewblocksintocascade(e.g.,8-bitaddiKon)–
blocksgetincreasinglycomplex,morecapable
• Nobodyonearthunderstandsmodernchipinside-out–
Grabpreviouslydevelopedblocksandrun–
Letacomputerdesignthegatearrangements(eyesclosed!)
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Lecture 11: Logic UCSD Physics 122 24
Reading
•
Asbefore,TheArtofElectronicsbyHorowitzandHill,andtheStudentManualaccompanimentbyHayesandHorowitzarevaluableresources
• Textreading:– p.432(p.461in3rded.)oncomparators–
6.2.5onrelays(esp.solidstate)–
pp.461–462(490–491in3rd)paragraphonopto-isolators–
6.6.10onlogicfamilies– p.410(p.449in3rd)onFETs–
6.6.1,6.6.2,6.6.3,6.6.4ondigitallogic– 6.6.7onDACs,ADCs
