Lecture 14Lecture 14

Logic Families III

Professor Sunil BhaveCU School of Electrical and Computer p

Engineering

March 19, 2010

Complementary Pass Transistor Logicp y g

P T i tA

FPass-Transistor

NetworkABB

A Inverse

(a)

FPass-TransistorNetwork

ABB

Inverse

A

B B B B

A

B B

A

B

A

B

B

A

B

F=AB

F=AB

F=A+B

F=A+B

A

A

A

F=A⊕ΒÝ

F=A⊕ΒÝ

(b)

OR/NOR EXOR/NEXORAND/NAND

Solution 3: Transmission Gate

CC

A B A B

CC

BA = 2.5 V

C = 2.5 V

CL

C = 0 V

Resistance of Transmission Gate

2.5 VR

30

R

Vout2.5 V

Rn

R

20 ce

, ohm

s

Rn

Rp

0 V

Rp

10

Res

ista

nc

Rn || Rp

0.0 1.0 2.00

V VVout, V

Pass-Transistor Based Multiplexerp

S S

SVDD

VDD

S S

AM2

F

M1

B

S F

S

GND

In1 In2S S

Transmission Gate XOR

B

BM2

AF

A

M1 M3/M4

B

BM3/M4

Delay in Transmission Gate Networksy

V1 Vi-1

2.5 2.5Vi Vi+1

2.5Vn-1 Vn

2.5

In

C0 0 CC 0 CC 0

In

(a)

V1 Vi Vi+1

C

Vn-1 Vn

CC

InReqReq Req Req

CC

(b)m

C

Req Req

C C

Req

C C

Req Req

C C

Req

CIn

(c)

Delay Optimizationy p

Transmission Gate Full Adder

VDDP

A

PA A

VDD

C

DDCi

SP Sum Generation

B

P

VDDA

Ci

P

AB VDDP

Ci

DD

A

P

Ci

CoCi

P Carry Generation

APSetup

Similar delays for sum and carrySimilar delays for sum and carry

Dynamic Logic

D i CMOSDynamic CMOSIn static circuits at every point in time (except whenIn static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.

f f ( )fan-in of n requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage ofDynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

i 2 ( 1 N 1 P ) irequires on n + 2 (n+1 N-type + 1 P-type) transistors

D i G tDynamic Gate

I

MpClkOut

C

Out

Clk Mp

In1

In2 PDNIn3

CL A

BC

3

MeClkClk

B

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)Evaluate (CLK = 1)

D i G tDynamic Gateoff

I

MpClkOut

C

Out

Clk Mp on 1off

((AB)+C)In1

In2 PDNIn3

CL A

BC

((AB)+C)

3

MeClkClk

B

Me

offon

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)Evaluate (Clk = 1)

C diti O t tConditions on OutputOnce the output of a dynamic gate is discharged itOnce the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

P ti f D i G tProperties of Dynamic GatesLogic function is implemented by the PDN onlyg y y

number of transistors is N + 2 (versus 2N for static complementary CMOS)

Full swing outputs (V = GND and V = V )Full swing outputs (VOL = GND and VOH = VDD)Non-ratioed - sizing of the devices does not affect the logic levelsgFaster switching speeds

reduced load capacitance due to lower input capacitance (Cin)reduced load capacitance due to smaller output loading (Cout)no Isc, so all the current provided by PDN goes into discharging CL

Properties of Dynamic Gatesp y

Overall power dissipation usually higher than static CMOS

no static current path ever exists between VDD and GND (including Psc)( g sc)no glitchinghigher transition probabilitiesextra load on Clkextra load on Clk

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTnTn, M, IH IL q Tn

low noise margin (NML)Needs a precharge/evaluate clock

Issues in Dynamic Design 1: Charge LeakageCharge Leakage

CLK

ClkOut

Mp

CLK

CL

Out

A

VO tEvaluate

Clk Me

VOut

Precharge

Leakage sources

Dominant component is subthreshold currentDominant component is subthreshold current

S l ti t Ch L kSolution to Charge LeakageKeeper

Clk Mp

A O t

Mkp

CLA

B

Out

Clk Me

Same approach as level restorer for pass-transistor logic

Issues in Dynamic Design 2: Charge SharingCharge Sharing

ClkO t

Mp

Charge stored originally on CL is redistributed (shared)

CLA

Out over CL and CA leading to reduced robustness

Clk

CA

CB

B=0

Me

Ch Sh i E lCharge Sharing Example

C 50fF

Clk

A AOut

CL=50fFA A

B B B !BCa=15fF C =15fFB !B

CC

a

Cc=15fF

Cb=15fF

Cd=10fF

Clk

Ch Sh iCharge Sharingcase 1) if ΔVout < VTn

VDD

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

or

Clk

Out

Mp

or

ΔVout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

X

CLA Ma

C

case 2) if ΔVout > VTnB = 0CaMb

ΔVout VDDCa

Ca CL+----------------------⎝ ⎠⎜ ⎟⎛ ⎞

–=CbClk Me

Solution to Charge R di t ib tiRedistribution

Clk Mp

AOut

MkpClk

A

B

Clk Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Issues in Dynamic Design 4: Cl k F dth hClock Feedthrough

ClkO t

Mp

Coupling between Out and Clk input of the precharge

CLA

Out device due to the gate to drain capacitance. So voltage of Out can rise

Clk

B

Me

voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Outclock couple to Out.

Cl k F dth hClock FeedthroughClock feedthrough

2.5Clk

In1

Out

Clock feedthrough

1.5

1

In2

In3 In &0.5

Clk

In3

In4

In &Clk

Out

-0.50 0.5 1

Clk

Time, ns

Clock feedthroughClock feedthrough

Oth Eff tOther Effects

Capacitive couplingCapacitive couplingSubstrate couplingMinority charge injectionSupply noise (ground bounce)

C di D i G tCascading Dynamic GatesV

Clk

Out1

Mp MpClk

Out2Clk

I

Clk

In

Me MeClk

In

Out1 VTne e Out1

Out2 ΔV

t

Only 0 → 1 transitions allowed at inputs!Only 0 → 1 transitions allowed at inputs!

sunil

Rectangle