restrukturisasi array logic

8/20/2019 restrukturisasi array logic

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A laser -Restructurable .LogicArray for Rapid Integrated

Circuit PrototypingJack 1. Raffel, Robert S. Frankel, Kenneth H. Konkle, and James E. !rg!ia

Laser "rogramming can red!ce the time re#!ired to c!stomi$e a logic circ!it to

min!tes %itho!t the access and resistance limitations of electrically "rogrammable

de&ices. 'e ha&e de&elo"ed a laser(restr!ct!rable logic array that can be

com"letely tested before "ackaging and that can be fabricated %ith a standard

com"lementary metal(o)ide(semicond!ctor *+S- "rocess. +irc!its of !" to

1// gate e#!i&a lents ha&e been restr!ct!red and a base array of 0/// gate

e#!i&alents has been fabricated. F!t!re %ork is aimed at the !se of 1(!m design

r!les to de&elo" arrays that ha&e a com"le)ity of tens of tho!sands of gates.

V&ER LAR2E S+ALE

3 45E2RA53 4

*6LSr - technol laser linking technology is the restr!ct!ring of the inter

ogy has enabled the fabrication of com"le)cir

c!it f!nctionality in a tiny &ol!me of

s"ace. 7nfort!nately, d!e to the tooling costs

associated %ith each ne% design and the time re#!ired

f!r con&entional silicon%afer "rocessing, the integrated

circ!it *3+- man! fact!ring cycle is not %ell s!ited todesign de&elo"ment and circ!it e)"erimentation. 5he

ra"id s!ccession of ne% generations of architect!res

and systems "laces a "remi!m on the ca"ability to

take a ne% design from conce"tion to fabrication as

#!ickly as "ossible. A ma8or ad&ance in red!cing

delays in the "rod!ct de&elo"ment cycle has been the

ad&ent of so"histicated com"!ter aided design

*+A9- tools that enable a high degree of a!tomation

in circ!it synthesis, layo!t, sim!lation, &eri fication, and

test(&ector generation. A corres"onding im "ro&ement

in the s"eed of "hysical im"lementation has been "ro&ided by a &ariety of fabrication strategies that

incl!de standard cell c!storni$ation, gate arrays, and

a n!mber of field("rogrammable logic de&ices.

At Lincoln Laboratory the !nderlying technology for

o!r %ork in %afer(scale integration is the ca"ability to

!se a laser for both forming and remo&ing connections

on a f!lly "rocessed silicon circ!it. 'e ha&e de&elo"ed

and demonstrated this technology by b!ilding a

n!mber of %afer(scale systems :1;. 5he "rinci"al

f!nction of the

connections on a monolithic %afer to achie&e the defect

a&oidance that is essential for obtaining acce"table

yields on s!ch large(area de&ices. 'e ha&e also !sed

this same technology to "rogram the f!nctionality of

a %afer by modifying the interconnect to reali$e a

&ariety of system architect!res. For e)am"le, a n!mber

of differ ent %afer scale systems, incl!ding a Fast

Fo!rier 5ransform *FF5-, a Ho!gh transform, a 1< ) 1<

con&ol&er, and a constant false(alarm(rate filter, ha&e

been b!ilt from a common %afer design that

com"rises an array of serial m!lti"liers and data

formatters :;.

5his e)"erience has led !s to de&elo" arestr!ct!rable

logic array *RLA- that is "rogrammable at the indi&id!al

chi" le&el and that !ses the laser linking technology

strictly for c!stomi$ation. 5o "ro&ide the fle)i bility of a

gate array %ith the ra"id t!rnaro!nd time of a "rogram mable logic de&ice, %e designed the basic

array mod!le to ha&e a &ery lo% le&el of logic

com"le)ity. *5he t!rn aro!nd time here is defined as

the time re#!ired to take

an Ie from design thro!gh fabrication.- Laser "rogram

ming "ro&ides an economical method of "rod!cing in

stant(t!rnaro!nd r+s that can reali$e any system f!nction by !sing a laser for both forming and

remo&ing connections at "redetermined sites to tailor


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the %iring on a f!lly fabricated, "ackaged, and tested

standard arrayVOLUME 4, NUMBER 2,1991 THE llNCOLN LABORATORYOURNAL =>


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Table 2. Progr ammable Technologies

T ec hnol og y Dev i c e Ad v antag es Di sadv ant ag es

#loatin+ 8ate T' ansisto' " Elect' icall 9' o+'a$$a/le " Rest' icte) A'chitect&' e

" Re&sa/le " .%ecial Co$%&te' (

Ai)e) *esi+n C A*-

Tools Re:&i' e)

" 9' o+' a$$in+ Ci'c&it

O;e'hea)

.tatic Ran)o$( T' ansisto' " Elect' icall 9'o+'a$$a/le " Rest' icte) A' chitect&'e

Access Me$o'2

,R AM-

" Re&sa/le " .%ecial C A* Tools Re:&i' e)

" 9'o+' a$$in+ Ci' c&it

O;e'hea)

" Lo3 9e'1 o'$ance

Volta+e Lin4 " Elect' icall 9'o+' a$$a/le " .%ecial #a/'ication 9'ocess

9' o+'a$$a/le Re:&i'e)

" .%ecial CA* Tools Re:&i'e)

" 9'o+' a$$in+ Ci'c&it

O;e'hea)

" Lo3 9e'1 o'$ance

Lase' Lin " .tan)a' ) Co$%le$enta'2 " .%ecial Lase' #acilit2

9' o+'a$$a/le Metal(O


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? RAFFEL E5 AL. A Laser-Restructur able Logic Arr a y for Rapid Integrated Cir cuit Pr ototy ping

? RAFFEL E5 AL.

A Laser-Re structur abl e Log ic Arra y for Rapid Integr at ed Cir cuit Proto typing

THE LINCOLN LABORATORY OURNAL 100VOLUME 4, NUMBER 2, 19911//1//1// THE LINCOLN VOLUME 4, NUMBER 2, 1991

A

"! = ((

*i&sionContact

.&/st'ate

.ection A( A

tains acce"tably lo% leakage, a re#!irement for good

circ!it isolation.

A layo!t of the interconnect str!ct!re for a standard

array that !ses laser (diff!sed links is sho%n in Fig!re


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? RAFFEL E5 AL. A Laser-Restructur able Logic Arr a y for Rapid Integrated Cir cuit Pr ototy ping

? RAFFEL E5 AL.

A Laser-Re structur abl e Log ic Arra y for Rapid Integr at ed Cir cuit Proto typing

THE LINCOLN LABORATORY OURNAL 101VOLUME 4, NUMBER 2, 19911/11/11/1 THE LINCOLN VOLUME 4, NUMBER 2, 1991

of 1// to


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9assi;e

Lase'

Bea$transistor circ!it diagram are sho%n in Fig!r e B. 5his

modification to the minim!m im"lementation "rod!ces

a mod!le that is more efficient in ty"ical a""lications

Ins&lato' Lin4

FIGURE 4! C'oss section o ;e'tical lin not )'a3n to

scale-! The lin )ielect'ic can /e silicon nit' i)e o' a$o'

%ho&s silicon!

metal lines, as sho%n in Fig!re 0. Link formation occ!rs

%hen the metal is melted by a laser beam and combines

%ith the link dielectric to form an al!min!m(silicon

alloy %ith a resistance of a f e% ohms. +!rrent %or k is

concentrated on o"timi$ing the interrnetal dielectric for

reliable lo%( "o%er linking and on r ed!cing the metal

line%idth at the link site %itho!t the loss of intr ale&el

contin!ity after link formation.

Te Uni!ersal Logic "odule #UL"$ Array

ne ma 8or ar chitect!r al iss!e in designing a "rogr am

ma ble logic ar r ay is the selection of the "rogramma ble

mod!le, or b!ilding block. 5he choice is greatly aff ected

by the characteristics of the interconnect. Meca!se the

connecti&e link allo%s for testing "r ior to "rogr amming,

the b!ilding block sho!ld be a testa ble !nit. 3n addition,

the lo%est(le&el b!ilding block that is com "ati ble %ith

the inter connect density sho!ld be !sed to "ro&ide fle)

ibility for a %ide range of a""lications.

ne b!ilding block that meets these r e#!irements isthe thr ee(in "!t 7ni&ersal Logic od!le *7L- :>;,

%hich can r eali$e all 1@ Moolean f!nctions of t%o

&ar ia bles. 5he logic f!nction for the minim!m im"le

mentation of this mod!le is

F N (Y 1 •Y2 ( Y 1 •Y! "

5he logic diagram of a modified 7L and its 1@(

%itho!t being significantly larger. 5he additional fo!rth

in"!t gi&es greater fle)ibility in im"lementing latches

and combinational logic, an o!t"!t in&erter makes thecom"lement of the o!t "!t signal a&ailable so that a

mod!le need ne&er be !sed solely for signal in&ersion,

and an additional t%o(transistor "robe is !sed for "re

"rogram testing. 5his modified 7L im"lements the

logic f!nction

F N F# N ( Y 1 •Y 2 (Y1 •Y! •Y 4-!

As sho%n in Fig!re B*b-, laser( "rogrammable links

and c!t "oints are "ro&ided so that each in"!t can be

disconnected from its &ertical interconnect and

connected to either "o%er or gro!nd.

A Restructurable Logic Array

An RLA chi" consists of an ar r ay of 7Ls s!rro!nded

by "o%er and signal 3 "ad blocks. Additional circ!itry

on the chi" allo%s for f!nctional testing both before and

after "rogramming. Fig!re @ sho%s an RLA chi" that

com"rises 1@ 7Ls and 14 11/ "ads. 5he chi",

named the RLA1@, %as f abricated in the S3S

f o!ndry %ith a 2 $l1m G(%ell +S "rocess. 5he 7L

arr ay consists of alternating ro%s of hori$ontal inter

connect channels and 7Ls, %hich are connected by&ertical %ir es. 5he channel interconnect "atern, sho%n

schematically in Fig!r e >, allo%s connections bet%een

crossing tr acks and c!ts in both hor i$ontal and &ertical

tracks, as sho%n in Fig!re


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F

F #

' o/e

,a-

%dd % d d

' o/e

8N*Y 4 F#

8N*

O C&t (D( Lin*b-

FIG!" ! Mo)iie) Uni;e'sal Lo+ic Mo)&le? a- lo+ic )ia+'a$, an) /- ci'c&it

)ia+' a$!

can test a col!mn of 7Ls and its &ertical tr acks by

feeding in"!t signals from a test b!s into the 7L

in"!ts and ena bling the "robe cir c!its in that col!mn.

5he o!t"!t of each 7L in a col!mn can be indi&id!al

ly obser&ed by se#!entially shifting the ro% "robe o!t

"!ts to a test o!t"!t "ad. Grior to restr!ct!ring, all

7Ls ar e tested for f!nctionality. Meca!se the "robeena ble and "robe m!lti"le)ing ar e not aff ected by r e

str!ct!ring, the o!t"!t of each 7L can also be o b

ser&ed after "rogramming. 3n addition, %e can test the

hori$ontal tracks in the channels for o"ens and ad

8acent shorts befor e "rogramming by connecting the

tr acks into t%o ser"entine chains.

Cip Input%&utput

3 blocks can be r estr!ct!r ed into one of ten f!nctions

b!ffered in"!t, !nb!ffered in"!t, !nb!ffered Schmitt

trigger in"!t, o!t"!t, tristate o!t"!t, bidir ectional, bi

dir ectional %ith Schmitt trigger, !nb!ffer ed in"!t %ithdri&er , !nb!ffered Schmitt(trigger in"!t %ith dri&er, and

n!ll. 5he 3 blocks are initially %ir ed in "air s one

block is tested for in"!t f!nction %hile its "artner is

tested for o!t"!t f!nction. Fig!r e @*a- sho%s the cir c!it

design for the 3 block , and Fig!r e @*b- sho%s ho% to


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THE LINCOLN L ABORATORY OURN AL 1/BVOLUME 4, NUMBER 2, 19911/0 THE LINCOLN LABORATORY OURN AL VOLUME 4! NUMBER 2! 1991

I 'o/e(Ena/le *eco)e' I

(111111 11 111111 1 1 1

I? / ? ?ULM> I? ? / ?ULM> I? ? ? ?ULM> I? / ? ?ULM>

>*1-)

I? / / ?ULM> I? / / ?ULM>I? / / ?ULM> I? / / ?ULM>/.

E???l

>Gtl

Gtl/I

*1-

e I?/ /

?ULM> I?/ /

?ULM> I?/

? ?ULM> I?/ /

?ULM>

9'o/e

O&t

In%&ts 9' o/e

Ena/le

c,In%&ts

H(( I? / / ?ULM> I? ? / ?ULM> I? / / ?ULM> I? / / ?ULM>

I I I I

I Test(B&s T' anse' Itttt

FIGURE *+ #$ a' 'a 3ith test %'o/in+!

An 3 f!nction is selected by laser "rogramming the

3 block on the chi", as sho%n in Fig!re @. 5he design

er b!ilds his logic o!t of the macros and 3 blocks by

connecting them %ith schematic(entry soft%ar e. nce

the schematic of com"onents fits the designerCs conce"

tion, the +A9 soft%are can PflattenP the schematic to its

7L(3 block im"lementation in the form of a stan

dard Electronic 9ata 3nterchange Format *E93F- //

neclist(a list of the se#!ence of terminal(to(terminal

"in connections that need to be made. 5his "rocess isanalogo!s to a gate array design style in %hich the gate

array li brary elements can be tho!ght of as transistor

macros. S!ch a design system can be r eali$ed in most

commer cially a&ailable schematic(ca "t!r e systems. For

e)am"le, the system has been im"lemented %ith the

r+A9, F!t!r enet, and 6ie%logic schematic(ca"t!r e

"ackages thro!gh the installation of macro li braries.

5he o!t"!t of this design "rocess is a neclist of connec

ti&ity of7Ls and 3 blocks.

5he neclist com "onents are ne)t ma""ed onto the

7Ls that ar e "hysically a&ailable on the laser ( "rogram

ma ble chi ". 5his ste " can be accom"lished a!tomatically

by !sing "lace(and(glo bal(ro!te techni#!es analogo!s to

those de&elo"ed f or gate arrays and standard cell designs.

For e)am"le, %e ha&e !sed 5im ber 'olf :@;, %hich im

"lements a sim!lated annealing "lacement algor ithm

fir st de&elo"ed for standard cell "lacement. 5im ber'olf also "erforms glo bal ro!ting. 3n o!r case, s!ch ro!ting

entails decom"osing large signal nets into smaller, mor e

easily ro!ta ble s!bnets that can each be contained in a

single channel of inter connect bet%een ro%s of 7Ls.

5he "lacement of 3 blocks determines the "ino!t of

the chi" and is "erfor med man!ally.

5he o!t"!t of the "lace(and(glo bal(ro!te "hase is a

/ / /

> / / / / / / / /

(!B

/ / / / / / /

/ / / / I / /


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THE LINCOLN LABORATORY OURNAL 1/@1/@VOLUME 4, NUMBER 2, 19911/D THE LINCOLN LABORATORY OURNAL VOLUME 4! NUMBER 2! 1991

Perfor'ance

5o meas!re the s"eed of RLA circ!its, %e laser(

"ro grammed se&eral test str!ct!r es onto a small

11(7L chi" f a br icated at S3S %ith the

same 2$*1++i "rocess !sed for the RLA1D// chi"

descr i bed ear lier. 5he test str!ct!r es %er e

1- long %ires of differ ent lengths to meas!r e the "ro"a

gation delay thro!gh the interconnect,

- %ires of the same length dr i&en by differ ent ty"es


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? RAFFEL E5 AL.

A Laser-Restrucsurable Logic Array for Rapid Int e grated Circuit Prototypin g ? RAFFEL E5 AL.

A Laser-Restructurable Logic Arr a y for Rapid Integr at ed Circuit Prototypin g

of internal dri&ers to meas!re the ca"abilities of

the dri&ers, and


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THE LINCOLN LABORATORY OURN AL ./VOLUME 4, NUMBER 2, 19911/@

THE LINCOLN L ABORATORY OURN AL VOLUME 4! NUMBER 2! 1991

diff!sed link !se of &ertical(link technology no% in

de&elo"ment %o!ld considerably shrink the e)tra area

o&erhead re#!ired by the links. +om"arisons %ith

floating(gate and RA(based "rogrammable de&ices

sho% m!ch larger ad&antages for the link(based

technologies.

Application E0a'ples

Laser"rogramming has been a""lied to both "rototy"ing

and logic consolidation. 3n one a""lication, %e originally

designed a system %ith the con&entional standard cell

techni#!e and, to obtain a "rototy"e #!ickly, re"licated

the system %ith an RLA chi". 3n another a""lication,

logic originally im"lemented %ith se&eral electrically

"rogrammable chi"s %as red!ced to a single RLA

chi". 5he fle)ibility of the RLA a""roach is ill!strated

by its ability to re"licate the f!nction of se&eral different ty "es of circ!its, incl!ding standard cells,

"rogrammable logic arrays *GLA-, and transistor (to

transistor logic *55L-.

ore than a do$en different a""lications ha&e been

"rogrammed onto the &ario!s smaller "redecessors of the

RLA1@ some of these are s!mmari$ed in 5able B.

5y"ically,abo!t


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THE LINCOLN LABORATORY OURN AL .1VOLUME 4, NUMBER 2, 19911/=

THE LINCOLN L ABORATORY OURN AL VOLUME 4! NUMBER 2! 1991

TRICOUNT2 is a 2(/it co&nte' that 'e%laces TTL %a'ts, an) TEMCOUNT is a

Celsi&s(to(#ah'enheit con;e'te'!


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~~'_e --~~~~-Vdd F

------

'o/eEna/le

o 0 1 2 ( Latch 51 5 2 Y1 Y 2 $ AN*JOR

F #

3Jl C&t !! Lin

C ut s and in6s F unct i on

None Maste' 07D Latch( ( (

F F# 1 " 2 0 ( F • C 8 "C(8

(a/c) .la;e 07D Latch

( ( (F F # 1 " 2 0 (F 9 C8 " C (8

a/e Co$/inational AN*JOR Lo+ic

F N F # N 5 1 • 52 Y 1 • Y2

FIGURE + Rest' &ct&' a/le cloce) lo+ic $o)&le!

into either a 9 sla&elatch or a fo!r(in"!t combinational

logic gate. 5he mod!le r etains the feat!r e of f!ll testabil ity befor e and after r estr !ct!ring, and r estr!ct!ring %ill

not affect loading on the global clock. 5he A49R

logic f!nction is mor e efficient for im"lementing logic

thro!gh the !se of com"!ter (aided logic generator s.

Conclusions

'e ha&e de&elo"ed a laser(r estr!ct!ring methodology,

circ!it mod!les, a chi" architect!re, and a set of a""lica

tion tools for a laser ( "rogr ammable r estr!ct!ra ble

logic ar r ay *RLA-. RLA chi"s ha&e been fabr icated

thro!gh a standar d com"lementary metal(o)ide(semi

cond!ctor *+S- "rocess, and se&eral diff erent digi

tal a""lications ha&e been im "lemented. An a""lication

%ith 0// 7ni&ersal Logic od!les *7L- *l(gate

e#!i&alent- %as r estr!ct!r ed in / min. 'e no% ha&e

a&aila ble an RLA de&ice %ith 1D// 7Ls and 1/0 3

"ins. +om "!ter (aided design *+A9- tools are a&aila ble

to interface %ith se&er al schematic(ca "t!r e systems, to

"lace the 7Ls and ro!te the nets, to cr eate laser

o"er ation command files, and to &er ity cir c!it "erfor (

N N

N N


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2 RAFFEL ET AL!

A Laser -Restructur ableLogic Array for Rapid Int e grat ed Circuit Prot otypin g

? RAFFEL E5 AL. A Laser-Restructur abl eLo gic Arra y for Rapid Integr at ed C ircuit Prototypin g

mance. 7sing a mask(e#!i&alent techni#!e, %e can

mass "rod!ce any RLA a""lication %ith no change in

chi " "erformance or a""earance. 'e ar e c!rr ently

de&elo "ing alternati&e logic mod!les and ne% link

str!ct!res that, %hen combined %ith 3(J1m designr !les, sho!ld enable the design of arr ays of more than

1/,/// gates and clock rates a""roaching 1// H$.

Ackno3ledg'ents

5he %ork "resented in this article %as "erformed in

large "art by former Lincoln La boratory staff mem

ber s. 3n "ar tic!lar , att Rhodes, 9a&e Allen, and Rich

2oldenberg %ere r es "onsi ble for most of the design

%ork descri bed. 5his %or k %as s"onsor ed by 9ARGA.


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112 THE LINCOLN LABORATORY OURNAL VOLUME 4! NUMBER 2!1991 THE LINCOLN LABOR ATORY OURNAL 111VOLUME 4, NUMBER 2,1991

R EFER E4CE)

1. J.1. Raffel, P5he R6LS3 A""roach to 'afer Scale 3ntegration,P

in * af er +cale Integration, eds. C! Jessho"e and '. oor e*Adam Hilger , Mr istol and Moston, Mristol, England, 1=@D-,

"". 1==(/, "".


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2 RAFFEL ET AL.

A Laser -Restructur ableLogicArray for Rapid Integrated Circuit Prototyping

JA+K I! RAFFEL

is Leader of the 9igital

3ntegrated +ir c!its 2ro!". He

recei&ed an A.M. degree f r om

+ol!mbia +ollege, a M.S.

degree in electrical engineering

from the +ol!m bia School of

Engineering, and an .S.degree f rom 35, %her e he

%as a research assistant at the

9igital +om"!ter La boratory.

JackCs %ork has s "anned the

areas of emitter (co!"led logic

*E+L- gate arrays, magnetic

film memory, semicond!ctor memory analogdigital con

&er sion, 3+ com "!ter (aided

design *+A9- systems, %afer

scale integration, and ne!ral

net%or ks.

R,MER 5 S. FRA4KEL

is a staff member in the 9igital

3ntegr ated +ir c!its 2r o!",

%here he s"eciali$es in soft%are

systems research and de&elo "

ment. Mefore 8oining Lincoln

La bor atory se&en years ago,

Mob %orked for Honey%ell3nc. and the 7ni&er sity of

assach!setts, Moston. He

r ecei&ed a M.A. degr ee in math

f rom Har&ar d and a Gh.9.

degr ee in math f r om the

7ni&er sity of 'isconsin.

KE44E5H H. K,4KLE

is a st alf member in the 9igital

3ntegrated +irc!its 2r o! ". His

f oc!s of research has been in

the design of %afer (scale

integrated circ!its. Ken

recei&ed an E.E. degr ee from

the 7ni&ersity of +incinnatiand an .S.E.E. degree from

35. He is a member of Eta

Ka""a 4! and Sigma Ki!

JAES E. 7R273A r ecei&ed

M.S. degr ees in electr ical

engineering, "hysics, and math

f rom the 7.S. Air Force

Academy and a Gh.9. degree

in electr ical engineer ing and

com "!ter science from 35.

James is a staff member in the 9igital 3ntegrated

+irc!its 2ro! ".


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restrukturisasi array logic