I2C-bus ElementsSASE March 2010SASE- March 2010

Alix Maldonado -Technical Marketing ManagerProduct Line System Management Business Line Interface Products

Agenda

I2C-bus Protocol

Electrical CharacteristicsElectrical Characteristics

Measurements with an Oscilloscope

Resources

Questions

2

I2C - ProtocolIIC - Inter-Integrated Circuitg

Logic

This means:• Decreased number of wires (reduced PCB area)• Reduced number of chip pins

Logic

p p• Remove glue logic• Clip many devices on to the bus• Modular design: Time-to-Market

V

I2C-bus

VCC

Invented by NXP!(Philips Semiconductors)

I2C-bus developed in the late 1970’s for Philips consumer products (e.g. TVs)

Worldwide industry standard and used by all major IC manufacturers

(Philips Semiconductors)

Worldwide industry standard and used by all major IC manufacturers

3

I2C - ProtocolHardware architecture

VDD

Pull up resistors

SDASDA

SCL

Data out

Data in

Clock out

Clock in

Data out

Data in

Clock out

Clock in

2 wire bus: – SDA: Serial Data Line

Device 1 Device 2

SDA: Serial Data Line– SCL: Serial Clock Line

Open-drain or open-collector output stages: wired-AND function

4

I2C - ProtocolHardware architecture (2)

Master2 Slave2

VDD

SDASCL

Multiple master

Master1 Slave1

Multiple slave

Bi-directional– Master-transmitter– Master-receiver– Slave-transmitter– Slave-receiver

Data collision is taken care offData collision is taken care off

5

I2C - ProtocolAddressing / device selection

Each device is addressed individually by softwareNew devices or functions can be easily “clipped" on to an existing bus!112 different addresses max with the 7-bit format (others reserved); additional 1024 with ( )10-bit formatAddress allocation coordinated by the I2C-bus committeeProgrammable pins means that several of the same devices can share the same bus

f fUnique address per device: fully fixed or with a programmable part through hardware pin's)10-bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5A4A3A2A1A0

V

Master1 Slave1

VDD

SDASCL

VDD 0 0 1 1 1 0 0

Fixed

Hardware Programmable

Address registerA6 A5 A4 A3 A2 A1 A0

6

I2C - ProtocolCommunication Master

Communication must start with: START conditionStart bit is always followed by slave addressSl dd i f ll d b READ NOT WRITE bit

Slave

Master or SlaveSlave address is followed by a READ or NOT-WRITE bitThe receiving device (either master or slave) must send an ACKNOWLEDGE bitCommunication must start with: STOP condition

START SLAVEADDRESS[7] R/W ACK DATA[8] ACK STOP

Example:

START SLAVEADDRESS[7] 0 ACK DATA[8] ACK STOP

Transmit (0 = Write)

DATA[8] ACK

Example:

START SLAVEADDRESS[7] 1 ACK DATA[8] ACK STOP

Receive (1 = Read)

DATA[8] ACK

7

I2C - ProtocolSTART & STOP conditions

Start condition - a HIGH to LOW transition on the SDA line while SCL is HIGH

Stop condition - a LOW to HIGH transition on the SDA line while SCL is HIGH

8

START Timing DiagramSTART condition is a high to low transition on the SDA line while SCL is high

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

9

STOP

STOP Timing DiagramSTOP condition is a low to high transition on the SDA line while SCL is high

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

10

STOP

RE-START Timing DiagramRESTART diti i hi h t l t iti th SDA li hil SCL iRESTART condition is a high to low transition on the SDA line while SCL is high, exactly the same as the START

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

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STOP

I2C - ProtocolBit transfer

During data transfer, SDA must be stable when SCL is High

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I2C - ProtocolData transfer

Each byte has to be followed by an acknowledge bit

Number of data bytes transmitted per transfer is unrestricted

If a slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW (clock stretching) to force the master into a wait state

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I2C - ProtocolAcknowledge / NOT-Acknowledge

I2C specification: Data transfer with acknowledge is obligatory. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW d i th HIGH i d f thi l k lduring the HIGH period of this clock pulse.

Scenarios with a NOT-acknowledge (NACK) (SDA staying HIGH):1. A receiver with the address is not present in the I2C bus.2 The receiver is performing real-time tasks and it cannot process the received I2C2. The receiver is performing real time tasks and it cannot process the received I C

information.3. The receiver is the master and wants to take control of SDA line again in order to

generate a STOP command. The slave transmitter MUST then release the SDA line when it sees the NACK so the master can send the STOP command

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line when it sees the NACK so the master can send the STOP command.

I2C - ProtocolArbitration procedurep

Two or more masters may generate a START condition at the same time

Arbitration is done on SDA while SCL is HIGH -Sl i l d

VDD

SDA

Slaves are not involvedDATA1

SDA

DATA2

SDA

Master 1 Master 2

Summary: The master that first sends a “1” while the other sends a “0” loses control (arbitration)

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I2C - ProtocolClock synchronization during the arbitration procedurey g p

VDD

SCLInternal counters of masters count the LOW and HIGH times (TL1, TH1) and (TL2, TH2)

CLK1

SCL

CLK2

SCLSCL

Master 1

SCL

Master 2

T T

Wired-AND SCL connection:TL= longest TL= max (TL1, TL2 ,TLn)T shortest T min (T T T )

TL1 TH1

TL2 TH2TH= shortest TH= min (TH1, TH2,THn)

T T

L2 H2

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TL TH

I2C - ProtocolModes

Standard Mode Fast Mode Fast Mode Plus (FM+) High Speed Mode(FM+)

Bitrate (kBit/s) 0 – 100 0 – 400 0 – 1000 0 – 1700 0 – 3400

Address (bits) 7 (10) 7 (10) 7 (10) 7 (10) 7 (10)

Capacitive Bus Load (pF) 400 400 550 400 100

Fast mode Plus (FM+):Increased bandwidth

Sink current (mA) 3 3 20 3 3

– Increased bandwidth– Increased transmission distance (at reduced bandwidth: >> 550 pF bus load)

17

I2C - ProtocolModes: Electrical specification

Standard Mode Fast Mode Fast Mode Plus (FM+)

Bitrate (kBit/s) 0 – 100 0 – 400 0 – 1000 0 – 1700 0 – 3400

High Speed Mode

Address (bits) 7 (10) 7 (10) 7 (10) 7 (10) 7 (10)

Capacitive Bus Load (pF) 400 400 4000 400 100

Sink current (mA) 3 3 20 3 3

Trise: Rise time (ns) 1000 300 120 160 80Trise: Rise time (ns) 1000 300 120 160 80

trise

VVcc

Vbus(V)

VIH

V

0.7 * VDD

0 3 * V

t (s)

VILVOL

0.3 VDD

0.4 V @ 3 mA sink current

0 4 V @ 20 mA sink current (FM+)

gndt1 t2

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0.4 V @ 20 mA sink current (FM+)

I2C - ProtocolSummaryy

START HIGH to LOW transition on SDA while SCL is HIGH

STOP LOW to HIGH transition on SDA while SCL is HIGH

DATA

8-bit word, MSB first (Address, Control, Data):- Must be stable when SCL is HIGH- Can change only when SCL is LOW- Number of bytes transmitted is unrestricted

D h 9th l k l d i th HIGH i dACKNOWLEDGE

- Done on each 9th clock pulse during the HIGH period- The transmitter releases the bus - SDA goes HIGH- The receiver pulls DOWN the bus line - SDA goes LOW

CLOCK

- Generated by the Master(s)- Maximum speed: (100, 400, 1000, 3400 kHz) but NO minCLOCK p ( )- A receiver can hold SCL low when performing another function (transmitter in a Wait state)- A master can slow down the clock for slow devices

ARBITRATION

- Master can start a transfer only if the bus is free- Several masters can start a transfer at the same time

A bit ti i d SDA li- Arbitration is done on SDA line- Master that lost the arbitration must stop sending data

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START and STOP ConditionsSTART and STOP Conditions

Q estion What is rong ith this fig re?Question: What is wrong with this figure?

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Data Transfer

AcknowledgeData

• During data transfer SDA must be stable when SCL is High• Each byte has to be followed by an acknowledge bit• Number of bytes transmitted per transfer is unrestricted

During data transfer, SDA must be stable when SCL is High

• If a slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state

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master into a wait state

I2C-bus Slave Address (1)Two formats of I2C slave address: 7-bit or 10-bit address

7-bit Slave address is most popular, allows up 111(27 = 128 devices 128 – 17 reserved ))

10-bit slave address may accommodate up to 210 = 1024 devices on the same bus

Devices that supports either 7 bit or 10 bit address may co exist on the sameDevices that supports either 7-bit or 10-bit address, may co-exist on the same bus

Reserved Addresses

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

ACK/

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STOPSTOP

I2C-bus Slave Address (2)µcon-t ll

I/O A/D LCD RTC µcon-t ll II

SCL

troller

SDA

D/A troller II

1 0 1 0 A2A1A0R/W1 0 1 0 0 1 1

New devices or

EEPROMA0A1A2

• Each device is addressed individually by software

Fixed Hardware Selectable

New devices or functions can be easily “clipped” on to an existing bus!

U i dd d i f ll fi d ith bl t

• Programmable pins mean that several of the same devices can share the same bus

• Unique address per device: fully fixed or with a programmable part through hardware pin(s)

• 112 different addresses max with the 7-bit format (others reserved)• Address allocation coordinated by the I2C-bus committee

• 10-bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5A4A3A2A1A0

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10 bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5A4A3A2A1A0

I2C Slave Address – 7bit Format

Consist of fixed address and hardware selectable address (optional), a total of 7-bitR/W bit is sometimes included as part of the address, and is called read or write address)

X X X X A2A1A0 R/W ACKS

p , )

Fixed Hardware Selectable pins

Only the addressed slave device acknowledges

7-bit address

R/W bit is included result in: odd address is always the“read” address, even address is always the“write” address

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

START Slave Address R/W ACK DATA NACK… DATAACK

RE-START/STOP

1 1 0 0 0 0 0 W

ACK/

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STOPSTOP

I2C Slave Address – 10bit Format

1 1 1 1 0 A A 0 ACK C

Consist of fixed command, 11110 and 10-bit address (fixed or hardware selectable)A write operation takes up two bytes

1 1 1 1 0 A9A8 0 A7A6A5A4A3A2A1A0ACK ACKS

Command Any 10-bit address slave devices may acknowledge

Only the addressed slave device acknowledges

Write

A read operation requires a two byte for write followed by a 1 byte read

1 1 1 1 0 A9A8 1

A read operation requires a two byte for write, followed by a 1 byte read

ACK1 1 1 1 0 A9A8 0 A7A6A5A4A3A2A1A0ACK ACK SrS

Write operation Commandp

Any 10-bit address slave devices may acknowledge

Only the addressed slave device acknowledges

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1st Clock Timing Diagram

First clock cycle is clock cycle after the START bit

START

First Clock

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First Clock

SCL, Serial Clock Timing Diagram

Falling edge of SCL signals the requirement to provide data on SDA

Rising edge of SCL signals the need to hold that data bitg g g

Clock period (T) = tCYCLE = 1/fSCL = tLOW + tHIGH + tf + tr

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Key numbers to keep in mindF t Hi h

Standard Mode

Fast Mode

Fast Mode Plus

High Speed Mode

Bit Rate (kb/s)

0 to 100 0 to 400 0 to 1000 0 to 1700 0 to 3400(kb/s)

Max Load (pF)

400 400 550 400 100

Rise time (ns)

1000 300 120 160 80

Rise Time

(ns)Noise

filter (ns)- 50 10 10 10

VDDVIH 0.7xVDD

Rise Time

GND

VIL 0.3xVDD0.4 V @ 3 mA Sink CurrentVOL 0.4 V @ 30 mA Sink Current (Fm+)

28

GND

SDA, Serial Data Timing Diagram

Normal data transition occurs when SCL is low

Data is evaluated when SCL is highg

SDA data changing state SDA evaluated

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Acknowledge (ACK)

Acknowledge bit occurs on the 9th SCL clock pulse

The transmitter and receiver behave as follows:The transmitter and receiver behave as follows:1. Transmitter releases SDA line after the 8th clock pulse2. Receiver acknowledges by pulling SDA low on the 9th clock pulse3. Transfer is aborted if SDA does not go low (no ACK) g ( )

SDA

No ACKHIGH

SDA

SCL

ACKLOW

9th SCL8th SCL

30

Acknowledge Example

31

Not Acknowledge (NACK)

Three Scenarios where there is no acknowledge taking place

1. The receiver being addressed is not present on the I2C busg p

2. The receiver is busy (cannot process the receiving information)

3. The master receiver wants to take control of SDA line

NACKHIGH

SDA

SCL

ACKLOW

9th SCL8th SCL

32

Not Acknowledge Example

33

Clock Stretch

A clock stretch is defined as the SCL line being pulled low – stretched –longer than its intended clock low period

Why a device stretches the clock? – A master performs clock stretch when it needs to slow down the clock in order to

accommodate a slower slave deviceA slave performs clock stretch when it needs to perform other function– A slave performs clock stretch when it needs to perform other function

Data is “DON’T CARE” when the clock is low

SDA

SCL

DON’T CARE

SCLClock stretch

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Multi-master S h i ti /A bit tiSynchronization/Arbitration

35

Clock Synchronization & Bus Arbitration

Multi-master environment requires clock synchronization and data arbitration

Masters synchronize on clock line – Result in new clock frequency = longest low + shortest high

Masters arbitrate on data line– Result in the losing master stop sending data– Losing master can continue to send SCL until the end the byte– Losing master can continue to send SCL until the end the byte– Data is not corrupted

VCC Master#2VCC Master#2

RpuRpu

Master#1 Slave Address#1

Slave Address#2

Master#1 Slave Address#1

Slave Address#2

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Address#1Address#2 Address#1Address#2

Clock Synchronization Timing Diagram

LOW period determined by the longest clock low period

Vdd

CLK 1 CLK 2

Mas ter 1 Mas ter 2VddVdd

CLK 1CLK 1 CLK 2CLK 2

Mas ter 1 Mas ter 2

HIGH period determined by shortest clock high period

CLK 1 CLK 2S CL

CLK 1CLK 1 CLK 2CLK 2S CL

1

2 3

4

2 3

37

Arbitration Timing Diagram

Two or more masters may generate a START condition at the same time

Arbitration is done on SDA while SCL is high - Slaves are not involved

Master 1 loses arbitrationDATA1 ≠SDA

Start command

“1” “0” “0” “1” “0” “1”

38

Bus Recovery Method

Problem:

Typical case is when a master fails during reading the slave deviceTypical case is when a master fails during reading the slave device

The SDA line is stuck low because the slave is stuck in the transmitter mode

Solution

Three methods to recover the bus:1) Use a hardware reset pin to reset the slave device (assuming the device ) p ( g

has a reset pin)2) Use a hardware self-timeout function such as SMBus timeout3) Use an I2C-bus recovery sequence to leave the “Slave-Transmitter” mode) y q

39

I2C-bus Recovery Sequence

An I2C-bus recovery sequence is done as follows:1) Send 9 clock pulses on SCL line while the master “keeps” the SDA line

high until the “Slave Transmitter” releases it including the time for the ACKhigh until the “Slave-Transmitter” releases it including the time for the ACK operation. “Keeping” SDA high during the ACK means that the “Master-Receiver” does not acknowledge the previous received byte

2) The “Slave-Transmitter” then goes in an idle state (mandatory when noacknowledge is received)

3) The master then sends a STOP command to initialize the bus

Slave releases SDA lineSlave held the line low

Slave releases SDA line

Slave becomes idle

40

Multi Master Mode - Clock SynchronizationVddMaster 1 Master 2

TL1 TH1

T1

CLK 2TL2, TH2

CLK 1TL1, TH1SCL

TL, TH

T2TL2 TH2

H1

Internal Counters count the Low and High times (TL1, TH1) and (TL2,

Count TH1

Count TL1

Counting TL1 done Wait State

TL2 still counting

CLK10

TH2)Count TH2Count TL2CLK2

0

Reset Counter High TH2Start Counting TL2

2 Counting TL2 doneStart Counting TH2SCL goes High

3

4

23

4SCL

0

TL = TL2 TH = TH1

• TL = longest TL = max (TL1, TL2 ,TLn )

T = shortest T = min (T T T )

Counting TH1 doneStart Counting TL1SCL goes Low

1 Start Counting TH1

Counting TH1 doneStart Counting TL1SCL goes Low

14

41

• TH = shortest TH = min (TH1, TH2,THn )

Multi Master Mode - Arbitration• Two or more masters may generate a START condition at the same time• Arbitration is done on SDA while SCL is HIGH - Slaves are not involved

Master 2 loses arbitration because DATA2 ≠ SDA

DATA10

Master 2 loses arbitration because DATA2 ≠ SDA

“0”

“1”

DATA20

SDA

1

“0”

SCL0

SDA0

SUMMARY: the master that sends a “1” while the other sends a “0” loses the arbitration

START “1” “0” “0” “1” “1” “0”

42

the arbitration

I2C b El i l Ch i iI2C-bus Electrical Characteristics

Subject / Department / AuthorSubject / Department / Author -

43

SDA/SCL Driver Architecture

SDA and SCL are open drain/collector– Required pull-up resistors to pull the line to logic “1”

Clock stretch is possible when a device is busy

Requires pull-up resistors2k 10 k2k to 10 kΩ

Open drain structure and bidirectional for SDA and/or SCL

SCL

SCL

10 pF Max

44

Max

Key Electrical Parameters

Standard Mode

Fast Mode

Fast Mode Plus

High Speed Mode

Bit Rate 0 t 100 0 t 400 0 t 1000 0 t 1700 0 t 3400

Bit Rate (kb/s)

0 to 100 0 to 400 0 to 1000 0 to 1700 0 to 3400

Max Load (pF)

40 400 560 400 100

Rise time 1000 300 120 160 80

0

Rise Time

(ns)1000 300 120 160 80

Noise filter (ns)

- 50 10 10 10

VDDVIH 70%VDD

Rise Time

GND

VIL 30%VDD0.4 V @ 3 mA Sink CurrentVOL

45

GND

Calculating Pull-up Resistors

1) RMIN < RPU < RMAX

VCC Master#2VCC Master#2

RPU

VDDMAX VOLMAX

RMIN

IOLMAX = 3mA IOLMAX = 6mA* IOLMAX = 30mA**

2) RMIN = (VDDMAX - VOLMAX) / IOLMAXVCC

Rpu

Master#2

Master#1 Slave Address#1

Slave Address#2

VCC

Rpu

Master#2

Master#1 Slave Address#1

Slave Address#2

3.6 V 0.4 V 1.1 kΩ 533 Ω 106 Ω

5.5 V 0.4 V 1.7 kΩ 850 Ω 170 ΩGlossary

RPU: Pull-up resistor

Address#1Address#2 Address#1Address#2

*With a buffer; **Fast mode Plus PU p

RMIN: Minimum pull-up resistor

RMAX: Maximum pull-up resistor

VDDMAX: Maximum supply rail

VOLMAX: Maximum output voltage lowMODE Frequency tr CMAX RMAX

3) RMAX * CMAX = 1.18*tr

With a buffer; Fast-mode Plus

VOLMAX: Maximum output voltage low

IOLMAX: Maximum sink current

CMAX: Maximum load capacitance

tr: Rise time

Standard 100 kHz 1000 ns 400 pF 2.96 kΩ

Fast Mode 400 kHz 300 ns 400 pF 885 Ω

Fast Mode Plus 1000 kHz 120 ns 560 pF 252 Ω

46

How to calculate I2C Pull-up Resistors?Minimum valueMinimum valueThere is a minimum resistor value determined by the I²C spec limit of 3 mA.R = (Vddmax – Volmax)/ 0.003AExample: using a 5±0 5 V bus: R (5 5V 0 4V)/ 0 003A 1 7 kΩExample: using a 5±0.5 V bus: R = (5.5V – 0.4V)/ 0.003A = 1.7 kΩ

Maximum valueDetermined by the I²C-bus rise time requirements:Determined by the I C bus rise time requirements:V(t1) = 0.3*Vdd = Vdd (1–1/et1/RC); then t1 = 0.3566749*RCV(t2) = 0.7*Vdd = Vdd (1–1/et2/RC); then t2 = 1.2039729*RC

t t2 t1 0 8472979*RCt = t2–t1 = 0.8472979*RCFor standard-mode I²C-bus: t = rise time = 1000ns (1 µs)

so RC = 1180.2 nsExample: at a bus load of 400 pF: Rmax = 2.95 kΩ

For fast-mode:I²C-bus rise time = 300 ns @ 400 pF: Rmax = 885 Ω

47

@ p max

How Do You Derive Rise Time for I2C-bus

I²C-bus rise time is determined as in the following :

1) V(t1) = 0.3*VDD = VDD (1–1/et1/RC) t1 = 0.3566749*RC ( EQ1)

2) V(t2) = 0.7*VDD = VDD (1–1/et2/RC) t2 = 1.2039729*RC ( EQ2)

3) Subtract EQ1 from EQ2 t rise time = t2–t1 = 0.8472979*RC or

R*C = 1 18*tR*C = 1.18*t rise time

VDD

V(t2)Rise Time

70%VDD

V(t1)

30%VDD0.4 V @ 3 mA Sink CurrentVOL

t1 t2 Time

48

Effects of Pull-up Resistors

Minimum pull-up resistor limits the maximum current sink that affects the voltage output low (VOL).the voltage output low (VOL).

– Increasing pull-up resistor above RMIN leads to decreasing VOL and higher noise marginDecreasing pull up resistor below R leads to increasing V and lower– Decreasing pull-up resistor below RMIN leads to increasing VOL and lower noise margin

Maximum pull-up resistor affects the rise time and speedp p p– Increasing pull-up resistor above RMAX leads to slower/possible rise time

violation or lower speed – Decreasing pull-up resistor below RMAX leads to faster rise time and speedDecreasing pull up resistor below RMAX leads to faster rise time and speed

49

Measurements using an Oscilloscope

50

Using Cursors to make measurements

Allows one to make i k tquick measurements

for and V∆ t∆

Handy in making roughHandy in making rough rise time measurements for I2C-bus

51

Effects of Pull-up ResistorsRise time for SDA and SCL lines using 9K pull up resistors

52

Effects of Pull-up ResistorsRise time for SDA and SCL lines using 2.2K pull up resistors

53

Effects of Pull-up ResistorsSide by side comparison of the difference in rise time using two different pull-up resistor values

54

Effects of Pull-up ResistorsRise time for SDA and SCL lines using 100K pull up resistors

Slow rise time, no stable logic high state.

55

Probing your I2C-bus

56

Passive Probe Basics

Passive probes make an attenuator circuit with the probe impedance and scope impedance

Probe9 MΩ Scope

1 MΩ1 MΩAttenuation ratio

1 M Ω /(9 MΩ +1MΩ)( )= 1/10

57

Importance of Oscilloscope Coupling

Signal is attenuated too much if the coupling is set incorrectly

P b Scope

Attenuation ratio50 Ω /(9M Ω +50 Ω) Probe

9 M ΩScope 50 Ω

50 Ω /(9M Ω 50 Ω)= 1/180,001

Most modern passive probes have a probe sense pin that mates with a probe sense ring on thepin that mates with a probe sense ring on the oscilloscope – this automatically sets the correct coupling and attenuation factor

58

Scope/Probe Impedance MatchingPassive probes have an adjustment that allows the user to tweak the impedance of the passive probe to match the impedance of the scope it is connected to, this low frequency adjustment results in improved pulse shapes on the oscilloscope displaypulse shapes on the oscilloscope display

59

Passive Probe Adjustment

All oscilloscopes have a “Cal Out” which provides a clean square wave for passive probe adjustment and compensation

Adjusting the capacitor in theAdjusting the capacitor in the probe allows the probe to be tuned for that scope and resulting in the good pulse shaperesulting in the good pulse shape shown below

60

Importance of ground lead length while probing

Pulse measured with

Not having proper ground connection, shows distorted signal

÷10 passive Probe

A: Without Ground LeadB: 50 cm Ground LeadC: 10 cm Ground Lead C 0 GD: BNC Direct Cable Connection(true signal shape)(true signal shape)

61

Exercise 1Verify understanding of the I²C bus protocoly g p

Subject / Department / AuthorSubject / Department / Author -

62

I2C-bus Building Blocks

I/O `Expander`

LED Blinker/ Dimmer DIP SwitchAD/DA

ConverterOther Slave

Color Mixing LED Driver

Bus Buffer, Voltage

Translator, Extender

VCC4 VCC5

VCC0

µCI²C in hardware

or software emulation

µCBus C

Master Selector

Multiplexer& Switch

8

VCC2

VCC1

Functions with I2C

I2C Bus ArchitectureDevices

Custom I2C

EEPROM LCD DriverReal Time

Clock / Calendar

Temperature Sensor

µCController

V

Custom I C hardware or software emulated

Other hardwareI2C

Bridge

SPIUART

VCC3

63

Which tools to help you win ?y

I2C Demoboards

Demo and Evaluation Boards

65

Evaluation/Demo Board ListOM# DescriptionOM# Description

OM6270 SPI/I2C to UART Bridge Demoboard (SC16IS750)

OM6271 SPI to I2C Master Bridge Demoboard (SC18IS600)

OM6272 UART to I2C Master Bridge Demoboard (SC18IM700)

OM6273 SPI/I2C to Dual UART/IRDA/GPIO Demoboard (SC16IS752)

OM6274 I2C to SPI Master Bridge Demoboard (SC18IS602)

OM6275 I2C 2005-1 Demo Board (15 I2C devices w/USB control & GUI)

OM6276 PCA9633 Demo Board (Four Color PWM LED Control with Microcontroller)

OM6277 PCA9564 Eval Board (I2C Master)

OM6278 I2C 2002-1A Eval Board (11 I2C devices w/printer port control & GUI)

OM6279 LED Dimmer Demo BoardOM6279 LED Dimmer Demo Board

OM6281 PCA9698 Demo Board (Advanced 40-bit GPIO with PCA9530 LED blinker)

OM6276 PCA9633 Demo Board (Four Color PWM LED Control)

OM6285 I2C 2002-1A Eval Board (without/printer port control & GUI)( p p )

OM6290 I2C –bus LCD driver evaluation board

OM10088 PCF8562 LCD Segment Display

More information: www ics nxp com/support/tools/interfaceMore information: www.ics.nxp.com/support/tools/interface

NXP Bridge IC – Demo Board KitsI2C/SPI slave to UART UART to I2C master SPI t I2C t I2C t SPI tI2C/SPI slave to UART UART to I2C master SPI to I2C master

SC16IS7xx SC18IM700 SC18IS600I2C to SPI master

SC18IS602

Kit i l d Kits includeKit i l d Kits include•Sample code: RS232 and NXP I2C devices•User Manual

Kits include

Key Benefit

•Sample code: SPI and NXP I2C devices•User Manual

Kits include

Key Benefit

•Sample code: RS232, RS485, and IrDA•User Manual

Kits include

Key Benefit

•Sample code: I2C and NXP SPI devices•User Manual

Kits include

Key Benefity

Easy interface to UART host and various I2C and GPIO devices. On-board I2C

y

Easy interface to SPI host and various I2C and GPIO devices. On-board I2C EEPROM and I2C LED

yEasy interface to I2C/SPI host and IrDA, RS232/RS485, and GPIO devices. Selectable I2C or SPI-

y

Easy interface to I2C host and SPI and GPIO devices.

Up to 4 SPI chip selectsEEPROM and I2C LED Dimmer

Dimmerbus interface Up to 5Mbps!

OM6270 – SC16IS750OM6273 – SC16IS752

OM6271 OM6272

Up to 4 SPI chip selects

OM6274OM6273 – SC16IS752

Experience the variety of I²C peripherals with the latest I²C Training Boardg

Fifteen different I²C devices on one board allows easy experimentation and training. (PCA9531, PCA9536, PCA9538, PCA9540B, PCA9541, PCA9543A, PCA9551, PCF8563, PCF8574, PCF85116-3, SA56004, SE98)

Add Extra I/O Ports, Temperature Sensors, LED Drivers, Real-time Clock, I²C Bus S it hiSwitchingUSB Connection to trial version (only devices on board and that fixed address is operational) Graphics Interface for Windows PC/Laptopwww.ics.nxp.com/support/boards/i2c20051/p ppTarget Board & USB based GUI (400 kHz) #OM6275

Get the color right with the single chip four color LED driver (R G B ?)four color LED driver (R G B ?)

Individual and Global PWM to set your perfect color and brightness or blink

I²C interface for easy connection to Micro or Baseband IC

Demo board with on board micro (LPC900) and FETs #OM6276Stand alone demo Board #OM6282

www.ics.nxp.com/support/boards/pca9633/www.ics.nxp.com/support/boards/pca9633/

Blink an LED without bit bangingDim and LED without burning a PWM on the MCUDim and LED without burning a PWM on the MCU

Two PWMs to map across 2,4,8,16 outputs– 25 mA per pin

I²C interface for easy connection to Micro or Baseband IC

Demo Board with on board micro #OM6279– PCA9533, PCA9531PCA9533, PCA9531– On-board NXP MCU demonstrates capabilities– www.ics.nxp.com/support/boards/leddemo

Easily Test and Demonstrate the PCA9698 40-Bit GPIO

Demonstrates a wide range of functions

1MHz Fast-mode Plus I2C-bus serial interface with 30mA drive

2.3 to 5.5V operation with 5.5V-tolerant I/O

40 configurable I/O pins that default to inputs at power-up

Designed for live insertion in PICMG applicationsDesigned for live insertion in PICMG applications

Onboard PCA9530 LED dimmer/blinker for LED applications

Low standby current

Demo board #OM6281

www.ics.nxp.com/support/boards/pca9698/

Train on many I²C peripherals using parallel printer port to PCprinter port to PC

Eleven different I²C devices on one board allows easy experimentation and training (LM75A, P82B96/PCA9600, PCA9501, PCA9515, PCA9543, PCA9550, PCA9551, PCA9554, PCA9555, PCA9561, PCF8582C-2)Add Extra I/O Ports, Temperature Sensors, LED Drivers, I²C Bus SwitchingAdd Extra I/O Ports, Temperature Sensors, LED Drivers, I C Bus SwitchingI²C Bus adapter uses parallel printer port for connection to full version (all devices and addresses operational) of Graphics Interface for Windows PC/Laptopwww.ics.nxp.com/support/boards/i2c20021/Target Board plus parallel printer port control (100 kHz) & GUI #OM6278Target Board plus parallel printer port control (100 kHz) & GUI #OM6278Target Board only #OM6285

NXP I2C-bus LCD driver evaluation board (OM6290)

Th NXP I2C b LCD h th di l h t ll d b I2C b LCDThe NXP I2C-bus LCD has three displays each controlled by an I2C-bus LCD driver.

The segment display has a backlight driven by LED driver PCA9633.

The board includes an NXP ARM7 microcontroller LPC2148

Demo board #OM6290

Easily drive a LCD Segment Display with a very small MCU and PCF8562small MCU and PCF8562

Good for a User Interface at the front panel of a systemScalable to match the complexity of the LCD displaySimple code using industry-standard 8051 coreEasily reprogram micro via USB adapter (#OM10083)http://www.teamfdi.com/products/lcddemo/lcddemo.shtmlDemo Board with on board micro #OM10088

MCU

PCF8562 LCD

“Glass”I²CMCULCD Driver

GlassI C

COG i tiCOG is an option

Easy Access to I2C Technical HelpThree easy ways to ask technical questions and obtain answers

Access I2C Discussion Forum from > www.nxp.com/i2c

CONTACT link on every Product Information Page

www nxp com/supportwww.nxp.com/support

Send e-mail directly to I2C.Support@nxp.com

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pp @ p

I2C Device Data Sheets, IBIS models Application Notes and Other InformationNotes and Other Information

Product familyProduct familydescriptionsline cardscross referencedata sheetsdata sheets

Link toapp notesmodelsmodelsuser guidesPLL designsoftwaredatasheets

www.nxp.com/i2c or www.nxp.com/i2clogic

datasheets

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Interface Products Internet SupportGeneral: http://www.nxp.com/support

I2C Control: http://www.nxp.com/i2cI2C.Support@nxp.com (E-mail Support)http://forums nxp com/forums (Forum)http://forums.nxp.com/forums (Forum)

All other Interface Productshttp://www.ics.nxp.com/interface/Interface.Support@nxp.com

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Questions?Questions?

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