IC Design Flow SASE

© Synopsys 2012 1

Digital IC Design

Victor Grimblatt

R&D Group Director

SASE 2012

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Agenda

Introduction

Electronic systems, an historic prospective

Synopsys Design Flow

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Introduction

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Consumers Driving “Smart” Electronics

1980 1990 2000 2010 2020

Pro

duct

Com

ple

xity /

Capabili

ties

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Mobile

0

20

40

60

80

100

2010 2011 2012 2013 2014 2015

Handset IC Market Value ($B)

0

3

6

9

12

15

2010 2011 2012 2013 2014 2015

Tablet IC Market Value ($B)

$38B to $109B in

non-memory ICs in 5 years!

Source IBS, February 2011

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19

90

19

92

19

94

19

96

19

98

20

00

20

02

20

04

20

06

20

08

20

10

20

12F

20

14F

Billio

ns

Microprocessor Sales $80 $70 $60 $50 $40 $30 $20 $10 $0

Source: Data Center Knowledge 2011; P. Otellini, Intel, Investor Meeting 2010

241.8 336.3

451.2 593.0

759.2

965.5

0

200

400

600

800

1,000

1,200

2010 2011F 2012F 2013F 2014F 2015F

IP T

raff

ic, E

xab

yte

s

Global IP Traffic

Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2011

Storage Manipulation

Creation Transportation

Data Access

Access

Access

0.8 1.227 1.8

7.91

0

2

4

6

8

10

2009 2010 2011 2012 2013 2014 2015

Data Storage

Source: Wikipedia, 2011; Google, Stockholder Meeting 2010

Cloud Infrastructure:

Data, Data, Data

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Smart Everything

Lines of

Code

SW & E/E

% Vehicle

Cost

Software

Sensors

Microprocessors

Storage

Communication

“Smart”

33% 1M 1990

1970 <9% 100K

2010 >40% 100M

Grid Buildings Cars Toasters Dogs…?

Exam

ple

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Electronic Content in Systems Increases

0%

5%

10%

15%

20%

25%

30%

Se

mic

on

du

cto

r C

on

ten

t

Source: ST, TI, IC Insights

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Applications

Electronics

~$1.31T

Semi

$320.8B

EDA & IP

$8.4B

EDA + IP

Sooner

Cheaper

Better

1

2

3

Drivers of Innovation

and Differentiation

Source: IC Insights, VDC Research,

Synopsys Estimates

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What Drives the Drivers?

Power

Performance

Cloud

Infrastructure

Power/Cost/Perf.

Integration

“Smart”

Performance

Power

Mobile

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Advanced Designs and Tapeouts

Source: Synopsys Global Technical Services

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Leading the Way at 32/28nm Design


> 370 32/28nm Active Designs

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≥250nm

180nm

130nm

90nm

65/55nm

45/40nm

32/28nm

22/20nm

<20nm

0%

25%

50%

75%

100%

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011

Advanced Design Trends

56% of Respondents Currently Designing at 45nm or Below

Source: 2011 Synopsys Global User Survey

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Advanced Design Trends

3%

5% 6% 5%

13%

20%

31%

13%

4%

0%

5%

10%

15%

20%

25%

30%

35%

≥250nm 180 130 90 65/55 45/40 32/28 22/20 <20

Last Current Next

Power Performance Requirements Drive Node Migrations


48% of “Next Designs” ≤ 32nm!

“Next Design” is this Year!

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≤50MHz

51-100MHz

101-200MHz

201-300MHz

301-400MHz

401-500MHz

751MHz-1GHz

1-2GHz

>2GHz

0%

20%

40%

60%

80%

100%

2004 2005 2006 2007 2008 2009 2010 2011

42%

Clock Frequency Trends

Frequency is Increasing Over 1GHz


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13% 12% 13%

6%

9% 9%

6%

9%

7%

16%

28%

13% 12%

7% 6%

10%

5% 4% 6%

10%

0%

10%

20%

30%

1-100K 101-500K 501K-1M 1-2M 2-5M 5-10M 10-20M 20-50M 50-100M >100M

Logic Memory

Designs Are Growing More Complex

Memory = 48% of Gate Count (on average)


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$-

$0.50

$1.00

$1.50

$2.00

$2.50

1 3 5 7 9 11 13 15 17 19 21 23 25 27

$M

Months

App-Specific SW

Low-Level SW

OS Support

Design Management

Post-silicon Validation

Masks

Physical Design

RTL Verification

RTL Development

Spec Development

IP Qualification

Hardware/Software Development Costs

Software Is Half of Time-to-Market

Source: IBS, Synopsys

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Electronic Systems, an Historic

Prospective

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Key Innovations in Electronics:

Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

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Audio/Video

2005

Sonos

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Computers & Communications

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Going to a satellite not so far away! Apollo Guidance Computer, ~100 Microns, MIT

Source: MIT, 1961

1961

10-3 MIPS

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Key Innovations in Semiconductors

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Once Upon a Time …

April, 1961 first integrated circuit developed by

Robert Noyce, from Fairchild Semiconductor

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A Big Event … 4004, 10 Microns, Intel

1971

10-1 MIPS

Source: 4004, Intel, 1971

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A 10,000X Improvement, Thanks To… “A Computer Code Entitled SCALD […] Speeds the Job”

Source: Lawrence Livermore National Laboratory, Newsline, January 10th, 1979

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1961-1981, A 10,000X Improvement… S-1 Supercomputer, ~3 Microns, LLNL

Source: Lawrence Livermore National Laboratory, 1983

1981

10 MIPS

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Time Flies Away … DEC Alpha 21064, 64bits, 750 nm CMOS, 200Mhz

Source: Wikimedia Commons; Courtesy of A. Domic

1991

300

DMIPS

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Another Time Stamp … Itanium, 180 Nanometers, Intel

Source: Intel, 2001

2001

~25 GOPS

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1961-2011, A 100,000,000X Improvement… Ivy Bridge, 22 Nanometers, Intel

~160mm2, 1.4B transistors, 2.5-4GHz, 45-80W

Source: M. Bohr, Intel, IDF 2011; S. Siers, Intel, ISSCC 2012; Sandra 2011

2011

100 GOPS

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The Wireless Side in 2011:

ST AP9540

62

SGX544 SIA

MMDSP

A9

MMDSP

SVA M

CD

E

HVA G1

DDR1 PHY

DD

R0 P

HY

Peri

ph

3

Peri

ph

1

Periph2

C2C

DDR

CTRL0

DDR

CTRL1

CSI

DSS

• Application processor for

smart phones and tablets

– Dual ARM Cortex A9

@ 1.85GHz

– Imagination GPU SGX544

@ 500MHz

– Dual 32 bits LPDDR2

@ 533MHz

• 32nm technology

– 10 metal layers

• Advanced power

management

– 10+ switchable power

domains with multi-

voltage/multi-supply

scenarios

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Area = 1

Area = 0.5

Gordon E. Moore’s Law Twice the Number of Transistors for the Same Price,

Every Two Years

“The complexity for minimum component

costs has increased at a rate of roughly a

factor of two per year ... Certainly over

the short term this rate can be expected to

continue, if not to increase. Over the

longer term, the rate of increase is a bit

more uncertain, although there is no

reason to believe it will not remain nearly

constant for at least 10 years.” Gordon E.

Moore, Electronic Magazine, April 19th,

1965

The Scaling Factor

0.5 = ~0.7

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Ley de Moore

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LO

G2 O

F T

HE

NU

MB

ER

OF

CO

MP

ON

EN

TS

PE

R IN

TE

GR

AT

ED

FU

NC

TIO

N

Fuente: Electronics, 19 Abril, 1965

http://download.intel.com/museum/Moores_Law/Articles-

Press_releases/Gordon_Moore_1965_Article.pdf

http://download.intel.com/museum/Moores_Law/Articles-Press_releases/Gordon_Moore_1965_Article.pdf



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Wafer 1” – 1959

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Wafer 300 mm

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Proyecciones para el 2000 en 1975

Moore no siempre tuvo

razón

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Design - Layout

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EDA Back Then… CALMAGRAPHIC, Calma

Source: D.E. Weisberg, The Engineering Design Revolution, 2008 (www.cadhistory.net)

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Design - Layout

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Plotter

1970 – From Manual Layout to Manufacturing

• Applicon- PCB & IC Digitizing, CAM*

• ComputerVision- Wiring, Mapping, Documentation, PCB

• David Mann output for IC masks

• Gerber for PCB artwork

• Autotrol for digitizing

Mainframe-500 lbs 128k; 8-16 bit

33 MB Disk

Keyboard, Tablet and CRT

Digitizing Table/Tablet

Mag Tape-Output

Photo-Mask Generation

* Computer Aided Manufacturing

The Age of

the Gods

SENSES

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Design - Layout

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Basic Early CAD Applications

Gridded

Pencil IC/PCB

Layouts

Artwork for

Manufacturing

Primitive Database

Card Deck from Keypunch

Schematic Simulation

Analog

01110010 00011001 10010110 00011001 01110010

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Standard Cells & Channel Routing

Source: GE Avionics, 1968

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Technology Or… Art?

Source: Intel & MoMA, 1974

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Design - Synthesis

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Design - Synthesis

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Design - Synthesis

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Design - Fab

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Design - Fab

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Design - Verification

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1980s

The Key Components of Modern EDA

Podem X

Scan Test

BBL &

Timberwolf

VHDL &

Verilog

Interconnect

modeling

Logic

Synthesis

Framework

DRC

& LVS

Dracula

Mead &

Conway

BDD

Hardware

Emulation

Flex

Cathedral

Ptolemy

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Some Key Contributors to EDA

Verilog

Commercial

Industry

System,

Layout

Place &

Route Logic

Synthesis

High-Level

Design DRC/LVS Multi

Discipline

Innovators

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Design Process

Design: specify and enter the

design intent

Implement: refine the design

through all phases

Verify: verify the correctness of

design and implementation

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Bottom – up / Top – down

• Bottom – up

– Start from simple modules

– Goes to complex modules

– Suitable to create small parts that will be reused

• Top – down

– Start from complex modules

– Goes to simple modules

– Suitable for big systems

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Bottom – up / Top – down

Complex system

Module (one function)

Register and gates

Transistors

Top – down Bottom – up

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Front End

Architecture

Functional Verification

RTL Design/Logic

Synthesis

Physical Design Design

Integrity

process begin wait until not CLOCK'stable and CLOCK=1; if(ENABLE='1') then TOGGLE<= not TOGGLE; end if; end process;

IC Design . . . A Simplified Explanation

Back End

Fabrication

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The Front End

Architecture:

• Key Algorithms (filtering, for example)

• Amount of on-chip Memories, sizes?

• How many Integer Proc Units?

RTL: Register Transfer Language

• Verilog (1988), VHDL, SystemVerilog: an executable spec for the chip, amounting to over a million lines of code

• Lots of simulations to verify the spec (literally billions of cycles)

• Timing constraints, clock definitions, etc

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The Front End

Logic Design: convert the RTL to logic gates (NAND-NORs, NOTs, Registers)

• A manual process in the past, still mostly manual for Analog

• Logic Synthesis (1989): automate the process

• Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc, etc.

• End point is a “netlist”, meaning a set of logic gates and their connections. A large netlist is in the 10s of millions of gates

• Can be simulated or “formally verified” versus the RTL.

• Key technique: how do you prove that two logic equations are equivalent?

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The Back End

Floorplanning

• Where do we place the large blocks? Where do we place the “random” logic and “structured blocks”? A combination of manual and automated approaches is used

• Need to keep connections short to meet timing, but also cannot “congest” the design too much or we cannot complete the connections

• Note that connections do have R and C (to substrate and coupling between wires) so they introduce delay! Meeting timing can be very difficult!

• The Power and Ground lines usually get decided here

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The Back End

Placement:

• Now we need to complete the exact details of where each block and gate will be

• Automation has been a key for many years (1980). A block may contain hundreds of thousands of cells, so it is very hard problem: minimize area, be routable and meet timing

• Note may have to add logic: repeaters to restore signals a key example

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The Back End

Routing

• Complete all the connections!

• But, need to meet timing and keep signal integrity. This also involve separating some wires, for example, to avoid bad couplings

• Automation is the norm here (1980)

Verification:

• Spacing and sizing rules are checked for all polygons (1980)

• Parasitics are extracted, netlists back annotated and time analyzed using static techniques (1990)

• Manufacturing requires complicated rules, such as wire density been “uniform”

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Design Goes to Fabrication

Sounds simple, but have a host of

very hard problems to solve!

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Fabrication

Mask fabrication

Wafer fabrication

Wafer testing

Assembly and packaging

IC test

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…the steps you take to design a chip!

What’s a design flow?

Technology

Process

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on

Jibber jabber jibber

just jawing

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Ya'll com back

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yada yada

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on and on


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Blah blah blah

yada yada

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yidie yadie

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on and on


just jawing

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Gate-level

netlist

Testbench

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

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Ya'll com back

Blah blah blah

yada yada

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yidie yadie

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on and on


just jawing

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Blah blah blah

yada yada

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yidie yadie

So on and so forth

on and on


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Specification

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

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Blah blah blah

yada yada

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yidie yadie

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on and on


just jawing

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Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

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Scripts

Initial constraints

System

Analysis System Studio

Logic Modeling

Select

Architecture

Module Compiler

Models / IP Library Compiler

DesignWare Library

VERA

RTL Verification

VCS-MX

ATPG

TetraMAX

Synthesis

Design Compiler

Power Compiler

DFT Compiler

Gate-level

verification

VCS-MX

Magellan

Formality

PrimeTime

PrimePower

Place & Route

Physical Compiler

Astro

Links-to-

Layout Design Planning

PrimeTime

NanoSim

HSPICE

Post-Route

Verification

Physical Data

Creation

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

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yada yada

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on and on


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Blah blah blah

yada yada

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yidie yadie

So on and so forth

on and on


just jawing

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Physical Compiler

JupiterXT

Proteus

Physical Design

Checks STAR-RCXT

Hercules

RTL Gates

Design

Constraints

Mask Writer

CATS

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Technology

Process

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

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Gate-level

netlist

Testbench

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

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Specification

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Scripts

Initial constraints

System

Analysis System Studio

Logic Modeling

Select

Architecture

Module Compiler

Models / IP Library Compiler

DesignWare Library

VERA

RTL Verification

VCS-MX

ATPG

TetraMAX

Synthesis

Design Compiler

Power Compiler

DFT Compiler

Gate-level

verification

VCS-MX

Magellan

Formality

PrimeTime

PrimePower

Place & Route

Physical Compiler

Astro

Links-to-

Layout Design Planning

PrimeTime

NanoSim

HSPICE

Post-Route

Verification

Physical Data

Creation

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back

Blah blah blah

yada yada

Blah blah blah

yidie yadie

So on and so forth

on and on


just jawing

Yackety yack

Ya'll com back GDSII

Physical Compiler

JupiterXT

Proteus

Physical Design

Checks STAR-RCXT

Hercules

RTL Gates

Design

Constraints

Mask Writer

CATS

Design Implementation

Design for Manufacturing

Verification

© Synopsys 2012 100

Systems

Silicon

SoC

Manufacturing

System Design

Verification Implementation IP


Classic IC Design Flow

Architectural choices, RTL compilation and simulation (VCS)

Logic synthesis (Design Compiler)

Formal verification (Formality)

Generation of test patterns (TetraMAX)

Physical design (IC Compiler)

Physical verification (Hercules)

Layout parasitics extraction (StarRC)

SPICE level simulation of completed design (HSPICE)



Architectural choices, RTL Compilation and Simulation

(VCS)


VCS Overview

VCS supports multiple languages

• Verilog

• VHDL

• C/C++

• SystemC

• SystemVerilog

• OpenVera

• Analog

Intuitive GUI help find bugs quickly

• Assertions

• Testbench

• Coverage

• Post-simulation analysis


VCS Features

The most used features are:

• Tracing the Cause of Failed Assertion

• Trace drivers and loads of a signal at any time to see the drivers and loads that caused a value change and see all the drivers/loads that possibly contributed to a signal value.

RTL and Gate Signal Comparison

Highlighting the net in gate-level schematic and Verilog



Logic Synthesis

(Design Compiler)


Introduction to Design Compiler

Design Compiler performs logic synthesis and optimization of design

• Synthesizes HDL designs into optimized technology-dependent gate-level designs.

• Results in smallest and fastest logical representation of a given function

• Design Compiler supports a wide range of flat and hierarchical design styles

• Combinational and sequential designs can be optimized for

• timing

• area

• power


DC and Design Flow

HDL

Design Compiler

Timing & power

analysis

Formal verification

Optimized

gate-level netlist

Place & route

Constraints

Technology

Library

IP DesignWare

Library

Symbol Library

SDF

PDEF

Back-annotation

Timing

optimization

Datapath

optimization

Power

optimization

Area

optimization

Test

synthesis

Timing

closure


Basic Synthesis Flow

Design rule constraints set_max_transition

set_max_fanout

set_max_capacitance

Design optimization constraints create_clock

set_clock_latency

set_propagated_clock

set_clock_uncertaintly

set_clock_transition

set_input_delay

set_output_delay

set_max_area

compile

check_design

report_area

report_constraint

report_timing

write

Develop HDL files

Specify libraries

Read design

Define design environment

Set design constraints

Optimize the design

Analyze and resolve design problems

Save the design database


Design Compiler Input and Output Files

Design

Compiler

Design source

Code

Verilog(.v )

VHDL (.vhd)

Synthesis

scripts (.tcl)

Reports and logs

(text formats)

Design database

(.db - Synopsys internal

database format)

Design

constraints

(.con, .sdc)

Gate level Verilog description


Design for Test

Synopsys' design-for-test (DFT) synthesis solution (DFT Compiler) – enables scan insertion within Design Compiler

DFT Compiler's integration with Design Compiler ensures DFT with optimization of area, power, and timing constraints, and predictable timing closure of physically optimized scan designs.


DFT Key Features

One-pass test synthesis

Comprehensive RTL and gate-level DFT design rule checking

Rapid scan synthesis

Adaptive scan technology

Hierarchical scan synthesis

Observe point insertion

Automatic fixing of scan violations (autoFix)

Location-based scan ordering

Timing-based scan ordering



Formal Verification

(Formality)


Formality Introduction

Formality checks whether two designs are functionally equivalent or not

Its purpose is to detect unexpected differences that may have been introduced into a design during development.

Formality

Design level 1 Design level 2 Design process

Equivalent

Yes/No ?


Key Concepts

Compare Point

• Primary output of a circuit

• Registers within a circuit

• An input to black boxes within circuit

Logic Cone

• A block of combinational logic which drives a compare point


Equivalence Checking Verification Process

Equivalence checking is a four-phase process:

• Reading and elaborating language descriptions into logical representations

• Setting up prompt for verification

• Mapping of corresponding compare points between pairs of designs (Matching)

• Comparison of logic cones that drive the compare points (Verification)


Input Files of Formality

Formality supports the following input formats:

Input formats Command

Verilog (synthesizable subset) - read_verilog

Verilog (simulation libraries) - read_verilog -vcs

VHDL (synthesizable subset) - read_vhdl

EDIF - read_edif

Synopsys binary files - read_db, read_ddc, read_mdb (*)


Formality Flow Overview

Guidance (Loading of automated setup file)

• The purpose of automated file (.svf) is to help Formality process design changes caused by other tools, which it should have access to as the changes are made.

Referencing (Specifying the reference design)

• The reference design is the design against which the transformed (implementation) design is compared.

Implementation (Specifying the implementation design)

• This is the changed design. It is the design correctness that needs to be verified.

Matching (Matching compare points)

• Process of aligning compare points between two designs.

Verification (Verify the Designs)

• Process of proving or disproving that compare points are equivalent (have same functionality).

Debug

• During debug the user should determined where and why the comparison results were unsuccessful.



Generation of Test Patterns

(TetraMAX)


Introduction

TetraMAX is a high-speed, high-capacity automatic test pattern generation (ATPG) tool.

It can generate test patterns that maximize test coverage while using a minimum number of test vectors for a wide variety of design types and design flows.

It is well suited for designs of all sizes up to millions of gates.


ATPG Modes

Basic-Scan ATPG, an efficient combinational-only mode for full-scan designs

Fast-Sequential ATPG for limited support of partial-scan designs

Full-Sequential ATPG for maximum test coverage in partial-scan designs.


Design Flow Using DFT Compiler and

TetraMAX

Design for test

Writing test protocol

TetraMAX ATPG

Verilog library

STIL test protocol file

Design Compiler

Compiled, scanned netlist

HDL netlist


TetraMAX Design Flow

STL test protocol file

Perform test design rule

checking(DRC)

Pre-process netlist

Read netlist

Build the model

Prepare to run ATPG

Run ATPG

Review test coverage

Save test patterns

Test protocol

Read Library

Re-run ATPG

Netlist

Models


Steps of Running TetraMAX

Reading the netlist

Reading Verilog library models

Building the ATPG model

Performing Test Design Rule Checking (Test DRC)

Generating test protocols


Test Design Rule Checking

Test DRC checks for the following conditions:

Whether the scan chains inputs and outputs are logically connected

Whether all the clocks and asynchronous set/reset pins connected to scan chain flip-flops are controlled only by primary input ports

Whether the clocks/sets/resets are off when you switch from normal mode to scan shift mode and again when you switch back to normal mode

Whether any internal multiple-driver nets can be in contention



Static Timing Analysis of Test Patterns

(PrimeTime)


Introduction

PrimeTime is a full-chip, gate-level static timing analysis tool that is an essential part of the design and analysis flow for today's large chip designs.

PrimeTime validates the timing performance of a design by checking all possible paths for timing violations, without using logic simulation or test vectors.


PrimeTime Inputs and Outputs

SDF

Gate-level

netlist Libraries

Parasitics

Initial timing

reports

Restore session in

PrimeTime for further

debugging

PrimeTime

Saved

session

Design

Constraints


Using PrimeTime in Physical Synthesis

Flow

RTL

description

PrimeTime

(Static Timing Analysis)

Synthesis

Place & Route

.db

.tcl

.sdc

.pt

Command-specified

conditions

Cell delays, transition

times, capacitance,

wire load models,

design rules,

operating conditions

Timing constraints for

resynthesis and logic

optimization

.lcctcl, .sdc

.db, Verilog, VHDL

Design data

.sdf

Path constraints

Delay data; detailed

parasitic data for

back-annotation

.sdf; RSPF, DSPF, SPEF, SBPF

Design sign-off

Gate-level

description

Chip layout

description

Technology

library

Timing

models

.db, interface logic

models, extracted

timing models



Physical Design

(IC Compiler)


Input and Output Files of IC Compiler

Milkyway Ref

library

Tech file

.tf

TluPlus,

.map

.db

Tech file

.tf

TluPlus,

.map

Cell Library

(.db)

Netlist

(.v, .ddc)

IC Compiler

Verilog

(.v)

GDSII

(.gds)

Standard

Parasitics

Exchange

Format

(.spef)


IC Compiler Design Flow

Data preparation

Floorplanning

Power Planning

Invoke ICC

Placement

Clock Tree Synthesis

Routing

Finishing

Results (.v, .gds, .spef)


Physical Design Steps (1)

Data preparation

• Milkyway design library creation, logic libraries setup and parasitic models setup, design import.

Floorplanning

• Setting up the core area, top-level ports, and placement sites.

Power Planning

• Rectangular rings creation, power straps creation, etc.

Core Placement and Optimization

• During the placement phase the design's standard cells will be automatically placed in horizontal placement rows.

• Allows following optimizations: power, optimize_dft, effort, etc


Physical Design Steps (2)

Core Clock Tree Synthesis and Optimization

• During clock tree synthesis, IC Compiler builds clock trees that meet the clock tree design rule constraints while balancing the loads and minimizing the clock skew. Allows the following options: area_recovery, power, optimize_dft, only_cts, etc.

Core Routing and Optimization

• This command performs simultaneous routing and postroute optimization on the current design. Allows following optimizations: power, size_only, stage, only_hold_time, only_design_rule etc.

Check DRC (Design Rule Checking) and LVS (layout vs. schematic)

Export the design

• Allows following formats: Verilog ,GDS format etc.



Physical Verification

(Hercules)


Introduction

Hercules is a hierarchical physical verification tool that performs design rule checking (DRC) and layout vs. schematic (LVS) on IC design.


Input Files of Hercules

Hercules uses several input files to perform DRC, LVS, LPE and ERC design verification. These input files are:

• Database

• Runset file

• Schematic netlist

The primary input file is the runset file.


Design Database

In the beginning of a Hercules run, primary group files are created that consist of one file per layer listed in the ASSIGN section of the runset file.

Read different design databases using:

• GDSII

• GDSOUT

• OASIS

• Milkyway


Runset File

Runset file is a control file that instructs Hercules where to find input data, which checks to perform and where to write output files.

Separate runsets are typically created for DRC and LVS.

• A DRC Runset instructs Hercules to check layout files for errors.

• A LVS Runset instructs Hercules to compare the layout netlist to the schematic netlist of a design.


Schematic Netlist

The schematic Netlist file is used during LVS comparison. It provides complete net information with each cell.

If schematic netlist is in CDL, NetTran will translate it to Hercules format.

nettran –verilog Johnson_count.v –cdl-a-cdl-s-sp-S-verilog-b1 VDD –verilog-b0 VSS\

-rootCell Johnson_count –sp ./saed90nm.cdl –outName Johnson_count.sp


Netlist Translation

Hercules uses the NetTran utility to translate the netlist

between different formats. (e.g. Verilog to SPICE, SPICE to Hercules netlist format)

7/14/10

INPUT

OUTPUT

SPICE SPICE

CDL Verilog

Verilog NetTran NetTran EDIF

EDIF EDIF3

EDIF3 Hercules

(default)

Hercules

Silos

Hercules

Netlist


DRC Flow

Hercules

(DRC run)

Input DRC Runset

runset.ev Physical

database

Output Summary files

(Error database)


LVS Flow

Hercules

(LVSrun)

Input LVS Runset

runset.ev Physical

database

Output Summary files

(Error database)



Layout Parasitics Extraction

(StarRC)


StarRC Overview

StarRC is a layout parasitic extraction tool. StarRC can be used at any physical design cycle stage to extract accurate parasitics.

StarRC reads OpenAccess, Milkyway, LEF/DEF or Hercules connected databases directly, without external processing.

Extracted parasitics can be written into the Synopsys centralized Milkyway database for use by analysis and optimization tools.

Because StarRC gracefully handles designs with layout versus schematic (LVS) violations, including opens and shorts, timing convergence can be ensured before the physical verification cycle begins.


Inputs and Outputs of StarRC

• TCAD_GRD_FILE -File containing the modeled layers of a circuit.

• MAPPING_FILE-File containing physical layer mapping information between the

input database and the specified TCAD_GRD_FILE

• star_cmd -ASCII file containing StarRC commands that controls extraction functions

StarRC .spf

TCAD_GRD_FILE saed90nm_9lm.nxtgrd

MAPPING_FILE tech2itf.map

star_cmd rcx_cmd


Input and Output Formats of StarRC

StarRC supports these industry-standard formats:

Input formats

• LEF(Layout Exchange Format)/DEF(Design Exchange Format)

• GDSII

• Milkyway

Output Netlist Formats

• SPICE

• Synopsys Binary Parasitic Format (SBPF)

• Standard Parasitic Exchange Format (SPEF)

• Detailed Standard Parasitic Format (DSPF)

StarRC accepts input from GDSII, LEF/DEF, and IC Compiler formats.


StarRC Extraction Flow

Milkyway

database GDSII OR

Schematic

Netlist

Physical Database

Technology data

(layer physical information)

*.nxtgrd

Mapping file (used to map

layers used in StarRC to

technology layers)

StarRC

Parasitic Netlist

StarRC Command File



SPICE-level Simulation of Completed Design

(HSPICE)


HSPICE Features

HSPICE supports:

• Analog/RF/mixed-signal IC Design

• Verilog-A Behavioral Modeling

• Design For Yield- Process Variability and MosRa Device Reliability Analysis

• Transient Noise Analysis

• Cell and Memory Characterization


HSPICE

Waveforms

(*.tr)

Measurement Results

(*.mt)

Netlist

Measure

Analyze type

Options

Model file

Input and Output Files of HSPICE


Synopsys Design Flow Architectural choices, RTL compilation and simulation

(VCS)

Logic synthesis (Design Compiler)

Formal verification (Formality)

Generation of test patterns (TetraMAX)

Physical design (IC Compiler)

Physical Verification (Hercules)

Layout Parasitics Extraction (StarRC)

SPICE-level simulation of completed design (HSPICE)


Thank You

Documents

IC Design Flow SASE